JPS59501762A - 直接メモリアクセス・インタ−フエイス装置 - Google Patents

直接メモリアクセス・インタ−フエイス装置

Info

Publication number
JPS59501762A
JPS59501762A JP58503053A JP50305383A JPS59501762A JP S59501762 A JPS59501762 A JP S59501762A JP 58503053 A JP58503053 A JP 58503053A JP 50305383 A JP50305383 A JP 50305383A JP S59501762 A JPS59501762 A JP S59501762A
Authority
JP
Japan
Prior art keywords
data
memory
bus
address
host processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58503053A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0420497B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
ピ−タ−ソン・ト−マス・アンドリユ−
Original Assignee
ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド filed Critical ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド
Publication of JPS59501762A publication Critical patent/JPS59501762A/ja
Publication of JPH0420497B2 publication Critical patent/JPH0420497B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Computer And Data Communications (AREA)
JP58503053A 1982-09-30 1983-09-09 直接メモリアクセス・インタ−フエイス装置 Granted JPS59501762A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US428681 1982-09-30
US06/428,681 US4538224A (en) 1982-09-30 1982-09-30 Direct memory access peripheral unit controller

Publications (2)

Publication Number Publication Date
JPS59501762A true JPS59501762A (ja) 1984-10-18
JPH0420497B2 JPH0420497B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-04-03

Family

ID=23699923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58503053A Granted JPS59501762A (ja) 1982-09-30 1983-09-09 直接メモリアクセス・インタ−フエイス装置

Country Status (7)

Country Link
US (1) US4538224A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0120889B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS59501762A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1194608A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3374965D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB2128000B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1984001449A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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US4918597A (en) * 1984-12-14 1990-04-17 Alcatel Usa Corp. Adaptive interface for transferring segmented message between device and microcomputer on line division multiplexed bus
US4750107A (en) * 1985-01-07 1988-06-07 Unisys Corporation Printer-tape data link processor with DMA slave controller which automatically switches between dual output control data chomels
US4821180A (en) * 1985-02-25 1989-04-11 Itt Corporation Device interface controller for intercepting communication between a microcomputer and peripheral devices to control data transfers
US4747047A (en) * 1985-12-06 1988-05-24 Unisys Corporation Data transfer system using two peripheral controllers to access dual-ported data storage units
US4847750A (en) * 1986-02-13 1989-07-11 Intelligent Instrumentation, Inc. Peripheral DMA controller for data acquisition system
US5151999A (en) * 1986-03-31 1992-09-29 Wang Laboratories, Inc. Serial communications controller for transfer of successive data frames with storage of supplemental data and word counts
US4942515A (en) * 1986-03-31 1990-07-17 Wang Laboratories, Inc. Serial communications controller with FIFO register for storing supplemental data and counter for counting number of words within each transferred frame
US4740909A (en) * 1986-04-28 1988-04-26 The United States Of America As Represented By The Secretary Of The Air Force Real time data reduction system standard interface unit
US4823305A (en) * 1986-07-18 1989-04-18 Chrysler Motors Corporation Serial data direct memory access system
JPH0744567B2 (ja) * 1986-08-27 1995-05-15 日産自動車株式会社 通信インタ−フエイス装置
US4779190A (en) * 1986-12-03 1988-10-18 Ncr Corporation Communication bus interface
US5241661A (en) * 1987-03-27 1993-08-31 International Business Machines Corporation DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter
EP0313668B1 (en) * 1987-05-06 1997-08-06 Fujitsu Ten, Ltd. Data transfer device
AU622626B2 (en) * 1987-06-03 1992-04-16 Sony Corporation Method of processing data
US5367688A (en) * 1987-09-04 1994-11-22 Digital Equipment Corporation Boot system for distributed digital data processing system
US5136718A (en) * 1987-09-04 1992-08-04 Digital Equipment Corporation Communications arrangement for digital data processing system employing heterogeneous multiple processing nodes
JPS6470858A (en) * 1987-09-11 1989-03-16 Hitachi Ltd Data transfer system
US5025383A (en) * 1988-01-22 1991-06-18 Fme Corporation Postage meter transparent I/O interface
JP2745521B2 (ja) * 1988-02-23 1998-04-28 株式会社日立製作所 フレーム送信方法
US5003463A (en) * 1988-06-30 1991-03-26 Wang Laboratories, Inc. Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
US5261057A (en) * 1988-06-30 1993-11-09 Wang Laboratories, Inc. I/O bus to system interface
US5253345A (en) * 1988-07-07 1993-10-12 Sears, Roebuck & Co. Point of sale register system
US5303236A (en) * 1988-08-26 1994-04-12 Hitachi, Ltd. Signalling apparatus for use in an ATM switching system
US5239636A (en) * 1988-09-09 1993-08-24 Advanced Micro Devices, Inc. Buffer memory subsystem for peripheral controllers
US5007012A (en) * 1988-09-09 1991-04-09 Advanced Micro Devices, Inc. Fly-by data transfer system
US4935868A (en) * 1988-11-28 1990-06-19 Ncr Corporation Multiple port bus interface controller with slave bus
US5243686A (en) * 1988-12-09 1993-09-07 Oki Electric Industry Co., Ltd. Multi-stage linear predictive analysis method for feature extraction from acoustic signals
US5274795A (en) * 1989-08-18 1993-12-28 Schlumberger Technology Corporation Peripheral I/O bus and programmable bus interface for computer data acquisition
CA2050507C (en) * 1990-10-26 1999-07-13 Lane Jordon Abrams Message-oriented bank controller interface
DE69130667T2 (de) * 1990-12-06 1999-05-06 Tandberg Data Asa, Oslo Datenspeicherungssystem mit auswechselbaren Medien zum Laden eines Steuerprogrammes von den auswechselbaren Medien
US5701417A (en) * 1991-03-27 1997-12-23 Microstar Laboratories Method and apparatus for providing initial instructions through a communications interface in a multiple computer system
US5970251A (en) * 1994-06-16 1999-10-19 Robert Bosch Gmbh Process for optimizing program parts for motor vehicle controllers
US5727184A (en) * 1994-06-27 1998-03-10 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
US5794014A (en) * 1994-06-27 1998-08-11 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
DE19504488C1 (de) * 1995-02-10 1996-06-20 Siemens Ag Verfahren zur Initialisierung von peripheren Einrichtungen durch eine programmgesteuerte Zentraleinrichttung eines Kommunikationssystems
WO1997015011A1 (en) * 1995-10-18 1997-04-24 Sierra Semiconductor Corporation Method and apparatus for interfacing devices used in asynchronous communications
US5897324A (en) * 1997-02-03 1999-04-27 Atop Technologies, Inc. Multimedia-book operable with removable data storage media implemented with universal interfacing book-adapting processor
US6070194A (en) * 1997-12-17 2000-05-30 Advanced Micro Devices, Inc. Using an index and count mechanism to coordinate access to a shared resource by interactive devices
JP2000010913A (ja) * 1998-06-26 2000-01-14 Sony Computer Entertainment Inc 情報処理装置および方法、並びに提供媒体
EP1096695B1 (en) * 1999-10-28 2012-03-21 STMicroelectronics S.r.l. Multichannel transceiver of digital signals over power lines
KR101979732B1 (ko) * 2012-05-04 2019-08-28 삼성전자 주식회사 비휘발성 메모리 컨트롤러 및 비휘발성 메모리 시스템
HK1210647A1 (en) * 2013-08-19 2016-04-29 Kabushiki Kaisha Toshiba Memory system
KR20160007859A (ko) * 2014-07-04 2016-01-21 삼성전자주식회사 컴퓨팅 시스템 및 이의 동작 방법.
US10542125B2 (en) * 2014-09-03 2020-01-21 The Boeing Company Systems and methods for configuring a computing device to use a communication protocol

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5498143A (en) * 1978-01-20 1979-08-02 Toshiba Corp Communication control system
JPS576921A (en) * 1980-06-13 1982-01-13 Fujitsu Ltd Loading system of initial program

Family Cites Families (9)

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Publication number Priority date Publication date Assignee Title
US4075691A (en) * 1975-11-06 1978-02-21 Bunker Ramo Corporation Communication control unit
US4093981A (en) * 1976-01-28 1978-06-06 Burroughs Corporation Data communications preprocessor
US4137565A (en) * 1977-01-10 1979-01-30 Xerox Corporation Direct memory access module for a controller
EP0021489A1 (en) * 1979-06-08 1981-01-07 Koninklijke Philips Electronics N.V. Input/output channel for a high-speed computing system
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
US4344130A (en) * 1979-09-26 1982-08-10 Sperry Corporation Apparatus to execute DMA transfer between computing devices using a block move instruction
US4298959A (en) * 1979-11-23 1981-11-03 United Technologies Corporation Digital information transfer system (DITS) receiver
US4418384A (en) * 1980-10-06 1983-11-29 Honeywell Information Systems Inc. Communication subsystem with an automatic abort transmission upon transmit underrun
JPS57143629A (en) * 1981-02-28 1982-09-04 Hitachi Ltd Input and output control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5498143A (en) * 1978-01-20 1979-08-02 Toshiba Corp Communication control system
JPS576921A (en) * 1980-06-13 1982-01-13 Fujitsu Ltd Loading system of initial program

Also Published As

Publication number Publication date
WO1984001449A1 (en) 1984-04-12
EP0120889B1 (en) 1987-12-16
DE3374965D1 (en) 1988-01-28
JPH0420497B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-04-03
EP0120889A1 (en) 1984-10-10
GB2128000A (en) 1984-04-18
US4538224A (en) 1985-08-27
GB8325793D0 (en) 1983-10-26
GB2128000B (en) 1986-09-10
CA1194608A (en) 1985-10-01

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