JPS5948981A - High density printed circuit board - Google Patents

High density printed circuit board

Info

Publication number
JPS5948981A
JPS5948981A JP15997182A JP15997182A JPS5948981A JP S5948981 A JPS5948981 A JP S5948981A JP 15997182 A JP15997182 A JP 15997182A JP 15997182 A JP15997182 A JP 15997182A JP S5948981 A JPS5948981 A JP S5948981A
Authority
JP
Japan
Prior art keywords
pattern
density printed
land
land pattern
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15997182A
Other languages
Japanese (ja)
Inventor
喜規 上川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP15997182A priority Critical patent/JPS5948981A/en
Publication of JPS5948981A publication Critical patent/JPS5948981A/en
Pending legal-status Critical Current

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  • Structure Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、信号パターンが接続されたう、ンドパター
ン内に部品挿入用の孔又は透孔(スルーホール)が形成
される高密度印刷配線基板に関する。
Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a high-density printed wiring board in which a hole or through hole for inserting a component is formed in a board pattern to which a signal pattern is connected. Regarding.

〔発明の技術的背忽〕[Technical background of the invention]

近時の半導体集積回路の高密度化に伴い、印刷配線基板
においても高密度化の細則にある。
With the recent increase in the density of semiconductor integrated circuits, there are also detailed rules for increasing the density of printed wiring boards.

例えば、従来、ランドパターンの径が1.5mmであt
ハD I P (Dual−Inline I’ack
ge)型のI C(Integrated C1rcu
it)のビンとビンとの間(2,54mu+)に幅0.
35 mm O,)ラプンを一木通していたものから、
ランドパターンの仔ヲ14111111、ラインの幅を
0.25 mInへと、ノ4クーンを小さく、細かぐす
る傾向にある。
For example, conventionally, if the diameter of the land pattern is 1.5 mm,
Ha D I P (Dual-Inline I'ack
ge) type IC (Integrated C1rcu)
It) between the bins (2,54mu+) with a width of 0.
35 mm O,) From the one that had been passed through a single tree,
There is a tendency to make the width of the land pattern smaller and finer by reducing the line width to 0.25 mIn.

〔背景技術の問題点〕[Problems with background technology]

しかしながら、このパターンの微細化は、マスク上にお
いてはICCビンJζニラインな2木、3本と辿すこと
が可能であZ・にもかかわらす。
However, this pattern miniaturization can be traced to two or three ICC bins Jζ lines on the mask, even though it is Z.

印刷配線基板の製造上、第1図に示すような問題が生ず
るため実現が困負11であった。−づ−なわち、ランド
パターン1内にIC挿入用の孔2を形1戊する際1色部
すれか生じた坂1台、その結果、ランドパターン1と信
号パターン3との間に断線事故が発浄しやすくなるため
である。このような事故は、ランドパターンJの径及び
46号・Vターン3の幅の微細化が進むにつれて多くな
る。
In manufacturing the printed wiring board, problems such as those shown in FIG. 1 occur, making it difficult to realize this. -In other words, when drilling the hole 2 for IC insertion in the land pattern 1, there was one slope where only one color was rubbed, resulting in a disconnection accident between the land pattern 1 and the signal pattern 3. This is because it becomes easier to purify. Such accidents increase as the diameter of the land pattern J and the width of the No. 46 V-turn 3 become smaller.

〔発明の目的〕  ゛ この発明は上記実情に鑑みてたさ】tたも01で、七の
目的は、製造時において、ランドパターン及び信号パタ
ーンの微細化及び孔開は時の位置すれに起因するランド
パターンとイム1士・ぐターンとの断線事故を防止する
ことができる1tも密度印刷配線基板を提供することに
ある。
[Object of the Invention] [This invention was made in view of the above circumstances] The seventh object of the present invention is to prevent miniaturization of land patterns and signal patterns and hole openings due to positional misalignment during manufacturing. An object of the present invention is to provide a high-density printed wiring board that can prevent a disconnection accident between a land pattern and an immum turn.

〔発明の概要〕[Summary of the invention]

この発明は、信号・ぐターンか接続されたランドパター
ン内に1部品挿入用の孔又は透孔が形成される高密度印
刷配線基板におい°(、l’l’I記信号パターンを前
記ランドパターンに接続する直前で多方向に分枝し、多
方向から前記ランドパターンに接続するものである。
The present invention provides a high-density printed wiring board in which a hole or through hole for inserting one component is formed in a land pattern connected to a signal pattern. It branches in multiple directions immediately before connecting to the land pattern, and connects to the land pattern from multiple directions.

〔発明の実施例〕[Embodiments of the invention]

以下、図面ビ参照してこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第2因において% 11.12はそれぞれ高密度印刷配
線基板におけるランドパターンである。これらランドパ
ターン11.12にはそれぞれ信号パターン(電源ライ
ン、GNDラインを含む)13.14が接続されている
In the second factor, %11.12 is the land pattern in the high-density printed wiring board, respectively. Signal patterns (including power supply lines and GND lines) 13 and 14 are connected to these land patterns 11 and 12, respectively.

信号パターン13.14はそれぞれランドパターン′1
1,12の面前において3方向°に分枝し、3方向から
ラントノやターン1ノ、ノ2にl’f Mcされている
Signal patterns 13 and 14 are land patterns '1, respectively.
It branches in three directions in front of No. 1 and No. 12, and l'f Mc is formed from three directions into Runto No., Turn No. 1 No., and No. 2.

このような構成においては、ランドパタ−ン11.12
内に例えはICピン挿入用の孔15゜16を形成する際
、ラントノ(’ターン1)(−おけるように孔15の1
1′f圓ずれが生じた場合であっても不部会はない。ず
なわち、孔J5の位1iijずれにより信号パターン1
3におけ乙、1木の分校パターン13aとランドパター
ン内Jとの間に断i!llη1故が生じブζ場合であっ
ても、仙の分枝パターン13b、1.icとラントノS
ターン1)との間が接続された)1゛まであるため、回
路動作に異常はない(なホ1、ラントノ8多−ンノ2は
孔16の位置ずれか律じでいt−い状態を’jjニー4
ものである。、)。
In such a configuration, the land pattern 11.12
For example, when forming holes 15 and 16 for inserting IC pins, turn 1 of hole 15 so that
Even if a 1'f circle shift occurs, there will be no failure. In other words, the signal pattern 1 is caused by a 1iij shift in hole J5.
In 3, there is a disconnection between the branch pattern 13a of the 1st tree and J in the land pattern! Even if llη1 is caused by ζ, the sacral branching pattern 13b, 1. ic and lantono S
There is no abnormality in the circuit operation because there is a connection between the turn 1) and the turn 1). 'jj knee 4
It is something. ,).

上記信乞パターン13の公社形状は第2図に示すような
形状に1す(らず%第3図に示すような形状でもよく、
また、第4図に示−4−ようにランドパターンJ7の形
状を方形とし、イe+ +、−;)(’り−718の分
子方向を2方向(分校パターン18a。
The shape of the public corporation of the begging pattern 13 may be the shape shown in FIG. 2, or the shape shown in FIG. 3,
Further, as shown in FIG. 4, the shape of the land pattern J7 is made into a rectangle, and the molecular directions of -718 are set in two directions (branch pattern 18a).

18b)とするようにしてもよい。さらに、第4図にお
いては1分枝パターン18a、18bをランドパターン
17の2辺における中央部にそれぞれ接続しているが、
第5図に示すように、分枝パターン1sa、18bをラ
ンドパターンJ7の角に近い部分に接続させるようにす
ると。
18b). Furthermore, in FIG. 4, the one-branch patterns 18a and 18b are connected to the center portions of the two sides of the land pattern 17, respectively.
As shown in FIG. 5, the branch patterns 1sa and 18b are connected to portions near the corners of the land pattern J7.

孔19の位置すれによる断線事故をJ゛り効果的に防止
できるものである。
This can effectively prevent wire breakage accidents due to misalignment of the holes 19.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれは、ランドパターン及び信
号ノやターンの微細化が進め、製造時において孔開けの
位置すれが生じても、ランドパターンと信号パターンと
の断線事故を効果的に防止できるので、高密度パターン
設計が可能となる高密度印刷配線基板を提供できる。
As described above, this invention effectively prevents disconnection accidents between the land pattern and the signal pattern even if the land pattern and the signal hole or turn become finer and the position of the hole is misaligned during manufacturing. Therefore, it is possible to provide a high-density printed wiring board that enables high-density pattern design.

【図面の簡単な説明】[Brief explanation of drawings]

第1図kl従来の高密度印刷配線基板における配線パタ
ーンを示す図、第2図はこの発明の一実施例に係る高密
度印刷配線基板における配線ノぐターンを示す図、第3
図乃至第5図はそれぞれこの発明の他の実施例を示す図
である。 11、  ノ2・・・ランドパターン、13.14・・
・46号パターン、 13  a 、   13b、   J、?c、   
14  a 、   ノ  4b。 14c・・・分枝パターン、 1 5 、   ノ  6 ・・・ 孔。
Fig. 1 shows a wiring pattern on a conventional high-density printed wiring board; Fig. 2 shows a wiring pattern on a high-density printed wiring board according to an embodiment of the present invention;
5 through 5 are diagrams showing other embodiments of the present invention, respectively. 11. No. 2...Land pattern, 13.14...
・No. 46 pattern, 13a, 13b, J,? c,
14a, no 4b. 14c...branch pattern, 15, no6...hole.

Claims (1)

【特許請求の範囲】[Claims] 信号パターンが接続されたランドパターン内に孔が形成
される冒密度印刷配線基扱において、前記(8号パター
ンが前記ランド・ゼターンに接、続される直前で多方向
に分枝し、多方向から前記ランドパターンに接続された
ことを・特徴とする高密度印刷配線基板。
In the high-density printed wiring system in which a hole is formed in the land pattern to which the signal pattern is connected, the above pattern (No. 8 pattern branches in multiple directions immediately before being connected to the land pattern, A high-density printed wiring board, characterized in that the board is connected to the land pattern.
JP15997182A 1982-09-14 1982-09-14 High density printed circuit board Pending JPS5948981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15997182A JPS5948981A (en) 1982-09-14 1982-09-14 High density printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15997182A JPS5948981A (en) 1982-09-14 1982-09-14 High density printed circuit board

Publications (1)

Publication Number Publication Date
JPS5948981A true JPS5948981A (en) 1984-03-21

Family

ID=15705167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15997182A Pending JPS5948981A (en) 1982-09-14 1982-09-14 High density printed circuit board

Country Status (1)

Country Link
JP (1) JPS5948981A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63291490A (en) * 1987-05-25 1988-11-29 Ibiden Co Ltd Substrate for bearing electronic component
WO2013141392A1 (en) * 2012-03-19 2013-09-26 日清紡ホ一ルディングス株式会社 Method for manufacturing electronic component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63291490A (en) * 1987-05-25 1988-11-29 Ibiden Co Ltd Substrate for bearing electronic component
WO2013141392A1 (en) * 2012-03-19 2013-09-26 日清紡ホ一ルディングス株式会社 Method for manufacturing electronic component
JP2013197273A (en) * 2012-03-19 2013-09-30 Nisshinbo Holdings Inc Electronic component manufacturing method
CN104170535A (en) * 2012-03-19 2014-11-26 日清纺控股株式会社 Method for manufacturing electronic component

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