JPS5948547B2 - Manufacturing method for semiconductor devices - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

More specifically, it concerns the manufacturing method of memory LSI incorporating MIS type capacitors.The cell circuit is shown schematically in Figure 1 as a memory cell most suitable for high integration in terms of layout simplicity and cell area, which affect yield. A memory cell using one MOS type transistor T and a capacitor C is attracting attention.

In the figure, W indicates a word line and D indicates a data line. The cell area of this memory cell must be kept as small as possible because it strongly depends on the circuit technology, especially the design of the high-sensitivity amplifier, the variation of multiple amplifiers within the chip, and the noise characteristics within the array. be.

For this reason, various attempts have been made to realize capacitors with large capacitance in a small area by improving the process or layout (for example, using inversion layer capacitance or using a material with a high dielectric constant for the insulating film). There is. As shown in FIG. 2, a capacitor C having a large capacitance with a small area has a silicon substrate 1 as a lower electrode and a MOS transistor T.
A polycrystalline silicon layer 3 is used as a gate electrode of a MOS transistor using an insulating film 2a having the same quality as the gate oxide film 2
It is conceivable to have a structure in which the upper electrode is made of the same material.

However, even with such a structure, since the flat insulating film 2a on the surface of the silicon substrate 1 is used,
Achieving the desired capacity requires a large area,
It is difficult to obtain a memory LSI with excellent performance without increasing the degree of integration. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can make a capacitor incorporated in a memory LSI or the like as small in area and large in capacity as possible.

According to the present invention, a groove is formed in the surface of the semiconductor substrate on which the MIS type capacitor is formed.

Embodiments according to the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a sectional view of a main part of a memory LSI in which the present invention is implemented, and shows one memory cell consisting of one MOS type transistor T and MOS type capacitor.

In the figure, 10 is a silicon substrate on which a silicon gate MOS type transistor T and a MOS type capacitor C are provided, and a groove is provided in the MOS type capacitor C portion. 10a is the source and drain of the transistor T; 11 is a field silicon oxide film;
12 is a gate oxide silicon film, 13 is a polycrystalline silicon layer for a gate electrode, 14 is a surface protection film such as a phosphosilicate glass film, and 15 is an aluminum electrode.

Further, 12a is an insulating film of a MOS type capacitor C formed at the same time as the gate silicon oxide film, and 13a is an upper electrode of the MOS type capacitor C formed at the same time as the gate electrode. Note that 16 is an aluminum electrode led out from the polycrystalline silicon layer 13a, which is the electrode of the MOS type capacitor C. The main part of this MOS type capacitor C is a region in which a groove is provided in the silicon substrate 1.

Therefore, the surface area of the insulating film 12a of the capacitor is
Since the size of the MOS capacitor C on the silicon substrate 1 is larger by the area of the groove side wall than the conventional MOS type capacitor which does not have this type of groove, in order to obtain the same capacitance, the MOS type capacitor C on the silicon substrate 1 must be increased by the area of the groove side wall. The area can be made small. Next, the present invention will be described using FIGS. 4 to 8. Memory LS
The manufacturing method of I will be explained in detail step by step.

(7) The surface of the silicon substrate 10 is thermally oxidized to form a thick silicon oxide film 11, and the silicon oxide film 11 in the element active region is removed by photoetching (FIG. 4). (
b) Silicon substrate 1 on which MOS type capacitor C is to be formed
Next, grooves are formed by dry etching or chemical etching using the photoresist film 17 as a mask (FIG. 5).

(c) The surface of the silicon substrate 1 is thermally oxidized to form the gate insulating film of the MOS transistor T and the MOS capacitor C.
About 1,000 people formed a silicon oxide film 12 that would become an insulating film.

Next, a polycrystalline silicon layer 3 having a thickness of about 5,000 layers is formed by the CVD method (FIG. 6). This serves as the gate electrode of the MOS transistor T and the upper electrode of the MOS capacitor C. (iv) After forming the gate electrode] 3, the capacitor electrode 13a, the gate silicon oxide film 12, and the capacitor insulating film 12a by a self-alignment method, impurities are diffused to form the source layer and the drain layer 10a, and The polycrystalline silicon layers 13 and 13a are made conductive and have low resistance (FIG. 7).

(e) A phosphosilicate glass film is formed as the surface protective film 14 by the CVD method, and after openings for electrodes are formed in this, aluminum electrodes 15 and 16 are formed (FIG. 8).
.

As mentioned above, the MOS type capacitor C according to the present invention
can be formed by reusing the manufacturing process for forming the silicon gate MOS type transistor T.

When forming a groove in the silicon substrate 1 in the C region of the MOS capacitor, dry etching such as ion etching or plasma etching is performed to form a groove in which the side wall surface of the groove is approximately perpendicular to the bottom surface of the groove. can be formed deeply. Therefore, a groove with a large sidewall area can be easily provided in a small area of the silicon substrate. Therefore, it is possible to achieve the desired capacity M with a small area.
An OS type capacitor can be provided on the silicon substrate 1. Therefore, a memory LSI incorporating this type of MOS type capacitor has high performance and high degree of integration. Further, since a plurality of grooves in the silicon substrate 1 of the MOS type capacitor C can be provided as required, a MOS type capacitor having a small area and a large capacity can be easily incorporated into a semiconductor device.

Although the embodiment of the present invention described above is a memory LSI whose main element is a silicon gate MOS type transistor, the present invention can be applied to various semiconductor devices whose main elements are bipolar transistors or MIS type transistors.

[Brief explanation of the drawing]

FIG. 1 is a cell circuit diagram of a memory cell using -1 MOS type transistor and capacitor C, FIG. 2 is a sectional view showing a memory cell structure considered as the memory cell shown in FIG. 1, and FIG. The figure is a sectional view showing an embodiment of the present invention.
FIGS. 4 to 8 show a memory LS which is an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing method of I in order of steps. T...MOS type transistor, C...
Capacitor, W...Word line, D...
Data line, 1, 10...Silicon substrate, 2, 1
2... Gate silicon oxide film, 3, 13...
... Gate electrode, 10a ... Source layer and drain layer, 11 ... Field silicon oxide film, 12a ... Insulating film of MOS type capacitor,
13a... Upper electrode of MOS type capacitor, 1
4... Surface protective film, 15, 16... Aluminum electrode.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device in which an MIS type transistor and a MIS type capacitor are formed on a semiconductor substrate, the method comprising: forming a groove in a portion of the surface of the semiconductor substrate where the MIS type capacitor is to be formed; An electrode of the MIS type capacitor is formed on the side wall surface of the groove via an insulating film, and a gate electrode of the MIS type transistor is also formed, and then the MIS type capacitor is formed on the surface of the semiconductor substrate using the gate electrode as an impurity introduction mask. A method for manufacturing a semiconductor device, comprising forming source and drain regions of a transistor. 2. A MIS type transistor on a semiconductor substrate and an MIS type capacitor connected to the MIS type transistor, with an electrode formed through an insulating film on the side wall surface of a groove formed on the surface of the semiconductor substrate as one electrode. 1. A method for manufacturing a semiconductor device, characterized in that the groove is formed by dry etching.