JPH0618258B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a one-transistor dynamic MOS memory that realizes a large capacity without increasing a planar area and is suitable for a large scale.

[Prior Art] Since the dynamic random access memory of 1 Kb (hereinafter abbreviated as dRAM) was announced in the early 1970's, the MOS dynamic memory has been quadrupled in size in three years. However, a 16-pin DIP (dual in-run package) has been mainly used for the package in which the memory chip is inserted, and the size of the cavity in which the chip is inserted is limited. With it, the increase is only about 1.4 times. (In addition, since the dRAM is used in a large amount, it is necessary to suppress the increase in chips in terms of cost.) Therefore, the memory cell area for 1 bit, which is one storage capacity unit, is also greatly reduced, and the scale is increased by 4 times. As a result, the size has been reduced to about 1/3. Since the capacitor capacitance C is represented by C = εA / Ti (here, ε: dielectric constant of insulating film, A: capacitor area, Ti: insulating film thickness), if the area A becomes 1/3, ε and T are the same. As long as C is also 1
/ 3. The signal amount S as the storage capacity is proportional to the stored charge amount Q _S , and since Q _S is the product of C and the storage voltage V _S , the smaller A is, the smaller Q _S is proportionally. And the signal S becomes smaller accordingly.

If the noise voltage is N, the signal-to-noise ratio (S / N ratio) becomes smaller as S decreases, which is a serious problem in circuit operation. Therefore, the amount of decrease in A is usually compensated by the decrease in Ti, and with the increase in the size of 4Kb, 16Kb, 64Kb and dRAM, the typical thickness Ti of the SiO ₂ film as an insulating film is It became smaller as 100 nm, 75 nm and 50 nm. In order to solve such a situation, a semiconductor memory cell using a groove type capacitor has been considered.

(For example, JP-A-51-130178 and JP-A-52
-154390 gazette).

[Problems to be Solved by the Invention] More recently, heavy metals (U, T
α particles radiated from (h etc.) cause about 2 in the Si substrate.
It has been confirmed that a charge of 00fC is generated, and that this becomes noise, and the charge as a signal amount is approximately 200f in terms of highly reliable operation.
It has become difficult to reduce it to C or less.

Therefore, it has been implemented to further accelerate the thickness of the insulating film, and in this case, dielectric breakdown of the insulating film has become a problem. The breakdown voltage electric field of the SiO ₂ film is 10 ⁷ V / cm at maximum.
Therefore, a 10 nm SiO ₂ film causes almost permanent destruction or is deteriorated by application of 10 V. Further, it is a serious problem in terms of long-term reliability that it is used near the maximum electric field even if it does not cause permanent destruction.

The object of the present invention is to reduce the size of α associated with miniaturization of these memory cells.
A method capable of maintaining or increasing the capacitor area A without reducing the insulating film thickness even when the memory cell is miniaturized, by coping with the disturbance caused by particles, the deterioration of the S / N ratio, and the seriousness of the problem of withstand voltage. Is to provide.

[Means for Solving the Problem] According to the present invention, the side wall of a groove dug in a Si substrate is used as a plate, and the electrode which is formed by filling the groove with an insulating film is used as a main portion of a capacitor electrode to store information. By using it for increasing the electrode area without increasing the planar area,
In addition, it is to increase the strength against α rays and the like.

[Operation] As a result, it is possible to obtain a desired capacitor capacitance without making the insulating film thin and increasing the risk of destruction and deterioration of the insulating film. Furthermore, since the substrate side is used as a plate, the strength against α rays is dramatically improved.

[Embodiment] FIG. 1 is a block diagram of a one-transistor type dRAM memory cell, which is composed of a capacitor 1 for storing charges and a switch transistor 2, and the drain of the switch transistor is connected to a bit line 3. The gate is connected to the word line 4.

This memory cell is operated by reading the signal charge stored in the capacitor 1 by the switch transistor 2. A memory array is formed to actually form an N-bit memory, but there are roughly two methods described below.

FIG. 2 shows a so-called "open bit line" configuration in which bit lines 3-1 and 3-2 are arranged on both sides of a sense-up circuit 5 which differentially amplifies signals. This is one word line 4
Only one bit line 3-1 is electrically crossed with respect to -1, and the difference between the signals on the bit lines 3-1 and 3-2 is detected by the sense amplifier 5.

FIG. 3 shows the other "folded bit line" configuration, in which two bit lines 3-1 and 3-2 connected to the sense amplifier 5 are arranged in parallel, and one word is formed. The line 4-1 intersects the two bit lines 3-1 and 3-2.

Although the embodiments of the present invention described later mainly show the case of the folded bit line configuration, they can be similarly applied to the open bit line configuration.

As shown in FIGS. 2 and 3, when the value of the parasitic capacitance 6 of the bit line 3-2 is C _D and the value of the capacitor 1-2 of the memory cell is C _S , the main performance of this memory array is shown. One of the indicators is C _S / C _D. The S / N ratio of this memory array has a one-to-one correspondence with C _S / C _D, and the value of the capacitor of the memory cell is increased, and at the same time, the parasitic capacitance C of the bit line 3 is increased.
_Reducing the value of _D also improves the S / N ratio.

FIG. 4 shows the plane 1 of the folded bit line type memory cell.
Here is an example: A part of the active region 7, which is usually surrounded by a thick field oxide film having a thickness of 100 nm or more, forms a capacitor and is covered with a plate 8. The plate 8 is selectively removed from the portion forming the switch transistor and the portion of the contact hole 9 for connecting the bit line electrode to the drain on the Si substrate, and the word lines 4-1 and 4 are formed in this portion.
-2 is deposited to form the switch transistor 2. To facilitate understanding, FIG. 5 shows a sectional view taken along the line AA 'of FIG.

For convenience of description, an example in which a transistor is an n-channel type is shown below. To make it a p-channel type, generally, the conductivity types of the Si substrate and the diffusion layer may be reversed from those of the n-channel type.

The conventional memory cell shown in FIG. 5 is a p-type, 10Ω-c.
m on the Si substrate 10 is usually 100 to 1000 n
A field SiO ₂ film 11 having a thickness of about m is selectively deposited by a so-called LOCOS method using Si ₃ N ₄ as a thermal oxidation mask. After this, polycrystalline Si added with phosphorus or As
A plate 8 typified by (hereinafter abbreviated as poly Si) is selectively deposited, and the plate 8 of poly Si is oxidized to form a first interlayer oxide film 13. After that, poly
When the word line 4 typified by Si or Mo silicide or refractory metal (Mo, W, etc.) is deposited and phosphorus or As is ion-implanted, the plate 8 and the word line 4 are formed.
An n ⁺ diffusion layer 15 is formed in the active region of the switch transistor 2 which is not deposited and serves as the source and drain of the switch transistor 2. After this, PS containing phosphorus by so-called CVD method
G (Phosoho-sillcate glass) 200-1000nm
The second interlayer insulating film 14 is formed to a thick thickness, and the contact hole 9 is formed in a portion for connecting the bit line 3 represented by an Al electrode to the diffusion layer 15 to selectively cover the bit line 3. To wear.

In this memory cell, the region 16 of the capacitor 1 which is the storage capacity is the shaded portion in FIG. 4, and the region 16 becomes smaller as the memory cell itself becomes smaller, unless the gate oxide film 12 is made thinner. As described above, the capacitance C _S of the capacitor becomes small, which is a great obstacle in memory operation.

In the above description, for the sake of convenience, the insulating film below the plate 8 and the word line 4 (that is, the gate of the switch transistor 2) is the same SiO ₂ film 12, but the main purpose is to increase the value C _S of the capacitor of the memory cell. The insulating film below the plate 8 may be an insulating film having a one-layer to _three- layer structure using one or both of SiO ₂ and Si ₃ N ₄ .

It is an object of the present invention to increase C _S without increasing the plane area without compensating for the drawbacks of the above-mentioned conventional structures.

The present invention will be described in detail below with reference to examples.

First, FIG. 6 shows a plan view of one embodiment of the present invention. The difference from the conventional memory cell shown in FIG.
A low resistance layer having the same conductivity type as that of the Si substrate is provided on the side wall of the groove 17 dug in the i substrate 10, this is used as a plate 8, and the electrode buried in this groove is used as the capacitor electrode 20.

The manufacturing process of the semiconductor memory according to the present invention will be described in detail below. First, as shown in FIG. 8, p-type, 1 to 20 Ω-cm
After forming the field oxide film 11 on the Si substrate 10 by the above-mentioned LOCOS method, a groove 17 having a predetermined size is formed by parallel plate plasma etching using a gas containing F or Cl such as SF ₆ or CCl ₄ as a main component. Form. Usually 1-5μ
Since an etching groove having a depth of m is formed, the groove pattern is once transferred to the CVD SiO ₂ film using an ordinary photoresistor.
The CVD SiO ₂ film is used as a mask to form the groove 17, and then the well-known diffusion method or the like is used to form the p ⁺ layer 8 having the same conductivity type as that of the Si substrate and having a conductivity of 1 Ω-cm or less on the side wall and the lower part of the groove. Plate 8 is used. Thereafter, as shown in FIG. 9, a single layer of SiO ₂ or Si ₃ N ₄ or a composite film thereof, or a capacitor insulating film 18 typified by Ta ₂ O _{5 is} deposited. A capacitor electrode connecting hole 20 reaching the Si substrate 10 is formed in a predetermined portion of the capacitor insulating film 18, and a predetermined capacitor electrode 19 of poly Si is connected to the Si substrate 10 through the connecting hole 20. Put on the part. If the thickness of the poly Si 19 is ½ or more of the inner wall spacing of the groove 17, as shown in FIG.
As a result, an n ⁺ diffusion layer 15 is formed in the Si substrate 10.

Then, as shown in FIG.
Oxidation by dry or wet oxidation method at ~ 1100 ° C
The first interlayer insulating film 13 having a thickness of 0 to 2000 nm is formed, and the portion where the switch transistor 2 is to be formed has a thickness of 10 to 50 nm.
A gate oxide film 12 having a thickness is formed, and poly is formed on the gate oxide film 12.
A gate (word line 4) of Si, Mo silicide, or Mo, W or the like is deposited. After that, by ion implantation method A
Then, s or the like is implanted to form the n ⁺ diffusion layer 15.

Further, a second interlayer insulating film 14 represented by CVDPSG is deposited to form a contact hole 9 to the n ⁺ diffusion layer 15,
A bit line 3 represented by Al is deposited.

By doing so, the capacitor 1 is formed by the capacitor insulating film 18, two electrodes sandwiching the capacitor insulating film 18, that is, the capacitor electrode 19 and the plate 8. If the plate 8 is of the same p-type as the Si substrate 10, the capacitor electrode 19 has a positive potential, so the p-type impurity concentration is sufficiently increased so that the surface of the plate 8 is not depleted or an inversion layer is formed at the maximum potential. Need to be kept. On the other hand, in the case of another embodiment of the present invention in which the plate 8 is of the n-type, even if the capacitor electrode 19 has a positive potential, there is no problem because the surface of the plate 8 is in the accumulation state. When the plate 8 is of the n-type, as shown in the groove 17 of FIG. 6, since n ⁺ layers are provided separately around the groove 17, it is necessary to connect them. As shown in the figure, if a Si substrate n type is used and a p type epitaxial layer is formed on this surface, all the spaced plates 8 are connected to an n type Si substrate 10. Since this Si substrate can be set to the ground potential, the influence of noise voltage is small. The manufacturing method is shown in FIG.
Instead of the Si substrate of the previous embodiment described in FIG. 10, the Si substrate 10 having the epitaxial layer 21 laminated thereon may be used.

FIG. 12 shows another embodiment of the present invention. The capacitor electrode 19 of the above-described embodiment is connected to the plate 8 to form the capacitor 1
However, the present example is characterized in that the second plate 22 is deposited via the first interlayer insulating film 13 and the capacitor is formed during this period. In this case, since the main capacitor is added to the capacitor between the plate 8 and the plate 8, a larger capacity capacitor can be obtained. In addition, the second plate 13, which can be set to the ground potential, also serves as a shield for the capacitor electrode 19 and is resistant to noise.

In the above-described embodiment of the present invention, the switch transistor 2 is made Si.
It is formed on the surface of the substrate 10 or the epitaxial layer 21. FIG. 13 shows another embodiment of the present invention.

As already described in the above embodiment, the capacitor insulating film 1
8 is deposited and then a single crystal film of Si is formed, and S including a portion which becomes the capacitor electrode 19 and the diffusion layer portion 15 in a later step.
Forming a structure (short for S ilicon O n I nsulator) OI . This can be polycrystalline or amorphous (amo
rphous) Si film is deposited, and the entire surface or a part of the surface is heated by a laser beam or a thermal heater, and once melted, or the single crystal layer 23 is grown on the insulating film in the solid phase. There is. (Although not shown in FIG. 13, SO
If a part of the Si film having the I structure is brought into contact with the Si substrate 10, single crystallization can be easily performed, which is a great advantage. ) Thereafter, the gate oxide film 12 and further the gate are deposited on the SOI portion 23 to form an n ⁺ layer, and one of them is a capacitor electrode 19
And the other is a diffusion layer 15 connected to the bit line 3. The subsequent steps are the same as in the previous embodiment. In this embodiment, since the switch transistor 2 is not provided on the Si substrate 11, the substrate 11 can have any conductivity type. That is, if the n-type is used, the Si substrate 10 itself becomes the plate even if the plate 8 is not provided.

Generally, in the present dynamic memory, it is difficult to form the entire Si substrate 10 into the n-type because peripheral circuits having moderate functions are formed around the memory cells, but in this case, the plate 8 may be provided and the memory cell It suffices to make only the portion of n type.

Although the second plate is not used in the embodiment shown in FIG. 13, the second plate 22 used in the embodiment shown in FIG.
Can be provided.

In the above description of the embodiment of the present invention, as shown in FIG. 6, the plane pattern of the groove 17 is a simple rectangular pattern.
The larger the surface of the capacitor electrode 19 facing the plate 8 is, the larger the capacity of the capacitor is. Therefore, as shown in FIGS. 14A to 14C, the groove 17 is formed in the comb shape of FIG. 14A. In this case, (c) in the case where the groove 17 is formed in a ring shape, the capacitance of the capacitor can be increased in the same plane area than in the case of a simple elongated shape.

The embodiment described above is chosen from among many alternative processes. Therefore, various alternatives are possible for each step, but in any case, it is common that the side wall of the groove formed in the substrate serves as a part of the capacitor.

Although the present invention has been described in the above embodiment as the word line 4 being a continuous gate in the memory cell array, the poly Si transfer gate 4 of the switching transistor 2 in the memory cell is continuously formed between the memory cells. Without separating, form through a new contact hole
It is also possible to connect with the word line 4 of l. In this way, the reliability of many conventional polycrystalline Si gates,
Since the resistance of Al is low, a high-speed memory switching time can be obtained.

As described above, the gist of the present invention is to make the side wall of the groove dug in the substrate part of the capacitor. Accordingly portions other than the grooves of the substrate, for example, the substrate surface portion, or polycrystalline Si-Si ₃ N ₄ film has been known - a stack Kondesa i.e. such second plate 22 made of polycrystalline Si on the substrate surface However, the gist of the present invention is not impaired even if the capacitor is formed in parallel and is connected in parallel with the capacitor on the side wall to further increase C _s .

Although the switch transistor is formed in the SOI layer in parallel with the Si substrate, as shown in FIG.
The transistor channel portion 24 may be formed in the layer 23 in the vertical direction. This vertical channel transistor is S
It can be applied to all memory cells using OI.

In addition, the present invention, as described at the beginning, is an n-channel type M
Although the description has been made using the OS transistor, it is possible to achieve the P-channel type by using impurities that reverse the conductivity types of all the impurities. Phosphorus or As may be replaced with B or Al, and B may be replaced with phosphorus, As, Sb, or the like.

[Effects of the Invention] The present invention has been described above with reference to the detailed embodiments. However, in the case where the switch transistor is formed on the substrate surface, the capacitor capacitance Cs is 2 times larger than that of the conventional memory cell in the same plane area.
What is formed in the SOI layer can increase Cs several times to several times. In reality, the shape of the groove is not completely straight, but rather rounded, and even if the design shape is square due to the resolution of lithography in the fine part, it becomes circular. However, even in this case, the reduction of Cs is limited to 10 to 20%.

The malfunction of the dynamic memory due to α rays is 10 Cs.
Even if it increases by%, it is often improved by one digit or more, so Cs
The increase of 2 times or more will not only increase the reliability of the memory of that scale, but also enable realization of a larger scale memory.

Further, according to the present invention, a large amount of electron-hole pairs generated in the Si substrate due to α-rays rarely directly flow into the capacitor electrode 19, and in particular, those using SOI do not flow at all. It has strong characteristics against lines.

[Brief description of drawings]

1 to 5 are views for explaining a conventional memory cell, and FIG.
FIG. 15 to FIG. 15 are views showing an embodiment of the present invention. Explanation of symbols 1 ... Capacitor, 2 ... Switch transistor, 3 ...
... bit line, 4 ... word line, 5 ... sense amplifier, 6
... parasitic capacitance, 7 ... active area, 8 ... plate, 9 ...
Contact hole, 10 Si substrate, 11 field oxide film, 12 gate oxide film, 13 first interlayer insulating film, 14 second interlayer insulating film, 15 diffusion layer, 16
...... Capacitor region, 17 ... Groove, 18 ... Capacitor insulating film, 19 ... Capacitor electrode, 20 ... Capacitor electrode connection hole, 21 ... Epitaxial layer, 22 ... Second
Plate, 23 ... SOI part, 24 ... Transistor channel part.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masanobu Miyao 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-56-81968 (JP, A) JP-A-52 -154390 (JP, A)

Claims (6)

[Claims] 1. A plurality of word lines, a plurality of bit lines provided to intersect with the word lines, a plurality of memory cells provided at intersections of the word lines and the bit lines, and the memory cells A capacitor for storing information and a switch transistor for controlling reading and writing of information from and to the capacitor are included. The capacitor has a groove formed in the semiconductor substrate, an insulating film provided on the surface of the groove, and An electrode provided on the insulating film, information is stored in the electrode, the first electrode of the switch transistor is electrically connected to the word line, and the second electrode of the switch transistor is Is electrically connected to the bit line, the third electrode of the switch transistor is electrically connected to the electrode, and the current path from the second electrode to the third electrode of the switch transistor is the above Is provided almost perpendicular to the semiconductor substrate,
Further, the semiconductor memory is characterized in that the switch transistor is laminated on the capacitor formed on the insulating film. 2. The semiconductor device according to claim 1, wherein the first electrode of the switch transistor is laminated on the second electrode via a second insulating film. memory. 3. The bit line is a third line on the word line.
The semiconductor memory according to claim 1, wherein the semiconductor memory is provided via the insulating film. 4. A plurality of word lines, a plurality of bit lines provided to intersect with the word lines, a plurality of memory cells provided at intersections of the word lines and the bit lines, and the memory cells The capacitor includes a capacitor for storing information and a switch transistor for controlling reading and writing of information from and to the capacitor, and the capacitor has a groove provided in the semiconductor substrate and a first insulating film provided on the surface of the groove. And an electrode provided on the first insulating film, information is stored in the electrode, and the first electrode of the switch transistor is electrically connected to the word line. The second electrode of the switch transistor is electrically connected to the bit line, the third electrode of the switch transistor is electrically connected to the electrode, and the second electrode and the third electrode of the switch transistor are Is above A semiconductor memory characterized in that the semiconductor memory is provided separately from the semiconductor substrate via a second insulating film provided on the semiconductor substrate in contact with the first insulating film. 5. The semiconductor according to claim 4, wherein the first electrode of the switch transistor is laminated on the second electrode via a third insulating film. memory. 6. The semiconductor memory according to claim 5, wherein the bit line is provided on the word line via a fourth insulating film.