JPS593918A - Manufacture of complementary semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate parasitic capacitance caused by overlap and attain the high speed, by a method wherein an insulation film having width corresponding to lateral diffusion length of impurity to be ion-implanted is formed to end at gate electrode side on active region to be ion-implanted. CONSTITUTION:When As<+> ion is implanted in P type well region 22, a first remaining CVD-SiO2 film 28 having width equal to lateral diffusion length LA of arsenic is formed to end at side of a gate electrode 272, thereby the gate electrode 272 and N<+> type source and drain regions 30, 31 are not overlapped. When B<+> ion is implanted in N type silicon substrate 21, first and second remaining CVD-SiO2 films 28', 32' having width equal to lateral diffusion length LB are formed to end at side of a gate electrode 271, thereby the gate electrode 271 and P<+> type source and drain regions 34, 35 are not overlapped.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a method of manufacturing a complementary semiconductor device. It is manufactured by the method shown in ).

First, for example, a thin thermal oxide film on a P-type silicon substrate (X region) 1? After forming, for example, impurity-doped polycrystalline silicon is deposited on the entire surface. Next, these polycrystalline silicon and thermal acid ratio r are sequentially buttered to form a P-type silicon substrate (
A gate electrode 3 is formed on the device region) 1 via a gate oxide M2.
(as shown in FIG. 1(a)) Next, as a mask for the gate electrode s2, a silicon substrate (device region) 1 is formed.
N-type impurity r ions are implanted. Next, annealing
The Np impurity km was made gaseously active, and the N was used as the source.
A drain region -15r is formed (as shown in FIG. 1(b)).

In the method described above, the gate electrode 3 and the N+ type source 1. The horizontal length of the drain region 4.5 and the N-type impurity are shown in FIG.
) is formed by overlapping only 2),
Does the distribution of parasitic capacitance in this overlap region increase device speed? It was an obstacle in my pursuit.

So, what are the above drawbacks? In order to solve the problem, see Figure 2 (a) to (d).
) has been adopted.

First, 13 gate electrodes made of, for example, polycrystalline silicon are formed on, for example, a P-type silicon substrate (device region) 11 via a gate oxide film 12'y (as shown in FIG. 2(a)).Next, N CVD -8to, film 14? with a width equal to the lateral diffusion length of the type impurity. (as shown in FIG. 2(b)). Next, reactive ion etching (RIE), which is an anisotropic etching, is performed.
The remaining CVD-8102 film 14' is removed by etching, and a wide remaining CVD-8102 film 14' is formed on the gate electrode 13 (as shown in FIG. 2(c)). Residual CV
D-8IO□ membrane 14'? An N-type impurity is added to the P-type silicon substrate 11 as a mask. Implant ions. Next, we went to an annealing meeting to find out whether it was an N-type impurity. electrically active, N+
Type source and drain regions 15'+116'f are formed (as shown in FIG. 2(d)).

In the method described above, N is applied to the edge of the gate electrode 13 in advance.
Residual C'VD with width equal to lateral diffusion length of type impurity
-810. Since the membrane 14' has even been formed, as shown in FIG.
d) Is the fcN type impurity ion-implanted in the illustrated process? Even if it is annealed and diffused, the gate electrode 13 and N”W
The source and drain regions 15 and 16 do not overlap.

Therefore, no parasitic capacitance is generated, and high-speed device operation can be achieved.

By the way, the person mentioned above, the law? When applied to the manufacture of complementary semiconductor devices, the following problems arise. .

That is, for example, boron is used as a P-type impurity to form a P-channel MO transistor, and an N-channel MO
8) When using arsenic as an N-type impurity to form a 7-transistor, the diffusion coefficient of boron is approximately twice that of arsenic, so the lateral diffusion length of boron is equal to the lateral diffusion length of arsenic. It is about twice the length. Therefore, what is the thickness of the insulating film formed on the side edges of each gate electrode? , when matched with the lateral diffusion length of boron, the drain region is formed without reaching the edge of the gate electrode, and the N-channel MO transistor does not operate even if a voltage higher than the threshold voltage is applied. do not. On the other hand, the width of the insulating film? When adjusted to the lateral diffusion length of arsenic, an overlap region is formed between the P+ source and drain regions and the gate electrode, and a parasitic capacitance is generated.

[Purpose of the invention]

The present invention deals with parasitic capacitance based on the overlap between the gate electrode and the source and drain regions in both P-channel and N-channel MOS transistors. What is the purpose of providing a method for manufacturing a complementary semiconductor device that can achieve faster speeds? This is the purpose.

[Summary of the invention]

The method for manufacturing a complementary semiconductor device of the present invention includes first and second
Is there an impurity of the opposite conductivity type in each active region of the conductivity type? Before ion implantation, an insulating film with a width corresponding to the lateral diffusion length of the impurity to be ion-implanted is formed at least on the gate electrode side edge of the active region where ions are to be implanted.↓
The purpose is to prevent the impurity diffusion layer and the gate electrode from overlapping in either the first or second conductivity type active regions, thereby eliminating parasitic capacitance.

[Embodiments of the invention]

The following is an example of the present invention? Figures 3 (a) to (h) and 4
This will be explained with reference to Figures (a) and (b).

Embodiment 1 First, 22 P-type well regions are formed on an N-type silicon substrate 21, and then an Elifield oxide film 23 and the N-type and P well regions thereunder are formed using the usual selective oxidation method and ion implantation into the field inversion prevention region. - Type field inversion prevention area 24.25
'z formed. Next, after forming a thin thermal oxide film 7 on the surface of the element region of the N-type silicon substrate 21 and the P-type well region 22, an impurity-doped polycrystalline silicon film is formed on the entire surface. Deposited.

Next, what about these polycrystalline silicon and thermal oxide films? Gate oxide films of 26Hz26xk are formed on the N-type, silicon substrate 21 and P-type well regions 22 by sequential patterning.
via the gate electrode 27. ．． 272 purple was formed (Fig. 3 (
a) As shown in Figure 3) Next, a first CVD-8in2 film 28 with a thickness equal to the lateral diffusion length of arsenic was deposited on the entire surface (as shown in Figure 3(b)). This first CVD is similar to reactive ion etching RIE, which is a reactive etching process.
-310, the film 28 is etched and the gate electrode 27 is
．． ．． 27. First remaining CVD-8 of width LA at the side end
I Os MW 2"+"' was formed (Fig. 3(C)
(Illustrated) 0 Continuing, at least the N-type silicon substrate 2
After forming a photoresist pattern 29 to cover the upper surface, this non-resist pattern 29 and the gate electrode 27 of the P-type well region 22 are formed. This gate electrode 27
First residual CVD-8102 film 2 formed on the second side edge
8'? As a mask, As 7i ions were implanted (3rd stage).
(D) (Illustrated) Next, the photoresist pattern 29? After removing
Fully annealed N+ type source and drain regions 30.31
'f formed. Subsequently, 32 second CVD-8IO2 films having a thickness equal to the difference between the lateral diffusion length of boron and arsenic were deposited on the entire surface (as shown in FIG. 3(e)). Next, Eriko No. 2 (D CVD-
8L (H film 32 is etched to form the gate electrode 2).
7. , the first remaining CVD formed at the 27° side end.
-Second residual CVD layer overlaid on the 8io2 film 28'...
810, film 32'...purple color formed. These first and second remaining CVr)-8IO! Membrane 28'...132'.
When combined with the width 7 of..., the horizontal diffusion length LB of boron
(as shown in FIG. 3(f)). Next, at least on the P-type well region 22? Covering sea urchin photoresist pattern 33? After forming the photoresist pattern 33 and the gate electrode 2 on the N-type silicon substrate 2,
7. The first .
Second remaining CVD-810, membrane 28'-, 32'
=-'fz-y sct and 'C'3''k ion implantation (
Figure 3 (g) diagram).

Next, the photoresist pattern 33? After removing
Anil? Gate type source, drain region 34.35
'; (formed.Continued, all ffi K 3rd +7)
CVD-810! After depositing 36 films, contact holes 37. ...After drilling the hole. Next, A/= on the entire surface.
film? After film deposition, buttering °CA, a Wiring 38
．． ...Complementary semiconductor device r was manufactured by sound formation (3rd
Figure (h) shown).

According to the manufacturing method described above, when Aa f ions are implanted into the P-type well region 22 in the step shown in FIG. Since the first residual CVD-810 film 28' with a width equal to the width of 100 nm has been formed, annealing is performed in the step shown in FIG.
．． 31'l (even if formed, the gate electrode 27. and N+,
There is no overlap with the H source and drain regions 30 and 31. On the other hand, when Bi ions are implanted into the Nu silicon substrate 21 in the step shown in FIG. 3(g), the gate electrode 27
First and second residual CVD-810, [2B
', 32' are formed, so annealing 7 is performed in the process shown in FIG. : Even if Il'7 is formed, the gate electrode 27. and P
+ type source.

There is no overlap with drain regions 34 and 35. Accordingly, an N-type silicon substrate 21 and a P-type well region v,
In any of 22, no parasitic capacitance is generated due to the overlap between the gate electrode and the source/drain region, and high-speed complementary semiconductor devices can be manufactured. ↓The N+ type source and drain regions 30 and 31 are formed first, and the diffusion coefficient is large d(1:I:,/
(D ion implantation and annealing K L P” source,
Since this is performed after the formation of the drain regions 34 and 35, P+
type source. Drain region 3a.

There are few heat steps after forming the gate electrode and the source and drain regions are less likely to overlap.

Embodiment 2 M3 Figures (a) to (e) In the steps shown in the drawings, a silicon substrate 21 and a well region 22 of the N type and the P type well region 22 separated by the field oxide film 23 were respectively coated with a silicon nitride layer (G) through the oxide film 2J*262. Gate electrodes 27, . 27 □ Lateral diffusion of arsenic on the side edge with a similar width remaining CVD-8101
pli 2 B'・"After forming the pores, As+ ions are implanted into the P-type well region 22 and annealing is performed to form the E-type source, drain/region 30. A second CV with a film thickness equal to the difference between the diffusion length LB and the lateral diffusion length L/ of arsenic.
D-8tO2 membrane 32? At this point, the remaining CVI is deposited at the end of the gate electrode 271) -8j
O□ film 28' and 2nd +7) CVD-8to, film 32
and? The combined width is equal to the lateral diffusion length LB of boron.

Subsequently, 39 photoresist patterns were formed in at least the P-type well region 22 with an X-shaped pattern, and then B 2 was ion-implanted into the photoresist patterns 39 as a mask (as shown in FIG. 4(a)). At this time, the gate electrode 27
The remaining CVD-8IO at the 10i11 end, film 2
8' and the second CVD-8IO, film 32 also acts as a mask.

Next, after removing the 39 photoresist patterns,
Annealed P+ type source and drain regions 40.4
1' (formed.Continuously, a contact hole 42...? is formed in the second insulating film 32, and an At film r is formed on the entire surface.
After vapor deposition, patterning is performed to form At wiring 43. ...?
Forming a complementary semiconductor device? was manufactured (as shown in FIG. 4(b)).

Therefore, the same effects as in Example 1 can be obtained even with the above-mentioned manufacturing method.

Note that the impurities used in the present invention are not limited to arsenic and boron as in the above embodiments, but may be other impurities, and the insulating film is not limited to CVD-810, but it goes without saying that other insulating films may be used. be.

〔Effect of the invention〕

According to the present invention, in both P-channel and N-channel λ10S transistors, there is a parasitic capacitance based on the over two-tube between the gate electrode and the source and drain regions. Is there a method for manufacturing complementary semiconductor devices that can achieve faster speeds by eliminating them? This is something that can be provided.

[Brief explanation of drawings]

Figures 1(a) and (b) show the conventional N? Yanel MO8)
Figure 2 is a sectional view showing the manufacturing method of transistors in order of process.
a) to (d) are cross-sectional views showing another manufacturing method of a conventional N-channel MO8) transistor in order of steps;
h) is a cross-sectional view showing the manufacturing method of a complementary semiconductor device according to the first embodiment of the present invention in the order of steps; FIGS. 4(a) and 4(b)
Is the method for manufacturing a complementary semiconductor device in Example 2 of the present invention? It is sectional drawing shown in order of a process. 21...N-type silicon substrate, 22°/P-type reel region, 23...Field oxide film, 24.25...N
""凰 and P""壓 field inversion prevention area, 26, .
26. ... Gate oxide film, I#, 21° ... Gate electrode, 28 ... First CVN-STO, film, 2 g
'-°° 1st residual CVD-810, membrane, so. 3I...N type source. Drain area, 32nd river 21st
Z) CVD-8in, film,! '2'-11g2 residual C
VD-8iQ, membrane, 34.35-P type north. 1”Vi:/area, 36-M 3 c7) cvD-s
102 i, 37・°・contact hole, 38・・
・AtWeM, 39°°° photoresist pattern, 40
．． 47...P type source, drain region, 42...
Contact hole, 43...A/- wiring. Applicant's agent Patent attorney Takehiko Suzue 1 =,
Figure 2 Figure 3 Figure 3

Claims (3)

[Claims] (1) Is there a gate insulating film on each active region of a semiconductor substrate having active regions of first and second conductivity types? At least each gate electrode is used as a mask to form an impurity of opposite conductivity type in each active region. In the manufacturing method of complementary semiconductor devices in which ions are implanted to form source and drain regions, do impurities of opposite conductivity types enter each active region? Before ion implantation, is it necessary to form an insulating film having a width corresponding to the lateral diffusion length of the impurity to be ion-implanted, at least at the end of the gate electrode side above the active region to be ion-implanted? A method for manufacturing a complementary semiconductor device characterized by: (2) When forming the source and drain regions by ion-implanting the first conductivity with a small diffusion coefficient into the active region of the opposite conductivity type as a type impurity and the second conductivity type impurity gold with a high diffusion coefficient at least as a gate electrode mask. , a first insulating film over the entire surface of the semiconductor substrate including the gate electrode? The insulating film is deposited and anisotropically etched to leave an insulating film with a width corresponding to the lateral diffusion length of the impurity of the first conductivity type at the edge of each gate electrode, and to form a first insulating film in the active region of the second conductivity type. A conductive type impurity silicon ion is implanted to form a first conductive source and drain region, and then a second insulating film is formed on the entire surface. The second conductive impurity is deposited and anisotropically etched at least at the edge of the gate electrode side on the active region of the first conductivity type, with a width corresponding to the lateral diffusion length of the second conductive impurity, together with the remaining insulating film. Insulating film? A complementary semiconductor device according to claim 1, characterized in that impurity silicon ions of the second conductivity type are implanted into the active region of the first conductivity type to form the second conductivity type source and drain regions. Production method. (3) A first conductivity type impurity with a small diffusion coefficient and a second conductivity type impurity with a large diffusion coefficient? At least the gate electrode? When forming source and drain regions by implanting ions into active regions of opposite conductivity types as a mask, a first insulating film is applied over the entire surface of the semiconductor substrate including the gate electrode. The insulating film is deposited and anisotropically etched to leave an insulating film having a width corresponding to the lateral diffusion length of the impurity of the first conductivity type at the end of each gate electrode, and to form the first insulating film in the active region of the second conductivity type. All conductive type impurity ions are implanted to form a conductive source and drain region, and then the second conductive type is added to the remaining insulating film at the gate electrode side edge on the active region of the first conductive type over the entire surface. The second insulating film has a width corresponding to the lateral diffusion length of the impurity. A second conductivity type impurity is deposited in the first conductivity type active region? Is it possible to implant ions to form the second conductivity type source and drain regions? A method for manufacturing a complementary semiconductor device according to claim 1.