JPS59197161A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To microscopically form an element attaining a high yield rate as well as to lessen the concentration of electric field by a method wherein, when a C- MOS semiconductor device of light redoped drain structure is formed, the controllability of the low density impurity region of each transistor is excellently maintained. CONSTITUTION:Of the first element forming region 24 and the second element forming region 25 of a P type Si substrate 21, first an N type well region 22 is formed on the region 25, and the regions 24 and 25 are isolated using a thick field oxide film 23. Then, a gate electrode 261 wherein a gate oxide film 272 is used as an underlaid film and a gate electrode 262 wherein a gate oxide film 272 is used as an underlaid film are provided on said regions 24 and 25, they are surrounded by an oxide film 28, a polycrystalline Si film 29' is formed along the side face of them, and its side wall is converted to an SiO2 film 30'. Subsequently, resists 31 and 34 are covered on the regions 24 and 25 alternately, N<+> type source and drain regions 32 and 33 are formed on the region 24, and P<+> type source and drain regions 35 and 36 are formed on the region 25 by performing an ion implantation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a CMO8 semiconductor device having a completely doped drain structure.

[Technical background of the invention and its problems]

In recent years, as MO8 semiconductor devices have been miniaturized, strong ? Deterioration of characteristics such as fluctuations in threshold voltage due to the generation of hot carriers caused by the jff and field has become a problem.

In order to solve these problems, LDD (Lightl
A ydoped drain) structure has been proposed.

In this LDD structure, the drain region (and source region) of the MO8 semiconductor device is
-Current) Impurity region (impurity concentration 1016-1018 cm)
-5) and the bacterial concentration adjacent to this low concentration (N-type) impurity region (i) impurity region (impurity concentration ~ 10 cm
) is composed of the following.

Since this MO8 semiconductor device having the LDD structure can alleviate the strong electric field in the channel region, the various problems described above can be solved.

By the way, the LDD structure has conventionally been adopted in N-channel MO8) Land Dusters, which have a large negative effect due to the generation of hot electrons, such as the following (1) and (1).
Although they are manufactured by methods such as 1), each of these manufacturing methods has its own problems. However, new problems arise when attempting to apply the LDD structure to a CMO8 semiconductor device.

The prior art and its drawbacks are explained below in Figures 1(,) to (d).
) and FIGS. 2(a) to 2(d).

(1) First, a field oxide film 2 is formed on the surface of the P-type silicon substrate 1 by selective oxidation, and then a thermal oxide film 3, which will become a gate oxide film, is formed on the surface of the element region surrounded by this field oxide film 2. Form. Next, after sequentially depositing a polycrystalline silicon film, a silicon nitride film, and a CVD oxide film on the entire surface, these are sequentially turned to form a polycrystalline silicon film pattern 4. whose area is larger than the final dirt electrode. A silicon nitride film 5 and a CVD oxide film 6 are formed. Subsequently, using these grooves as a mask, N-type impurity ions are implanted at a localized dose (as shown in FIG. 1(a)). Next, only the peripheral portion of the polycrystalline silicon pattern 4 is selectively side-etched to form a dirt electrode 7 (as shown in FIG. 2B). Then, Cv
After removing the thermal oxide film 3 not covered by the D oxide film pattern 6 and the gate electrode 7 to form the gate oxide film 8, the silicon nitride film pattern 5 is removed. Next, using the dirt electrode 7 as a mask, N-type impurities are ion-implanted at a low dose (as shown in FIG. 3(c)).

Next, a heat treatment is performed to activate the impurity ion implanted layer twice. Source and drain regions 9, consisting of N'' type impurity regions 9a, 10a near the channel region and furnace l impurity regions 9b, 10b adjacent to these regions;
10 (as shown in FIG. 10(d)).

This method involves performing high-dose ion implantation and low-dose ion implantation before and after side etching of the polycrystalline silicon/gutter 4 to control the widths of the N-type impurity regions 9a and 10a. .

However, it is difficult to control the amount of side etching of the polycrystalline silicon pattern 4, and a stable yield cannot be ensured at the LSI level. Of course, similar drawbacks occur when applied to a CMOS process.

(11) First, a field oxide film 12 is formed on the surface of a P-type silicon substrate 11 according to a selective oxidation method, and a gate electrode 14 is formed in the element region via a dirt oxide film 13.
Using this dirt electrode 14 as a mask, N-type impurity ions are implanted at a low dose (as shown in FIG. 2(a)). Next, a CVD oxide film 15 is deposited on the entire surface (as shown in FIG. 2(b)).

Subsequently, this CVD nine-oxide film 15 is etched by anisotropic etching, and the CVD film 15 remaining on the side surface of the dirt electrode 14 is etched.
D-oxidized WA (hereinafter referred to as sidewall film) 16.
form 16. The conditions of anisotropic etching are controlled so that the width of this sidewall film 16.16 is equal to the width of the N-type impurity region to be formed. Next, K-
N-type impurities are implanted at a high dose using the side electrode 14 and the sidewall film 16, 16 as masks (see Fig.
c) As shown). Next, heat treatment is performed to activate the impurity ion-implanted layers described above to form N-type impurity regions 17a and 18a near the channel region and N-type impurity regions 17a and 18a adjacent to these regions.
Source and drain regions 17 and 18f consisting of dielectric impurity regions 17b and 18b are formed (as shown in FIG. 2D).

This method has various drawbacks as follows.

(a) When the CVD oxide film 15 is etched by anisotropic etching to form the sidewall film 16.16, over-etching occurs and the N''' type impurity region 1 is etched.
Controllability of the widths of 7a and 18a deteriorates.

(b) Process margin is small.

(c) When CVD oxide film 15 is used, step coverage is not good, and if extra etching is performed taking into account the margin, the surface of substrate 11 may be damaged by anisotropic etching species, and the film thickness of field oxide film 12 may be damaged. will decrease.

In addition, when this method is applied to a CMOS process, ion implantation of low and high doses of N-type impurities and ion implantation of low and high doses of P-type impurities (N-channel MO8) results in LDD structure only for the lannostar. P when doing
For each high-dose ion implantation of a type impurity, a photoresist gloss turn must be formed covering the P-type or N-type device region, increasing the number of etching steps. This results in a decrease in retention. Furthermore, since the sidewall films 16, 16 are not usually removed in this method, the second
(C) A step of ion-implanting a P-type impurity (usually boron) is always required before the high-dose ion implantation of an N-type impurity in the illustrated step. However, since boron is easily diffused, the P channel λtos is
Control of source and drain regions of Trannostar: ji
Sexuality becomes worse.

[Object of the invention] The present invention has been made in view of the above circumstances.
The present invention aims to provide a method for manufacturing a semiconductor device in which a low-risk impurity region can be formed with good controllability when the structure is applied to a CMO8 near process, and in which retention is not reduced.

[Kaede of invention]

The method for manufacturing a semiconductor device of the present invention includes a first conductive, rhombic first element region (for example, when an N well region is formed on a P-type silicon substrate, an element region of the substrate other than the well region) and After forming dirt electrodes on the surface of each element region of a semiconductor substrate having a second element region of two conductivity types (the element region of the well region) via a gate insulating film, a dirt electrode is formed on the surface of the dirt electrode and the surface of the element region. A first film is formed, a non-monocrystalline silicon film (for example, a polycrystalline silicon film) is deposited on the entire surface, a second film is further formed on the surface, and then a second film and a polycrystalline silicon film are deposited. Sequential anisotropic etching is performed to leave a polycrystalline silicon film on the side surface of the gate electrode. Continuing,
High-dose ion implantation of a second conductivity type (N2u) impurity selectively into the first element region using the dirt electrode and the remaining polycrystalline silicon film as a mask, and the dirt after removing the remaining polycrystalline silicon film. Low-dose ion implantation is performed using the electrode as a mask, and heat treatment is performed to form the N-channel/I of the LDD structure.
/Form a MOS transistor. Next, a high dose of first conductivity type (P type) impurity is selectively implanted into the second element region using the dirt electrode and the remaining polycrystalline silicon film as a mask, and after removing the remaining polycrystalline silicon film. A low-dose ion implantation is performed using the dirt electrode as a mask, followed by heat treatment to form a P-channel transnoster with an LDD structure.

According to this method, it is possible to form the low density impurity region of each transistor with good controllability, and the process margin is large due to the good step coverage of the polycrystalline silicon film, and the photolithography process is also increased. Therefore, a decrease in yield can be prevented.

[Embodiment 1 of the Invention] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3(a) to 3(a).

First, a Nm well region 2 is formed in a part of the P-type silicon base &21.
2, a field oxide film 23 is formed according to a normal selective oxidation method, and a first element/region 24 surrounded by the field oxide film 23 is formed on the substrate 21 other than the well region 22.
A second element region 2.5 surrounded by a field oxide film 23 is formed in the well region 22.

Next, after forming a thermal oxide film with a thickness of about 250X on the surfaces of the first and second element regions 24.25, a thermal oxide film with a thickness of about 300X is formed on the entire surface.
Deposit a ~6000X polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form dirt electrodes 261 and 26 in the first and second device regions 24 and 25, respectively.
After forming 2, the thermal oxide film is etched using the dirt electrodes 261 and 262 as a mask to form dirt oxide films 271 and 272 (as shown in FIG. 3(a)).

Next, thermal oxidation is performed to form the gate electrode 261.

262 surface and exposed ml and second element region 24.
25 Thermal oxide film 2 with a thickness of 400X as the first coating on the surface
form 8. Subsequently, a polycrystalline silicon film 29 is deposited over the entire surface by the LPCVD method. Since the polycrystalline silicon film has good step coverage, the dirt electrode 261 r
A substantially vertical stepped shape corresponding to the shape of 262 is obtained. Furthermore, since the thickness of the polycrystalline silicon film 29 is an important factor in determining the width of the N-fi impurity region in the source and drain regions, which will be described later, careful control of the film thickness is required. Next, thermal oxidation is performed to form a thermal oxide film 30 as a second coating on the surface of the polycrystalline silicon film 29. A part of this thermal oxide film 3° will be used as a mask when performing anisotropic etching of the polycrystalline silicon film 29 in a later step, and will be an important factor in determining the width of the N-type impurity region (the same Figure (b) shown).

Next, the thermal oxide film 30 is etched by anisotropic etching to form a dirt electrode 261.

Residual thermal oxide films 30', . . . are formed only on the side walls of the step portion of the polycrystalline silicon film 29 corresponding to the shape of
Figure (c) shown).

Next, the polycrystalline silicon film 29 is etched by anisotropic etching using these remaining thermally oxidized m30', . . . as a mask. Residual polycrystalline silicon films 29', . . . are formed on the side walls of 26 squares via the thermal oxide film 28, with the remaining thermal oxide films 30', . When etching this polycrystalline silicon film, the remaining thermal oxide film 30',...
Since side etching of the polycrystalline silicon film 29 is prevented, residual polycrystalline silicon films 29', . . . with a width equal to the film thickness are formed with good controllability (see (d)
).

Next, a photoresist pattern 31 is formed on the N-type well region 22, and the remaining polycrystalline silicon film 29' is formed on the gate electrode 261 and its side surfaces.

Using 29' as a mask, ions of arsenic, for example, are implanted into the first element region 24 at a high dose (approximately the dose for forming a normal source and drain) (as shown in FIG. 3(e)).

Then, J is etched by isotropic etching using an etching solution.
) Remaining polycrystalline silicon film 2 on element region 24 of r1
9' and 29' are removed. At this time, the remaining polycrystalline silicon film 29', the remaining thermal oxide film 30' on the 29',
30' is lifted off. Next, dart electrode 2
Using 61 as a mask, arsenic, for example, is ion-implanted at a low dose into the first element region 24 (as shown in FIG. 6(f)).

Next, after removing the photoresist pattern 31, the arsenic ion implantation layer twice is activated by heat treatment, and an N-type impurity region 3 near the channel region is formed in the first device region 24.
2a, 33a and an N-enhanced impurity region 32b adjacent to these regions.

33b, source and drain regions 32 and 33 are formed. As a result, an N-channel transistor with an LDD structure is formed (as shown in FIG. 2(g)).

Next, after forming a photorenost pattern 34 on the substrate 21 other than the well region 22, the gate electrode 262 and the remaining polycrystalline silicon films 29', 29' on the side surfaces thereof are removed.
Using this as a mask, ions of, for example, ion are implanted into the second element region 25 at a high dose (as shown in FIG. 4(h)).

Next, the remaining polycrystalline silicon film 29' on the second element region 25 is etched by isotropic etching using an etching solution.
29' is removed. At this time, the remaining polycrystalline silicon film 29
30', 30' are lifted on. Subsequently, using the gate electrode 262 as a mask, ions of boron, for example, are implanted at a low dose into the second element region 25 (as shown in FIG. 3(i)).

Next, after removing the photoresist no-turns 34, the twice-implanted boron ion layer is activated by heat treatment, and Pl impurity regions 35h and 36a near the channel region and adjacent to these regions are formed in the second element region 25. P+7
! Impurity region 35b.

Source and drain regions 35° and 36 made of 36b and 36b are formed. As a result, a P-channel transistor having an LDD structure is formed (as shown in FIG. 12(j)).

Next, after depositing a CVD oxide film 31 on the entire surface, a contact hole 38. ...Drill a hole. Furthermore, A on the entire surface
After depositing the T film, ・Cutning is performed to form the At wiring 39.
. . . to manufacture a CMOS inverter with an LDD structure (as shown in FIG. 2(k)).

According to the method described above, the anisotropic etching of the thermal oxide film (second film) 30 in the step shown in FIG. 3(C) and the remaining thermal oxide film 3 in the step shown in FIG.
By anisotropic etching of the polycrystalline silicon film 29 using 0' as a mask, gate electrode 26. , 2Gz (residual polycrystalline silicon film on il1 surface (so-called sidewall film)
The width of z9', . . . can be well controlled. It's a trench, dirt electrode 261. Since a polycrystalline silicon film with good step coverage and uniform film quality is used as the sidewall pattern left on the sidewall of the 2G, the process margin is much greater than when a CVD 71% film is used as the sidewall film. becomes larger. For example, the third
Figure (c) In the anisotropic etching of the thermal oxide film 30 in the illustrated step, over-etching of 60 times is possible. The anisotropic etching of crystalline silicon g3o makes it easy to detect the end point of the device21), and the remaining polycrystalline silicon in the steps shown in (f) and (i) of the same figure can be easily detected.
When removing the contact film 29' by isotropic etching, over-etching of 200% is possible because the selectivity with respect to the field oxide film 23 and the thermal oxide film 28 is high. This is why the N-type impurity region 32a of the N-channel transistor.

The width of 33a or the P-type impurity regions 35* and 36a of the P-channel transistor can be extremely well controlled. Further, there is no fear that the substrate 21 or the field oxide film 23 will be eroded by the anisotropic etching species. Furthermore, the ion implantation process for the P-channel transistor can be performed after the ion implantation process for the N-channel transistor, and the number of three etching processes is the same as in the normal 0MO8 manufacturing process, making it easy to apply to the CMOS process. . therefore,
Even if the CMO8 semiconductor device becomes smaller, the strong electric field in the channel region can be alleviated without reducing the yield, and various adverse effects caused by the generation of hot carriers can be eliminated.

In the above embodiment, thermal oxide films were used as both the first and second films, but the present invention is not limited to this, and an oxide film or a nitride film may be formed by the C2 method or the Snow R-Ivy method.

Further, in the above embodiment, the P-channel transistor also has an LDD structure, but since the P-channel transistor mask has comparatively less adverse effects due to hot carriers, only the N-channel transistor mask may have the LDD structure. In this case, the remaining polycrystalline silicon film 30' on the second element region 25 is removed without performing the high-dose boron ion implantation in the step shown in FIG. Using this as a mask, boron ion implantation can be performed at a high dose. Furthermore, in the above embodiment, arsenic was ion-implanted at a low dose in the step shown in FIG. 3(f), but in the step shown in FIG.
After forming the □, a photoresist pattern is formed on the NM well hollow region 22, and the dart electrode 26. Arsenic may be ion-implanted at a low dose into the first element region 24 using as a mask.

Further, in the above embodiment, a case has been described in which an N-type well region is formed on a P-type silicon substrate, but it goes without saying that a P-type well region may be formed on an N-type silicon substrate.

〔Effect of the invention〕

As described in detail above, according to the method of manufacturing a semiconductor device of the present invention, even if the device is miniaturized, the yield does not decrease and the high-performance film can be used to alleviate various adverse effects caused by electric field concentration in the channel region. If a CMO8 semiconductor device can be manufactured, a remarkable effect of 1/λ will be achieved.

[Brief explanation of drawings]

Figures 1 (a) to (d) and Figures 2 (a) to (d) are cross-sectional views showing a conventional manufacturing method for obtaining an N-channel MO8) run mask manufactured by LDD@, respectively, and Figure 3 (a). )
~(Odor is CMO of LDD structure in the embodiment of the present invention)
FIG. 3 is a cross-sectional view showing a manufacturing method for obtaining an S inverter. 21... P-type silicon substrate, 22... N-type well region, 23... field oxide film, 24... first element region, 25... second element region, 261. 262... Dirt electrode, 271 +272... Dirt oxide film, 28... Thermal oxide film (first film), 29.
...Polycrystalline silicon film, 29'...Remaining polycrystalline silicon IJ
Con film, 30... Thermal oxide film (second film), 30'...
-Residual thermal oxide film, 31.34...Photoresist cutane, 32a, 33a=-N- type impurity region, 32b. , 33 b...N'' type impurity region, 32.33...
sauce. Drain region, 35a, 36a...P1 impurity region,
35 b, 36 b...p+ type impurity region, 37
...CVD oxidation IJia', ss...contact hole, 39...At wiring. Desennin's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (2)

[Claims] (1) First element region of first conductivity type and second conductor region:
A step of forming a dirt electrode on each element region of the semiconductor substrate forming the second element region of the mold through a gate insulating film, and a step of forming a first coating M on the surface of each element region exposed in the step 6, and a step of forming a second coating on the surface of the non-single crystal silicon film after depositing a non-single crystal silicon film on the entire surface. and,
etching the second film by anisotropic one-step etching to leave the second film only on the side surface of the stepped portion of the non-single crystal silicon film; and etching the second film using the remaining second film as a mask. a step of etching the crystalline silicon film by mechanical etching to leave a non-mono3.4 crystalline silicon film on the side surface of the first layer through the first film; A step of selectively ion-implanting a second conductivity type impurity into the first element region at a high dose using the non-single crystal silicon film remaining on the gate electrode and its side surfaces as a mask; After removing the non-single-crystal silicon film remaining on the side surface of the dirt electrode, a second layer is selectively applied to the first element region using this dirt electrode as a mask.
A process of ion-implanting conductive type impurities at a low dose;
The ion implantation layer is activated twice by heat treatment, and the first
A second region consisting of a low concentration impurity region near the channel entrapment region and a high concentration impurity region adjacent to these regions is formed in the device region.
Steps of forming conductive type source and drain regions; 1. selectively ion-implanting a first conductive cage type impurity into the second element region at a planar dose using the dirt electrode on the second element region and the non-single crystal silicon film remaining on the side surface thereof as a mask; After removing the non-single-crystal silicon film remaining on the side surface of the dirt electrode in the second element region, using the dirt electrode as a mask, ions of the first conductivity type impurity are selectively implanted into the second element region at a low dose. and activating the ion-implanted layers twice by heat treatment, forming a first region in the second device region consisting of a low concentration impurity region near the channel region and a high concentration impurity region adjacent to these regions. 1. A method of manufacturing a semiconductor device, comprising a step of forming conductive type source and drain regions. (2) The first and second coatings are thermally oxidized films, oxide films or oxidized films formed by a CVD method or a suction method. The method for manufacturing a semiconductor device according to item 1.