KR940000987B1 - Manufacturing method for soi-structured transistor - Google Patents

Abstract

The method for improving the to pology and preventing the carrier movement between gate, drain and source comprises the steps of: (a) forming active regions for N and P channels; (b) forming a field oxide layer on an oxide layer placed between the active regions; (c) injecting the high density P type ion after exposing the P channel source and drain region with a first masking process; (d) injecting the high density P type ion into the exposed P channel gate trench region and high density n channel source, drain regions; (e) injecting the low density n type ion into the exposed low density n channel source, drain regions and P channel gate trench region; (f) forming a side-wall oxide layer and a gate oxide layer on the inside of the gate trench; and (g) forming a gate electrode, a protective layer and a metal layer in sequence.

Description

Soy structure transistor manufacturing method

1 is a structural cross-sectional view of the related art.

2 is a cross-sectional view of the process of the present invention.

* Explanation of symbols for main parts of the drawings

1: bare wafer 2: oxide film

3: P type epi layer 4: Ireland

5: field oxide film 6: P source and drain

7: n-gate trench 8: n source and drain

9: n source and drain 10: n gate trench

11: gate trench sidewall 12: gate oxide film

13,13a: gate electrode polysilicon 14: BPSG film

15: metal film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a transistor having a SOI structure, and in particular, to improve topology and improve gate, source, and drain using a gate trench and a gate sidewall. It is suitable to prevent the movement of the carrier (carrier) between.

Conventional soy structure transistors have a p-type epitaxial layer formed on sapphire or an insulator as shown in FIG. 1, and a gate, a source, and a drain are formed thereon. As a transistor is formed on the insulator, current leakage can be prevented. Bulk effect could be reduced.

This manufacturing process will be described with reference to FIG.

First, a silicon oxide film 21 as an insulator is formed on the wafer 20, and then a p-type epi layer 22 is formed. Then, the p-type epi layer 22 is selectively anisotropic etched. The active region 23 of the N-channel transistor and the p-channel transistor is formed.

Then, a LOCOS (Local Oxidation of Silicon) process is performed on the silicon oxide film 21 between the active region 23 and the active region 23 to form a field oxide layer 24, and a gate is formed at the center of each active region 23. The silicon oxide film 25 and the gate polysilicon film 26 are sequentially formed.

Subsequently, a high concentration n-type ion implantation and a high concentration P-type ion implantation mask process and an ion implantation process for source and drain are sequentially performed to form source and drain junctions under both gates.

The process is completed by depositing the B.P.S.G (Boron-Phosphorous-Silicate-Glass) film 27 and the metal film 28 in sequence.

However, since the transistor is formed on the island, the topography of the subsequently deposited metal film is not good, so that cracks are easily generated in the metal film and the moving speed of the carrier is slowed down, resulting in a slow speed.

The present invention is to eliminate the above disadvantages and will be described in detail with reference to the accompanying drawings 2 (A) to 3 (H) as follows.

First, as shown in FIG. 2A, oxidation is performed on the wafer 1 to form an oxide film 2 as an insulator, and a P-type epitaxial layer 3 is formed thereon to a thickness of about 9000-10000 kPa. Type-etching 3 is etched at regular intervals to form islands of active regions 4 of n- and p-channel transistors.

Subsequently, as illustrated in FIG. 4B, an oxide film 5 is formed on the oxide film 2 between the active region 4 and the active region 4, and a photoresist PR ₁ is deposited on the entire surface, and is exposed and developed. After exposing the high concentration source and drain formation regions of the p-channel transistor, high concentration of p-type boron is implanted at high energy to form the high concentration p-type source and drain 6.

As shown in FIG. 2C, the photoresist PR ₁ is removed, and then a gate transistor having a depth of about 7000 to 8000 Å is formed in the gate forming region, which is the center of each active region 4, by a photolithography process.

Subsequently, as illustrated in FIG. 2D, the photoresist PR ₂ is deposited on the entire surface, and is exposed and developed to expose a high concentration source and drain formation region of the transistor region and a gate trench region of the p-channel transistor region. Phosphorous ions, which are n-type ions, are implanted with high energy to form a high concentration n-type gate trench 7 and a high concentration n-type source and drain 8 to remove photoresist PR ₂ .

As shown in FIG. 2E, the photosensitive agent PR ₃ is deposited, exposed, and developed to expose the low concentration n-type source and drain formation region of the n-channel transistor region and the low concentration n-type gate trench formation region of the p-channel transistor region. Next, low concentrations of n-type ions boron are implanted into the regions at low energy to form a low concentration n-type source and drain 9 and a low concentration n-type gate trench 10.

Subsequently, as shown in FIG. 2 (f), an oxide film is formed as a whole and then etched back to form a gate trench sidewall 11 and a gate oxide film 12 having a thickness of about 300 microseconds in each gate trench of the n-channel and p-channel transistor regions. Next, as shown in FIG. 2 (g), gate electrode polysilicon 13 and 13a are deposited in each gate trench of the n-type and p-channel transistor regions.

Finally, as shown in FIG. 2 (h), the B.P.S.G film 14 and the metal film 15 are sequentially formed to complete a transistor having a soy structure.

As described above, the present invention has the following effects.

First, since the gate is formed in a trench structure, the difference in topology can be reduced, and thus the movement speed can be increased because the carrier can be easily moved.

Second, since an insulating side wall is formed between the gate and the source / drain, electric field formation between the gate and the source / drain can be prevented.

Thus, carrier movement between the gate and the source / drain can be prevented.

Claims (2)

Depositing an oxide film 2 and a p-type epi layer 3 on the wafer 1 in turn and etching the p-type epi layer 3 at regular intervals to form an active region 4 of the N-channel and p-channel transistors. Forming a field oxide film 5 on the oxide film 2 between the active regions 4, and exposing a portion to be a high concentration source and a drain of the p-channel transistor by a first masking process and then implanting a high concentration p-type ion. And a portion of a high concentration source and drain of the n-channel transistor and a gate of the p-channel transistor in the second masking process by etching a predetermined depth in the center of each active region 4 where the gates of the p-channel and n-channel transistors are to be formed. High-density p-type ion implantation and third masking process are performed after exposing the trench portion to expose the low-density source and drain portion of the n-channel transistor and the gate trench portion of the p-channel transistor. Forming a sidewall oxide film 11 and a gate oxide film 12 in each gate trench by depositing and etching back an oxide film on the entire surface, and then forming a gate electrode 13 in each gate trench. And forming a protective film (14) and a metal film (15) sequentially on the entire surface thereof. The method of claim 1, wherein the gate electrode (13) is formed of polysilicon and the protective film (14) is formed of a BPSG film.