JPS5927098B2 - Method for manufacturing MOS type semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a method for manufacturing a MOS type semiconductor integrated circuit, particularly a semiconductor integrated circuit including a silicon gate MOS transistor having a high melting point metal layer.

BACKGROUND OF THE INVENTION A conventional method of manufacturing a semiconductor integrated circuit device having two N-channel MOS transistor regions arranged adjacent to each other will be described with reference to FIGS. 1 and 2.

First, as shown in FIG. 1, S
Utilizing the oxidation resistance of the i3N4 film (LO-COS method), a thick oxide film 102 is formed in the field isolation region, and then thin gate oxide films 103A and 103B are formed in the active regions of the two transistor regions A and B. Furthermore, a conductive PolySi layer 104 and a high melting point metal layer 105 such as Mo are sequentially formed on the entire surface.

FIG. 2, which shows the next process, shows the situation when mask alignment misalignment occurs in the gate photolithography process.

In order to electrically isolate the gate electrode wiring in transistor regions A and B, high melting point metal layer 105 and conductive P
It is necessary to cut the olySi layer 104 at the same time, but if the pattern of the high melting point metal layer 105A is shifted to the left, the underlying PolySi layer 104A and gate SlO21
When 03A is etched away in a self-aligned manner,
The channel region surface 107 of the MOS transistor is exposed.

If tooth/drain diffusion is performed in this state, the source/drain
Region 107 at the same time as drain diffusion layers 108A and 109A
It is also diffused to form a diffusion layer 110. Therefore, the source and drain of the transistor region A become electrically short-circuited, causing an increase in leakage current between the source and drain regions. In order to prevent this phenomenon, it is necessary to increase the width of the isolation region of the gate pattern in consideration of variations in mask alignment accuracy on the field.
Specifically, this will be explained using FIG. 3. Figure 3 a and b
After the source/drain diffusion process, an interlayer insulating film 11 is applied over the entire surface.
1, source/drain/gate contact holes 112A, 112B, 113A, 113B, 114A,
Open holes 114B and draw out electrodes 115A from each.
, 115B, 116A, 116B, 117A, 117B
This shows the state in which the

In FIG. 3a, 11 is the active interval of the transistor region A (5B), and Δl is the overlap length of the gate pattern onto the field, which needs to be a length that takes into account variations in mask alignment accuracy as described above. is the distance between adjacent gate electrodes determined by the resolution of photolithography.Therefore, the required isolation width 11 is 2.
It becomes Δl+m. As described above, in the conventional method, the active interval 11 between the two transistor regions is designed to include the alignment accuracy Δl of the gate pattern, which has the disadvantage that it is difficult to achieve high integration of the C device.

Further, since the conductive POlySl layer 104 extends on the surface of the SlO2 layer 102, the metal layer 105 is not planarized, resulting in a breakage accident. OBJECTS OF THE INVENTION An object of the present invention is to provide a manufacturing method that enables high integration density of a MOS type semiconductor integrated circuit having a high melting point metal wiring layer.

Furthermore, another object of the present invention is to provide a MOS transistor that can easily separate wiring layers between the gates of adjacent MOS transistors.
An object of the present invention is to provide a method for manufacturing an S-type semiconductor integrated circuit.

Still another object of the present invention is to provide a method for manufacturing a MOS type semiconductor integrated circuit which enables flattened multilayer wiring layers.

Structure of the Invention The method of manufacturing a MOS type semiconductor integrated circuit according to the present invention includes a polysilicon gate M formed by self-alignment.
In a method for manufacturing a MOS type semiconductor integrated circuit including an OS transistor, a conductive layer having etching selectivity with the polysilicon layer extending from a surface of a polysilicon gate electrode region of a polysilicon layer in an active region to at least a surface of a field oxide film is provided. a step of removing the polysilicon layer other than the polysilicon gate electrode region by cenosifalignment, a step of removing the conductive layer on the surface of the field oxide film, and a step of removing the conductive layer and the polysilicon gate. It is characterized by a step of forming source and drain regions using the electrode region as a diffusion mask.

Embodiment of the Invention A method of manufacturing an integrated circuit having two adjacent N-channel MOS transistor regions A and B according to the invention will be described with reference to FIGS. 4 to 10.

First, as shown in FIG. 4, a gate insulating film 202, a POlySi layer 203 doped with donor impurities to become a gate electrode and conductive, and a Si3N4 film 204 to serve as a mask for selective oxidation are formed on the entire surface of a P-type Si substrate 201. Generate each. Next, as shown in FIG. 5, in order to form a field isolation region, a Sl3N4 film 204, a POlySi2O
3. The insulating film 202 is sequentially removed in a self-aligned manner.

Then, a predetermined amount of acceptor impurity is added to the exposed Sl substrate surface 205 in order to prevent the parasitic MOS transistor effect. After that, as shown in FIG.
Selective thermal oxidation is performed using 04A and 204B as masks to form a thick SiO2 film 206 for field isolation.
form. Next, as shown in FIG. 7, the Si3N4 film 204 used as a mask for thermal oxidation is completely removed and the PO
After exposing the surface of ySl2O3, a metal film 207 made of tungsten (W) or molybdenum (MO) with a high melting point and capable of making ohmic contact with the POlySi layers 203A and 203B is coated over the entire surface using an appropriate method such as sputtering or vapor deposition. to form. Therefore, this metal film 207 is connected to each active region of the MOS transistor region A,
Inside B, there is a two-layer structure of POlySl2O3A and 2O3B, and the field isolation SiO2 film 2
06 has a single layer structure of only this metal film 207.
Next, as shown in FIGS. 8A and 8B, the metal film 207 that will become each gate electrode is coated with SiO2 film for field isolation.
The other metal films are removed, leaving a shape connected via the surface of the film 206. Furthermore, as shown in FIG. 8c, the POlySl2O3A, 2O3B in the active regions A, B and the gate oxide films 202A, 202B are removed by etching using the metal film 207 as a mask. Next, after forming the pattern of the metal film 207 and POlySi2O3 in this way, only the metal film 207 is partially removed by photolithography again to separate the gate electrode wiring of the MOS transistor regions A and B as shown in FIG. Then, gate electrodes 207A and 207B are formed, respectively.

Here, the active S between MOS transistor regions A and B
The iO2 film 206 has the minimum width l2 possible with photolithography technology.
The gate electrodes 207A and 207B are formed by the polySi layer 20 in the gate region by the mask alignment deviation Δl.
The pattern is formed with the surfaces of 3A and 203B exposed. Next, as shown in FIGS. 10a, b, and c, diffusion regions 208A, 208B, 209A, and 209B as source/drain regions are formed by a diffusion process as in the prior art, and an interlayer insulating film 210 is further formed on the entire surface. generate.

After that, the source/drain/gate contact holes 21
1A, 211B, 212A, 212B, 213A, 21
3B, and lead electrodes 214A, 21 from each.
4B, 215A, 215B, 216A, and 216B are formed. Effects of the Invention As explained above, according to the manufacturing method of the present invention, even if a mask misalignment occurs when forming a high melting point gate electrode, the gate electrode of an adjacent MOS transistor can be replaced by simply cutting the high melting point metal layer. Can electrically insulate wiring.

Since the surface of the silicon substrate under the gate electrode is not exposed and the underlying conductive Po1ySi layer acts as a mask, there is no accident of short circuit between the source and drain regions during the diffusion process for forming the source and drain regions.

Therefore, the leakage current between the source and drain of the MOS transistor is reduced, and a decrease in yield due to deterioration of breakdown voltage is prevented. Furthermore, since the width l2 of the SiO2 film that isolates adjacent MOS transistor regions can be miniaturized to the resolution limit of photolithography technology, high integration of semiconductor integrated circuits becomes possible.

Furthermore, in the manufacturing method according to the present invention, conductive PoI is formed on the surface of the field isolation region made of thick SiO2.
Since no ySi layer is formed, the surface is flattened, an accident of breakage of the high melting point metal layer is prevented, and a stable multilayer wiring structure with aluminum wiring becomes possible.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the manufacturing process of a conventional MOS type integrated circuit. FIG. 2a is a plan view showing the manufacturing process of a conventional MOS type semiconductor integrated circuit. FIGS. 2b and 2c are cross-sectional views taken along the Ei and Rollo lines of FIG. 2a, respectively.
FIG. 3a is a plan view showing the manufacturing process of a conventional MOS type semiconductor integrated circuit. FIG. 3b is a sectional view taken along the Haha line in FIG. 3a. 4 to 10 are process diagrams for manufacturing a MOS type semiconductor integrated circuit according to the present invention. 8th
Figures b and c are cross-sectional views along the 21-2 line and the Hoch line, respectively, of the plan view of Figure 8a. FIGS. 10b and 10c are cross-sectional views taken along the Hoheline and the tort lines, respectively, of the plan view of FIG. 10a. 201・
... P-type Si substrate, 202 ... Gate insulating film, 203 ... Conductive PolySi film, 20
4... S13N4 film, 206... Thick SiO2 film, 207... High melting point metal film, 208
A, 208B, 209A, 209B... Diffusion region, 210... Interlayer insulating film, 214A, 214
B, 215A, 215B, 216A, 216B...
...Extraction electrode.

Claims (1)

[Claims] 1. In a method for manufacturing a MOS type semiconductor integrated circuit including a polysilicon gate MOS transistor formed by self-alignment, from the surface of a polysilicon gate electrode region of a polysilicon layer in an active region to at least the surface of a field oxide film. a step of forming a conductive layer with etching selectivity with the polysilicon layer extending to the polysilicon layer; a step of removing the polysilicon layer other than the polysilicon gate electrode region by self-alignment; and a step of removing the polysilicon layer on the surface of the field oxide film. A method for manufacturing a MOS type semiconductor integrated circuit, comprising the steps of removing the conductive layer and forming source and drain regions using the conductive layer and the polysilicon gate electrode region as a diffusion mask. 2. The method of manufacturing a MOS type semiconductor integrated circuit according to claim 1, wherein the conductive layer is made of tungsten or molybdenum.