JP3172402B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an LDD (Lightly Doped D).
The present invention relates to an improvement in a method of forming a contact hole in a MOS transistor having a rain) structure.

[0002]

2. Description of the Related Art A method of manufacturing a conventional semiconductor device will be described below with reference to the drawings. 2. Description of the Related Art In recent years, with the miniaturization of semiconductor integrated circuit devices, the development of self-aligned contact (SAC) technology that can eliminate the need for design margin for alignment when forming a contact hole has become active. ing. This is MO
After forming an S transistor, a silicon nitride film (hereinafter, referred to as
It is called a nitride film. ) Is formed over the gate electrode, and the contact hole is formed while protecting the side wall and upper surface of the gate electrode, so that the margin of the design dimension of the contact hole required for uneven alignment is reduced. That is the method.

[0003] In the following, MOS of LDD structure by SAC will be described.
A method for manufacturing a type transistor will be described with reference to the drawings. First, as shown in FIG. 6, a MOS transistor having an LDD structure is formed by a conventional method. As shown in FIG. 6, a gate electrode (4) is formed via a gate insulating film (3) on a p-type silicon substrate (1) separated by a selective oxide film (2). A sidewall (5) is formed on the side wall, and a low-concentration n− type impurity diffusion layer (6A) and a high-concentration n + are formed on the surface of the silicon substrate (1) sandwiching the formation region of the gate electrode (4). It has a structure in which a source / drain region layer (6) formed of a type impurity diffusion layer (6B) is formed.

Next, as shown in FIG. 7, after forming a nitride film (7) and a BPSG (Boron Phoso-Silicate Glass) film (8) on the entire surface, a resist film is formed, and the resist film is formed by photolithography. (9) is selectively formed on the gate electrode (4). Next, as shown in FIG. 8, using the resist film (9) as a mask, the BPSG film (8) and the nitride film (7) are anisotropically etched and removed.

[0005] Next, as shown in FIG.
After peeling off, a SiO2 film (10) is formed on the entire surface, and BP
Using the SG film (8) and the nitride film (7) as masks, the SiO2 film (1
0) is etched to expose the surface of the source / drain region layer (6) to form a contact hole (CH) as shown in FIG. During this etching process,
As shown in FIG. 10, the upper surface of the gate electrode (4) is covered with a nitride film (7) and a BPSG film (8), and the side surfaces are covered with a sidewall (5) and an oxide film (10A). Since the etching is performed while protecting 4), the alignment at the time of the contact hole (CH) is slightly shifted, and the formation region of the contact hole (CH) partially overlaps with the formation region of the gate electrode (4). Even if the gate electrode (4)
Are exposed by the etching at the time of forming the contact hole and lead to the contact hole. When the aluminum wiring (11A, 11B) is formed later in the contact hole (CH), the gate electrode (4) and the aluminum wiring (11A, 11B)
Is suppressed from being short-circuited.

Thereafter, aluminum is formed by sputtering or the like, and is patterned to form aluminum wirings (11A, 11B) as shown in FIG. 11 on the source / drain region layer (6).
Form on top.

[0007]

However, according to the above-mentioned conventional manufacturing method, for example, when the gate electrode length (channel length direction) is 0.35 μm, the nitride film (7) and the BPSG film formed thereon are formed. A resist film (9) serving as a mask of (8) has a thickness of about 0.25 μm at the center on the gate electrode (4).
It must be formed as a pattern with a resist line width of m. This is because if the line width of the resist film (9) is made larger than the gate electrode length, the misalignment between the gate electrode (4) and the resist film (9) causes the relationship between the gate electrode and the source electrode, and the relationship between the gate electrode and the drain electrode. Becomes asymmetric. The relative permittivity of the oxide film is 3.8, the relative permittivity of the nitride film is as high as about 6, and the distance between the gate electrode and the drain electrode varies. Not preferred. For this reason, a resist pattern as thin as 0.25 μm has to be formed. However, a new exposure apparatus such as a KrF excimer laser having a high resolution is required for that purpose, resulting in an increase in cost.

When etching is performed using the thinned resist film (9) as a mask, the end of the gate electrode (4) is exposed as shown in FIG. 8, and the nitride film (7) and BPSG are removed. The film (8) cannot cover this sufficiently. When an aluminum electrode is formed thereon, the gate electrode and the source / drain are short-circuited. for that reason
An SiO2 film (10) is formed from its upper surface, and the entire surface is etched to form a contact while covering the gate electrode (4) with an SiO2 film (10A), a nitride film (7), and a BPSG film (8) as shown in FIG. A hole (CH) is formed.

However, since the SiO2 film (10A) is formed by a low-pressure CVD method or the like having high uniformity in the process of forming the SiO2 film (10A), it is formed on the gate electrode (4) as shown in FIG. Since the thickness of the SiO2 film (10) formed on the source / drain region layer (6) becomes substantially equal to the thickness of the SiO2 film (10), the contact hole (C
H) In the entire surface etching step at the time of formation, the SiO2 film (10A) does not remain so thick as shown in FIG.

Thereafter, when the aluminum electrodes (11A, 11B) are formed, as shown in FIG.
A, 11B) and the gate electrode (4) become narrower, so that the parasitic capacitance between them becomes larger, the element becomes slower, and a voltage applied during this time causes electrostatic breakdown. There were also problems such as becoming easier.

On the other hand, what if the SiO2 film (10A) is formed not by low pressure CVD but by normal pressure CVD in the process of forming the SiO2 film (10A)? In this case, a depression (12) occurs as shown in FIG. 12, and the film thickness becomes thin at the position of the depression (12). On the other hand, 1000 to fill the depression (12)
When the heat treatment is performed at a temperature of not less than ° C., the diffusion depth of the source / drain layer becomes deep as shown in FIG.

The depressions (12) are formed by a gate electrode (4) 2000Å, a nitride film (7) 1000Å, and a BPSG
The film (8) becomes remarkable due to a total of 8000 ° steps of 5000 °. If this step is small, the depression (12) is also small, and the depression (12) can be filled by heat treatment at 900 ° C.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks. As shown in FIG. 1, as shown in FIG.
A gate electrode is formed with a gate insulating film interposed therebetween, a sidewall made of an insulating film is formed on a side wall of the gate electrode, and a low-concentration reverse conductivity type impurity is formed on the surface of the semiconductor substrate with the gate electrode formation region interposed therebetween. Forming a first oxide film by a normal pressure CVD method on a MOS transistor in which a source / drain region layer formed of a diffusion layer and a high-concentration reverse conductivity type impurity diffusion layer is formed; FIG. Etching the entire surface of the first oxide film so as to selectively leave the first oxide film so as to cover the gate electrode and the sidewalls, as shown in FIGS. 3 and 4. Forming a nitride film and a second oxide film in this order, and selectively removing the nitride film and the second oxide film in a source / drain region layer formation region to form an opening; as shown in FIG. Above Having a step of forming a metal wiring in the opening to increase the distance between the gate electrode and the metal wiring when forming the contact hole, reduce the parasitic capacitance between the gate electrode and the metal wiring, speed up the operation of the element, and cause electrostatic breakdown. It is possible to provide a semiconductor device in which is suppressed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. 1 to 5 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present embodiment. Hereinafter, a method of manufacturing a MOS transistor having an LDD structure using the SAC will be described with reference to the drawings.

First, as shown in FIG.
A MOS transistor having a structure is formed. As shown in FIG. 1, a gate insulating film (2) is formed on a p-type silicon substrate (21) in which elements are separated by a selective oxide film (22).
3), a gate electrode (24) is formed, a sidewall (25) is formed on a side wall thereof, and a gate electrode (2) is formed.
On the surface of the silicon substrate (21) sandwiching the formation region of 4),
The transistor has a structure in which a source / drain region layer (26) including a low-concentration n− type impurity diffusion layer (26A) and a high-concentration n + type impurity diffusion layer (26B) is formed.

The entire surface of the upper surface of the MOS transistor having the LDD structure is formed by a normal pressure CVD method and is an example of a first oxide film having a thickness of 3000 ＰＳ of PSG (Phoso-Silicate G).
An SiO2 film (27) made of glass (lass) is formed. The conditions at this time are a temperature of 400 ° C. and 1 atm, and a phosphorus concentration of PSG is 8 wt%. Formed in this way
By annealing the SiO2 film (27) in an N2 atmosphere at 900 DEG C. for 30 minutes, the thickness of the SiO2 film (27) on the upper surface of the source / drain region layer (26) is reduced as shown in FIG. Then, the thickness (a) of the SiO2 film (27) on the upper surface of the gate electrode (24) and the SiO2 film (2) near the sidewall (25)
The film thickness (b) of 7) is formed thick. This is because a normal pressure CVD method is used in which film thickness is not so good as compared with a low pressure CVD method or the like at the time of film formation.

This fact is described in the literature ACAdama and CDCap
io, "Planarization of Phosphorus-Doped Silicon Dio
xide "Journal of Electrochemical Society 128,423 (1
981). According to this document, the thickness (a) of the SiO2 film (27) on the upper surface of the gate electrode (24) shown in FIG.
And the thickness (b) of the SiO2 film (27) near the sidewall (25) and the upper surface of the source / drain region layer (26).
The ratio of the SiO2 film (27) to the film thickness (c) is approximately a: b: c = 10: 13: 8, and a and b are formed thicker than c. Is shown.

Next, as shown in FIG. 2, the SiO2 film (27)
Is entirely etched to form a source / drain region layer (2
6) is exposed. Then, the thickness (a) of the SiO2 film (27) on the upper surface of the gate electrode (24) and the side wall (2)
5) Since the thickness (b) of the nearby SiO2 film (27) is formed to be thicker than the thickness (c) of the SiO2 film (27) on the upper surface of the source / drain region layer (26), When the / drain region layer (26) is exposed, the SiO2 film (27) remains so as to sufficiently cover the gate electrode (24) and the sidewall (25) as shown in FIG.

Next, as shown in FIG.
00Å nitride film (28), 5000Å BPSG
[Boron Phoso-Silicate Glass] A film (29) is formed. Next, after forming a resist film (not shown) by a photolithography method, an opening is formed at a position where a contact hole is to be formed, and this is used as a mask to form a BPSG film (2).
9), by anisotropically etching and removing the nitride film (28), as shown in FIG.
To form

Thereafter, aluminum is formed by sputtering or the like, and is patterned to form aluminum wirings (30A, 30B) as shown in FIG.
Form on top. According to the above-described manufacturing method according to the present embodiment, since the normal pressure CVD method is used when forming the SiO2 film (27), the entire surface of the gate electrode (24) is etched as shown in FIG. Top and side walls (2
An SiO2 film (27) is formed so as to sufficiently cover the side wall of (5).

Thereafter, the nitride film (28) and the BPSG film (2
Even if the contact hole (CH) is formed by forming 9), as shown in FIG. 4, the distance between the contact hole (CH) and the gate electrode (24) is sufficient as compared with the conventional case as shown in FIG. Wide, then aluminum wiring (30A, 30B)
Is formed in the contact hole (CH), the distance between the aluminum wiring (30A, 30B) and the gate electrode (24) is sufficiently large.
During this time, it is possible to avoid problems such as an increase in the parasitic capacitance, a decrease in the operation speed of the element, and the occurrence of electrostatic breakdown due to the voltage applied during this time.

[0022]

As described above, according to the semiconductor device of the present invention, a gate electrode is formed via a gate insulating film on a semiconductor substrate of one conductivity type in which a device is separated by a selective oxide film. Sidewalls made of an insulating film are formed on the side walls of the gate electrode, and are formed on the surface of the semiconductor substrate with a low-concentration reverse-conductivity-type impurity diffusion layer and a high-concentration reverse-conductivity-type impurity diffusion layer sandwiching the gate electrode formation region. A normal pressure C is applied on the MOS transistor on which the source / drain region layers are formed.
Since the first oxide film is formed by a relatively low heat treatment at 900 ° C. by the VD method, the first oxide film is formed thick on the protruding upper surface of the gate electrode, the upper surface and the side wall of the sidewall, and It is formed thin on the semiconductor substrate on the / drain region layer. In addition, the heat treatment at 900 ° C. has an advantage that the source / drain region layer does not become too deep.

Thereafter, the first oxide film is entirely etched to remove the first oxide film on the source / drain region layer but still leave the first oxide film on the gate electrode and the sidewall.
Since the oxide film selectively remains so as to sufficiently cover them, a nitride film and a second oxide film are sequentially formed thereafter, and the nitride film and the second oxide film in the formation region of the source / drain region layer are formed.
Even if an oxide film is selectively removed to form an opening, the distance between the opening and the gate electrode is sufficiently large.

The resist pattern that determines the contact area is a pattern of 0.35 μm or more,
There is an advantage that a resist pattern can be formed by a line stepper. Therefore, even if a metal wiring is formed in the opening, the parasitic capacitance between the metal wiring and the gate electrode can be reduced due to the large distance between the metal wiring and the gate electrode, so that the device can be prevented from operating at a low speed. It is possible to suppress the occurrence of electrostatic breakdown due to the applied voltage.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a first sectional view illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIG. 7 is a second cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIG. 8 is a third sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 9 is a fourth cross-sectional view illustrating the method of manufacturing the semiconductor device according to the conventional example.

FIG. 10 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 11 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 12 is a seventh sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 13 is an eighth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 21/768

Claims (1)

(57) [Claims] 1. A gate electrode is formed via a gate insulating film on a semiconductor substrate of one conductivity type in which an element is separated by a selective oxide film, and a sidewall made of an insulating film is formed on a side wall of the gate electrode. A MOS transistor having, on the surface of the semiconductor substrate, a source / drain region layer formed of a low-concentration reverse-conductivity-type impurity diffusion layer and a high-concentration reverse-conductivity-type impurity diffusion layer with the gate electrode formation region interposed therebetween; A step of forming a first oxide film thereon by a normal pressure CVD method, and selecting the first oxide film so as to cover the gate electrode and the sidewall by etching the entire first oxide film. Forming an opening by sequentially forming a nitride film and a second oxide film, and selectively removing the nitride film and the second oxide film in a source / drain region layer formation region; Forming a metal wiring in the opening.