516173 A7 五、發明說明（ 發明領域： 本發明係關於一種製造半導體裝置 * , 套’特別盥剎 用可棄式間隙壁製造自行對準接觸窗（self j、 contact ’ SAC)之方法有關。本發明在深次微米金氧3^ = 效電晶體裝置中，提供—較大製程自由度。 、琢 發明背景： 經濟部智慧財產局員工消費合作社印製 白 積體電 度快和 續致力 種趨勢 半導體 電容等 相較以 其中一 窗在晶 準接觸 的許多 半導體技術被應用於製造積體電路；近十幾年來， 路設計者一直期望以更快的腳步製造出尺寸小、速 禮度问的電子元件。於是，增加晶片的積集度和持 於縮小半導體元件之尺寸，成為半導體製造業的一 。隨者疋件密度的提高和彼此間隔愈來愈接近，在 基板當中或在其上製造的半導體元件（如電晶體、 )必須愈做愈小。因而元件之間的對準及黃光技術 往更形重要。而傳統的自行對準接觸窗的製程便是 種被發展來克服這項挑戰的技術❶但是，隨著接觸 圓上的特徵結構（閘極間距）的縮小，傳統的自行對 窗之製程自由度也降低；甚至，衍生了製程整合上 問題。請見說明如下。 當電子裝置縮小至小於0 · 1 8微米的尺度，先前技術 在形成自行對準接觸窗之過程中，將遭遇困難，如第一圖 -------」----Ί·裝------- (請先閱讀背面之注意事項再填寫本頁} 訂--------- 516173 A7 B7 五、發明說明（） 所示。閘極氧化層3與多晶矽閘極5在半導體基板1上形 成。接著，一金屬矽化層5a在閘極5上形成，以降低電 阻。而後’由氮化矽組成之蓋層（cap layer)7覆蓋在閘極 ；結構之表層上方。通常，保護蓋層7係做為SAC蝕刻屏障， 以免閘極被姓则。用以降低熱載子效應的輕換雜沒極 15(Lightly Doped Drain, LDD)’可直接在有保護蓋層7 的閘極形成後做離子佈植形成；，或在一較薄之氧化層9形 成在閘極之側壁和基板上後，再做離子植入。由氮化矽組 成之側壁間隙壁11在閘極結構之側壁形成，用以在閘極 結構旁之基板1當中形成主動區域1 3，如源極與汲極。利 用非均向性姓刻（a n i s 〇 t r 〇 p i c e t c h)製造間隙壁 Π之 後’用以形成間隙壁11之一部份材料會留在保護蓋層7 # 之上層表面。 請參閱第二圖，一無邊緣氮化矽層1 7沿著上述表層 結構之特徵均勻地形成。其中無邊緣氮化石夕層1 7之功用 係保護用於元件絕緣的淺溝隔絕層（Shallow Trench Isolation， ST 1)23區域，在接觸窗製程中不受損傷。 同時，亦有改善在蝕刻時，間隙壁11之可靠性，以及調 整其後接觸窗之寬度的功能。而後，形成一介電層19，以 r 覆蓋無邊緣氮化矽層1 7、閘極結構、氮化物蓋層7，以及 側壁間隙壁11，而此介電層可由硼磷矽玻璃（BPSG)形成。 一光阻圖案（未表示出）在介電層19上形成，接著在介電 層1 9上進行乾蝕刻，以於BPSG 1 9中形成接觸窗21，隨 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝 iI--I!訂----- 經濟部智慧財產局員工消費合作社印製 516173 A7 B7 五、發明說明（ 後移除此光阻層。一導電材料將填充至接觸窗21當中， 接著藉由化學機械式麻 锇式磨先進仃平面化，以於該處形成導雷 性插塞。 °月參閱第-圖。在傳統的自行對準接觸窗製程，各間 隙壁間之取紐距離(以d表示）約等於D_2(L^ + Wspa…）， -I # 其"代表閑極5間距離；w。心與…:則分別代表氧化 層9與間隙壁π之寬度。在目前製程參數下，d之寬度小 於〇·19微米，而W°xide與Ip…之寬度則分別大於等於1〇〇 微米與400微米。若再加上無邊緣氮化石夕層17加入製程 田中’則接觸窗21之寬度將被擠壓至小於0.05微米。接 觸窗之縱橫比（接觸窗深度與寬度之比值）約為 9(0·45/0·05)，這在深次微米製程中，將衍生許多製程上 的困擾，如被擠壓之接觸窗將對溝填（gap filling)之步 驟造成影響’其使重新填充材料至接觸窗變得困難。另一 方面，閘極間之介電材料（特別是留在結構中的氮化矽側 壁間隙壁11)將使與寄生電容有關之問題更惡化。強電容 器耦合將增長由接線之寄生電容所導致之阻容（RC)時間 延遲。另外，在氮化矽間隙壁角落產生之強應力，也被視 為是造成基板缺陷形成的一大主因。 因此’吾人需要一新的形成自行對準接觸窗之方法 以應用於砍半導體電子元件的製造。 本紙^.尺度適用中國國家標準（CNS)A4 五、發明說明（） 登明目的；S _埽· 本發明之目的之一 ▲ 係^供一製造具有自 窗積體電路之方法，邗日了 ^ 並且可以解決上述之問題 本發明之另一目沾，#516173 A7 V. Description of the invention (Field of the invention: The present invention relates to a method for manufacturing a semiconductor device *, a disposable spacer for a special brake, and a method for manufacturing a self-aligning contact window (self j, contact 'SAC). This It was invented in the deep sub-micron gold oxide 3 ^ = effect transistor device to provide—larger process freedom. Background of the invention: The printed consumer electronics cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs have printed electricity and continued to work on this trend. Compared with many semiconductor technologies such as semiconductor capacitors, which are in quasi-contact with one of the windows, they are applied to the fabrication of integrated circuits. For more than a decade, road designers have been looking forward to making small-sized, quick-styling products at a faster pace. Electronic components. Therefore, increasing the accumulation of wafers and reducing the size of semiconductor components has become one of the semiconductor manufacturing industries. As the density of components increases and the distance between them becomes closer, they are manufactured in or on substrates. Semiconductor components (such as transistors, etc.) must be made smaller and smaller. Therefore, the alignment between components and yellow light technology are more important. Traditional self-alignment The process of quasi-contact windows is a technology that has been developed to overcome this challenge. However, with the shrinking of the characteristic structure (gate spacing) on the contact circle, the traditional freedom of the process of self-aligning windows also decreases; even, The problem of process integration has been derived. Please see the description below. When the electronic device is reduced to a size smaller than 0 · 18 microns, the prior art will encounter difficulties in forming the self-aligning contact window, as shown in the first figure --- ---- "---- Ί · 装 ------- (Please read the notes on the back before filling out this page} Order --------- 516173 A7 B7 V. Description of the invention ( ). A gate oxide layer 3 and a polycrystalline silicon gate 5 are formed on the semiconductor substrate 1. Then, a metal silicide layer 5a is formed on the gate 5 to reduce the resistance. Then, a capping layer composed of silicon nitride ( Cap layer) 7 covers the gate; above the surface of the structure. Usually, the protective cap layer 7 is used as a SAC etching barrier to prevent the gate from being named. Lightly Doped 15 (Lightly Doped to reduce the hot carrier effect) Drain, LDD) 'can be implanted directly after the gate with protective cap 7 is formed; Or, after a thin oxide layer 9 is formed on the side wall of the gate and the substrate, ion implantation is performed. A side wall spacer 11 composed of silicon nitride is formed on the side wall of the gate structure, and is used for the gate. An active region 13 is formed in the substrate 1 next to the structure, such as a source and a drain. Anisotropic surnames (anis 〇tr 〇picetch) are used to manufacture the spacer Π 'to form part of the material of the spacer 11 It will remain on the upper surface of the protective cap layer 7 #. Please refer to the second figure, a non-edge silicon nitride layer 17 is uniformly formed along the characteristics of the surface structure described above. The function of the non-edge nitride nitride layer 17 is to protect the Shallow Trench Isolation (ST 1) 23 area used for element insulation from damage during the contact window process. At the same time, it also has the function of improving the reliability of the partition wall 11 during etching, and adjusting the width of the contact window thereafter. Then, a dielectric layer 19 is formed to cover the edgeless silicon nitride layer 17, the gate structure, the nitride capping layer 7, and the sidewall spacer 11 with r. The dielectric layer may be made of borophosphosilicate glass (BPSG). form. A photoresist pattern (not shown) is formed on the dielectric layer 19, and then dry etching is performed on the dielectric layer 19 to form a contact window 21 in the BPSG 19. With 3 paper sizes, Chinese national standards ( CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page)-Install iI--I! Order ----- Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 516173 A7 B7 V. Description of the invention (The photoresist layer is removed afterwards. A conductive material will be filled into the contact window 21, and then a planarization is performed by a chemical-mechanical mochi-type mill to form a lightning-conducting plug there. ° Refer to the figure-. In the traditional self-aligning contact window process, the distance between the gap walls (represented by d) is approximately equal to D_2 (L ^ + Wspa…), -I # 其 " 5 distances; w. Heart and…: respectively represent the width of the oxide layer 9 and the gap π. Under the current process parameters, the width of d is less than 0.19 microns, and the width of W ° xide and Ip ... are greater than It is equal to 100 microns and 400 microns. If a non-edge nitride layer 17 is added to the process Tanaka ', then The width of window 21 will be squeezed to less than 0.05 micron. The aspect ratio of the contact window (the ratio of the depth and width of the contact window) is about 9 (0 · 45/0 · 05), which will be derived in the deep submicron process Many process problems, such as the squeezed contact window, will affect the gap filling process. It makes it difficult to refill the material to the contact window. On the other hand, the dielectric material between the gates ( Especially the silicon nitride sidewall spacers 11) left in the structure will worsen the problems related to parasitic capacitance. Strong capacitor coupling will increase the resistance-capacitance (RC) time delay caused by the parasitic capacitance of the wiring. In addition, in The strong stress generated in the corners of the silicon nitride gap walls is also considered to be a major cause of the formation of substrate defects. Therefore, 'I need a new method of forming self-aligned contact windows for the manufacture of semiconductor electronic components. This paper ^. The standard is applicable to the Chinese National Standard (CNS) A4. 5. Description of the invention () The purpose of the invention; S _ 埽 · One of the purposes of the invention ▲ Department ^ For a method of manufacturing a circuit with a self-winding integrated circuit ^ And available Another object of solving the above problems of the present invention James, #
的係耠供以可移除式間R 行對準接觸窗之方法。 首先，閘極氧化層多晶石夕層，以及氮化物 沈積在基板上。而後，閘極氧化層、多晶矽層， 矽層經圖案化以形成一閘極結構。接著，一氧化 熱處理，選擇性地形成於閘極表面與基板上。上 層係做為進行輕摻雜汲極植入之緩衝層。以離子 輕摻雜汲極後，一薄襯墊層沈積於基板之特徵結 上述之襯墊層係以氮化物為材料所組成，且厚g 埃（angstroms)至100埃之間。可移除式間隙 形成並附著在襯墊層邊，而間隙壁之材料，最好 容易移除之特性。由矽酸四乙酯（TE〇s)所構成之 其中一選擇。源極與汲極隨後藉由高劑量離子佈 閘極結構與間隙壁做為佈植遮罩，形成於基板中 而後’利用氫氟酸溶液或緩衝氧化钱刻| Oxide Etchant, B0E)，以濕性浸泡法去除可移 壁。整體結構將回復至沈積矽酸四乙酯間隙壁 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） '對準接觸 壁製造自 蓋層分別 以及II化 碎層藉由 述之氧化 佈植形成 構表面。 L約為50 壁相繼地 能夠呈現 氧化層係 植，利用 除式間隙 之前的結 516173 其表示根據先前技術 其表示根據先前技術 其表示先前技術之自 其表示根據本發明所 其表示根據本發明以 A7 五、發明說明（） 構。其後，進行一選擇性步驟於氮化層表面形成無邊界 層。此無邊界層係用以確定在進行自行對準接觸窗蝕刻 時’淺溝絕緣層和閘極將不會被蝕刻。無邊緣氮化層之厚 度係介於1 5 0埃與2 5 0埃之間。於閘極結構上形成之介電 層，可由二氧化矽、硼磷矽玻璃與氧化矽玻璃（s〇G)組成。 ,隨後，圖案化一光阻於介電層上，以定義出接觸窗區域。 圖式簡單說明： 第一圖係半導體晶圓之剖面圖 所形成電晶體之步驟； 第二圖係半導體晶圓之剖面圖 所形成自行對準接觸窗孓步驟； 第二圖係半導體晶圓之剖面圖 行對準接觸窗結構； ♦ 第四圖係半導體晶圓之剖面圖 形成電晶體之步驟； 第五圖係半導體晶圓之剖面圖 可移除式間隙壁形成自行對準接觸窗之步驟； '第六圖係半導體晶圓之剖面圖，其表示根據本發明所 形成之自行對準接觸窗構造。 W虎對照說日q : ------^—-—•裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製The system provides a way to align the contact windows between removable rows. First, a gate oxide polycrystalline layer and a nitride are deposited on the substrate. Then, the gate oxide layer and the polycrystalline silicon layer are patterned to form a gate structure. Next, an oxide heat treatment is selectively formed on the gate surface and the substrate. The upper layer is used as a buffer layer for lightly doped drain implantation. After lightly doping the drain with ions, a thin pad layer is deposited on the substrate. The above pad layer is made of nitride and has a thickness between angstroms and 100 angstroms. Removable gaps are formed and attached to the edge of the cushion layer, and the material of the gap wall is preferably easy to remove. One option consists of tetraethyl silicate (TE0s). The source and drain electrodes are then formed using a high-dose ionic gate structure and a spacer as a planting mask, formed in the substrate, and then 'etched with hydrofluoric acid solution or buffered oxide | Oxide Etchant, B0E), wet Sexual immersion removes removable walls. The overall structure will be restored to the deposited tetraethyl silicate spacer wall 5 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 'The contact wall is manufactured from the cover layer and the II layer separately by Said oxidative implantation forms a textured surface. L is about 50. The wall can successively present an oxide layer plant, using the knot before the division gap 516173, which represents according to the prior art, which represents according to the prior art, which represents the prior art, according to the present invention, which represents according to the present invention, A7 V. Description of Invention () Structure. Thereafter, a selective step is performed to form a borderless layer on the surface of the nitride layer. This borderless layer is used to determine that the 'shallow trench insulation layer and gate will not be etched during self-aligned contact window etching. The thickness of the edgeless nitride layer is between 150 angstroms and 250 angstroms. The dielectric layer formed on the gate structure may be composed of silicon dioxide, borophosphosilicate glass, and silicon oxide glass (SOG). Then, a photoresist is patterned on the dielectric layer to define a contact window area. Brief description of the drawings: The first diagram is a step of forming a transistor in a cross-sectional view of a semiconductor wafer; the second diagram is a step of forming a self-aligned contact window in a cross-section of a semiconductor wafer; The cross-sectional view is aligned with the contact window structure. ♦ The fourth drawing is the step of forming a transistor in the cross-sectional view of the semiconductor wafer. The fifth drawing is the step of forming a self-aligned contact window in the cross-section view of the semiconductor wafer. 'The sixth figure is a cross-sectional view of a semiconductor wafer, which shows a self-aligned contact window structure formed according to the present invention. W Tiger compares the day q: ------ ^ ----- • install -------- order --------- (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
A7A7
1基板 3閘極氧化層 5多晶碎閘極 6多晶秒層 8第一氮化矽層 1 〇氧化矽層 1 2薄襯塾層 1 4間隙壁 1 6輕摻雜汲極 1 8源極與汲極 20無邊界層 22介電層 2 4接觸窗 2 6淺溝隔絕層 發明詳細势、明· 2基板 4閘極氧化層 5 a金屬矽化層 7保護蓋層 9氧化層 11間隙壁 1 3 '主動區 1 5輕摻雜汲極 1 7氮化矽層 19介電層 21接觸窗 2 3淺溝隔絕層 7 — — —----------I -----I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本發明將參酌圖式 種製造自行對以做4細之說明。本發明提供- — ®之方法。再者，本發明可用以改1 阻谷時間延遲問 _ θ加閘極間之間距，以及降低在傳統 氮化閘極角落產峰 y 之應力。請參閱第四圖，單晶體基板2 係-晶體方向"00]之p型或N型基板。在建構元件之前， :場氧化區或溝渠絕緣區之I缘區域，將預先形成於半導 體基板上，以做為元件間之絕緣。例如，在基板上利用塾 7 516173 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 氧化層與氮化矽層’做為氧化屏F章’以形成場氧化層區。 隨後石夕基板於氧氣環境被氧化，而形成場氧化層區。此氧 化層區之厚度約侧至咖埃。上述製程完成後，利用 傳統之濕㈣，移除氮切層與墊氧化層。所謂的淺溝隔 絕層 26(Shal l〇w Trenrh T 4· . 0 wench Is〇latlon， STI)亦可用於替 代場氧化層區。 閘極氧化層4與多晶矽層6分別沈積於基板2。通常， 閘極氧化層4係利用包含氧氣在内之反應氣體，經熱處理 而形成。閘極氧化層4亦可以低溫化學氣相沈積法形成， 例如使用矽烷（silane)作為前導物質（precurs〇r)之電漿 化學氣相沈積。閘極氧化層4可利用其他已知之氧化物與 程序而形成。例如’藉由化學氣相沈積過程，在攝氏3〇〇 至450度之下，以石夕酸四乙酯作為源（s〇urce)，可形成氧 化矽層1 0。多晶矽層6係作為金氧半導體之閘極，並經由 化學氣相沈積至厚度約在1 〇 〇 〇埃至2 〇 〇 〇埃。在習知技術 中’金屬石夕化物6 a可選擇性地在多晶石夕上形成。 第一氮化矽層8隨後在多晶矽層上形成，作為蓋層或 硬遮罩’用以保護閘極。其後，以光阻層做為蝕刻遮罩， 餘刻閘極氧化層4、多晶矽層6及第一氮化矽層8，以形 成具有蓋層之閘極結構。第一氮化石夕層8可利用低壓化學 氣相沈積法（Low Pressure Chemical Vapor Deposition， LPCVD) ’藉由和二氣曱石夕炫（dichlorosilane)與氨作用而 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） ;1--_----------^--------- (請先閱讀背面之注意事項再填寫本頁) 516173 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（） 形成。第一氮化矽層8之厚 間。 厚度約介於500埃與1 000埃之 其後’氧化矽層1 0經由埶 …處理，選擇性地形成 極與基板上。氧化矽層丨0 成於閘 仙之厗度約介於5〇埃與15〇 間，而任何適當的厚度皆可。 令之 手又S 了形成乳化矽層10之目的係 在於提供一緩衝區，以進行輕摻雜没極植入。首先，利用 4離子佈植法形成輕摻雜汲極16，而後一薄襯墊層12沈積 於基板2之特徵結構上。i述薄概塾層之厚度約介於Μ 埃與100埃之間。形成此薄襯墊層之材料係由氮化物所組 成。薄襯墊層形成後，形成可移除式間隙壁之枒料，接連 地沈積於薄襯墊層1 2之上。形成間隙壁之材料，最好能 夠具有容易移除之特性，而由矽酸四乙酯所構成之氧化層 係其中一選擇。例如，藉由化學氣相沈積法，在攝氏3〇〇 至450度之下，以矽酸四乙酯作為源，可形成氧化矽層。 ,矽酸四乙酯之厚度約20 0埃與8 0 0埃之間，並可隨元件汲 極之需要做適當调整。如第四圖所示，利用非均向性钱刻 法蝕刻矽酸四乙酯氧化層，以形成間隙壁1 4，使其附著於 由閘極氧化層4、閘極6與第一氮化矽層8所組成之閘極 結構之側壁。源極與汲極1 8隨後藉由高劑量離子佈植， 利用閘極結構與間隙壁1 4做為植入遮罩，而形成於基板2 中。 參閱第五圖，形成源極與汲極1 8之後，可移除式間 良紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^ --------^---------.^91. (請先閱讀背面之注意事項再填寫本頁) M6173 A7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明（ 隙壁14隨後被移除。在一 ^ 貫施例中’係利用氫氟酸溶液 或緩衝氧化蝕刻劑，以省从、* /…、性次泡法去除可移除式間隙壁 14。亂化碎層 1 2將仅罐、&、廿 ’、5蔓淺溝絕緣層和閘極免於在蝕刻和 移除過程中與被蝕刻，而整 S體、、去構亦將回復至沈積石夕酸四 乙酯之前的結構。其後，推 、设進仃一選擇性步驟於第一氮化層 12表面形成無邊界層盔a …、邊界層20係用以確定在進行 :亍ί準接觸窗#刻時，淺溝爸緣層區域不會被餘刻。若 氮化層1“之厚度足夠的話，無邊界層即可略除。無邊界 層2〇之材料為氣化物，且其厚度約從150埃至250埃。 w電層2 2於閘極結構上形成約2 5 〇 〇埃至& 〇⑽埃之 厚又，丨電層22可由二氧化石夕' 獨碌石夕玻璃與氧化石夕玻 璃組成。隨後，圖案化一光阻（未表示出）於介電層22 上，以定義出接觸窗區域。上述光阻有一開口對準於基板 之接觸窗。而後以氧化物與氮化物之高選擇性蝕刻過程， 蝕刻介電@ 22。介電層22係供作絕緣層，以隔絕基板2 以及接續覆蓋其上之各層。#中覆蓋其上之各層，係用於 内連線或類似之用途。用於介電層22、氮化矽層12與/ 或無邊界層之間之高選擇性蝕刻反應氣體，包含一氧化 碳、環-八氟丁烷（GF8)與四氟甲烷（CF4)等。藉由蝕刻劑， 使二氧化矽之蝕刻速率大於氮化矽之蝕刻速率。氮化矽層 20、1 2以及第一氮化矽層8係供作蝕刻屏障，以於介電層 22中形成接觸窗24。因此，高選擇性蝕刻製程可改善接 觸窗之精確度。1 substrate 3 gate oxide layer 5 polycrystalline gate 6 polycrystalline second layer 8 first silicon nitride layer 1 silicon oxide layer 1 2 thin liner layer 1 4 spacer wall 1 6 lightly doped drain electrode 1 8 source Electrode and drain electrode 20 no boundary layer 22 dielectric layer 2 4 contact window 2 6 shallow trench insulation layer invention details, clear · 2 substrate 4 gate oxide layer 5 a metal silicide layer 7 protective cover layer 9 oxide layer 11 gap wall 1 3 'active region 1 5 lightly doped drain 1 7 silicon nitride layer 19 dielectric layer 21 contact window 2 3 shallow trench isolation layer 7 — — —---------- I ---- -I (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This invention will refer to the production of drawings to make detailed explanations. The present invention provides a -® method. Furthermore, the present invention can be used to change the valley delay time delay θ θ plus the gap between the gates and reduce the stress of peak y generated at the corner of the traditional nitrided gate. Please refer to the fourth figure, the single crystal substrate 2 is a p-type or N-type substrate with crystal orientation " 00]. Before the components are constructed, the I-edge area of the field oxidation area or trench insulation area will be formed on the semiconductor substrate in advance to serve as insulation between the components. For example, it is printed on the substrate using 塾 7 516173 A7 B7, the Intellectual Property Bureau of the Ministry of Economic Affairs, the Employees' Cooperatives, and the fifth, the invention description (the oxide layer and the silicon nitride layer are used as the oxide screen F chapter) to form the field oxide layer. The substrate is oxidized in an oxygen environment to form a field oxide layer region. The thickness of this oxide layer region is about 300 angstroms to the side. After the above process is completed, the conventional wet layer is used to remove the nitrogen cutting layer and the pad oxide layer. The so-called Shallow trench isolation layer 26 (Shal l0w Trenrh T 4.. 0 wench Isolatlon, STI) can also be used in place of the field oxide layer region. Gate oxide layer 4 and polycrystalline silicon layer 6 are deposited on substrate 2, respectively. Generally, the gate The polar oxide layer 4 is formed by using a reaction gas including oxygen and subjected to heat treatment. The gate oxide layer 4 can also be formed by a low-temperature chemical vapor deposition method, for example, using silane as a precursor of a precursor. Slurry chemical vapor deposition. The gate oxide layer 4 can be formed using other known oxides and procedures. For example, 'through chemical vapor deposition process at 300 to 450 degrees Celsius, tetraethyl oxalate Ester as source sorcure), a silicon oxide layer 10 can be formed. The polycrystalline silicon layer 6 is used as a gate of a gold-oxide semiconductor, and is deposited by chemical vapor deposition to a thickness of about 1000 Angstroms to 2000 Angstroms. In the technology, 'metallic oxide 6 a can be selectively formed on polycrystalline silicon. The first silicon nitride layer 8 is then formed on the polycrystalline silicon layer as a cap layer or hard mask' to protect the gate. Then, a photoresist layer is used as an etching mask, and the gate oxide layer 4, the polycrystalline silicon layer 6, and the first silicon nitride layer 8 are etched to form a gate structure with a capping layer. The first nitride nitride layer 8 may Use of Low Pressure Chemical Vapor Deposition (LPCVD) 'By using the interaction of dichlorosilane and ammonia, this paper applies Chinese National Standard (CNS) A4 (210 χ 297) %); 1 --_---------- ^ --------- (Please read the precautions on the back before filling out this page) 516173 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Preparation A7 V. Description of the invention () Formation. The thickness of the first silicon nitride layer 8 is between 500 angstroms and 1,000 angstroms. The post-'silicon oxide layer 10 is selectively formed on the substrate and the substrate through the 埶 ... treatment. The silicon oxide layer is formed at a gate of approximately 50 angstroms and approximately 50 angstroms, and any suitable thickness is Yes. The purpose of forming the emulsified silicon layer 10 is to provide a buffer zone for lightly doped implantation. First, the lightly doped drain 16 is formed by the 4 ion implantation method, and the latter A thin pad layer 12 is deposited on the characteristic structure of the substrate 2. The thickness of the thin layer is approximately between M Angstroms and 100 Angstroms. The material forming the thin backing layer is composed of a nitride. After the thin backing layer is formed, a removable spacer is formed and deposited on the thin backing layer 12 in succession. The material for forming the partition wall is preferably one which can be easily removed, and an oxide layer composed of tetraethyl silicate is one of the choices. For example, a silicon oxide layer can be formed by a chemical vapor deposition method at a temperature of 300 to 450 degrees Celsius using tetraethyl silicate as a source. The thickness of tetraethyl silicate is between about 200 angstroms and 800 angstroms, and can be adjusted appropriately according to the needs of the device drain. As shown in the fourth figure, the tetraethyl silicate oxide layer is etched by using an anisotropic money engraving method to form a partition wall 14 to be attached to the gate oxide layer 4, the gate electrode 6, and the first nitride. The sidewall of the gate structure composed of the silicon layer 8. The source and drain electrodes 18 are then implanted in the substrate 2 by implanting high-dose ions, using the gate structure and the spacer 14 as implantation masks. Referring to the fifth figure, after forming the source and drain electrodes 18, the size of the removable Jianliang paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) ^ -------- ^- --------. ^ 91. (Please read the notes on the back before filling out this page) M6173 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (Gap 14 was subsequently removed. In one embodiment, the use of a hydrofluoric acid solution or a buffered oxidizing agent removes the removable partition wall 14 from the *, ..., and the secondary bubble method. The chaotic layer 12 will only be cans. , &Amp;, 廿 ', 5 蔓 shallow trench insulation layer and gate are protected from being etched and removed during the etching and removal process, and the entire S body, and destructuring will also be restored to those before the deposition of tetraethyl oxalate After that, a selective step is performed to form a boundaryless layer helmet a on the surface of the first nitrided layer 12. The boundary layer 20 is used to determine when performing: 准 准 准 窗 # 刻 ， 浅The trench edge layer area will not be etched. If the thickness of the nitride layer 1 "is sufficient, the borderless layer can be omitted. The material of the borderless layer 20 is a vapor. And its thickness is about 150 angstroms to 250 angstroms. W The electrical layer 22 is formed on the gate structure to a thickness of about 25,000 angstroms to & 〇⑽ angstroms, and the electrical layer 22 may be made of stone dioxide. Shixi glass and oxidized stone are composed of glass. Then, a photoresist (not shown) is patterned on the dielectric layer 22 to define the contact window area. The photoresist has an opening aligned with the contact window of the substrate. With the highly selective etching process of oxides and nitrides, the dielectric @ 22 is etched. The dielectric layer 22 is used as an insulating layer to isolate the substrate 2 and successively cover the layers thereon. Used for interconnection or similar purposes. Used for highly selective etching reaction gas between dielectric layer 22, silicon nitride layer 12 and / or borderless layer, including carbon monoxide, cyclo-octafluorobutane (GF8) And tetrafluoromethane (CF4), etc. By using an etchant, the etching rate of silicon dioxide is greater than that of silicon nitride. The silicon nitride layers 20, 12 and the first silicon nitride layer 8 are used as etching barriers. To form a contact window 24 in the dielectric layer 22. Therefore, the high selective etching process can improve the contact Of accuracy.
------,---_--裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 516173 五、發明說明（ 由於可移除式間隙壁14於進行自行對準接 刖即已去除’ &方法將不會使閘極間之間距變窄 / 進行溝填之步驟將μ前技術更為簡便。另外匕’ 之問題，可藉由移除間隙壁而得到改善。同時，可= 傳統氮化石夕間隙壁角落產生之應力。請參閱第六圖^ 間之最短間距(以d’表示)約等 中D，代表問極間之間距；w一與w—則分別代表氧化 層1。與氮化層12之寬度。假設D，之尺寸小於〇19微来， 且界。_與w„,tri“之寬度約分別大於等於8〇]〇〇、與 100〜20 0，則接觸窗之縱橫比（接觸窗深度與寬度之比值） 約為3·46(0·45/0·13) ’而此數值較先前技術所得的更 佳。因此，習知技術所產生之問冑，可藉由本發明之方法 得到解決。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍；凡其它未脫離本發明所揭示 之精神下所完成之等效改變或修飾，均應包含在下述之申 請專利範圍内。 ；---<----------訂--- (請先閱讀背面之注音？事項再填寫本頁) 線考. 經濟部智慧財產局員工消費合作社印製------, ---_-- install -------- order --------- line (please read the precautions on the back before filling this page) 516173 V. Invention Explanation (Because the removable spacer 14 is removed after performing self-alignment connection, the & method will not narrow the gap between the gates / the step of trench filling will make the previous technique easier. The problem of the dagger can be improved by removing the spacer. At the same time, it can be = the stress generated at the corner of the spacer of the traditional nitride stone. Please refer to the shortest distance (represented by d ') in the sixth figure ^ D, represents the distance between the interrogation electrodes; w_ and w- represent the width of the oxide layer 1. and the width of the nitride layer 12. Assuming that D, the size is less than 019 micrometers, and the boundary. _ And w ", tri" The widths of the contact windows are approximately equal to or greater than 80, 〇〇, and 100 to 200, respectively. The aspect ratio of the contact window (the ratio of the depth and width of the contact window) is approximately 3.46 (0 · 45/0 · 13). The value is better than that obtained by the prior art. Therefore, the problems caused by the conventional technology can be solved by the method of the present invention. The above are only the preferred embodiments of the present invention, and are not intended to be used to Limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the scope of patent application described below;; --- < ----- ----- Order --- (Please read the phonetic on the back? Matters before filling out this page) Online test. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs