JPS59215118A - 非同期型直並列デ−タ変換装置 - Google Patents

非同期型直並列デ−タ変換装置

Info

Publication number
JPS59215118A
JPS59215118A JP8976483A JP8976483A JPS59215118A JP S59215118 A JPS59215118 A JP S59215118A JP 8976483 A JP8976483 A JP 8976483A JP 8976483 A JP8976483 A JP 8976483A JP S59215118 A JPS59215118 A JP S59215118A
Authority
JP
Japan
Prior art keywords
data
signal
logic
output
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8976483A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0566049B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Soichi Miyata
宗一 宮田
Toshiya Okamoto
俊弥 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP8976483A priority Critical patent/JPS59215118A/ja
Publication of JPS59215118A publication Critical patent/JPS59215118A/ja
Publication of JPH0566049B2 publication Critical patent/JPH0566049B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Dc Digital Transmission (AREA)
JP8976483A 1983-05-20 1983-05-20 非同期型直並列デ−タ変換装置 Granted JPS59215118A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8976483A JPS59215118A (ja) 1983-05-20 1983-05-20 非同期型直並列デ−タ変換装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8976483A JPS59215118A (ja) 1983-05-20 1983-05-20 非同期型直並列デ−タ変換装置

Publications (2)

Publication Number Publication Date
JPS59215118A true JPS59215118A (ja) 1984-12-05
JPH0566049B2 JPH0566049B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-09-21

Family

ID=13979767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8976483A Granted JPS59215118A (ja) 1983-05-20 1983-05-20 非同期型直並列デ−タ変換装置

Country Status (1)

Country Link
JP (1) JPS59215118A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001029650A1 (en) * 1999-10-20 2001-04-26 Fujitsu Network Communications, Inc. Multiple time domain serial-to-parallel converter
US7408962B2 (en) 2000-09-14 2008-08-05 Nec Corporation Demultiplexer apparatus and communication apparatus using the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5389608A (en) * 1977-01-18 1978-08-07 Nec Corp Multilevel code transmission system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5389608A (en) * 1977-01-18 1978-08-07 Nec Corp Multilevel code transmission system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001029650A1 (en) * 1999-10-20 2001-04-26 Fujitsu Network Communications, Inc. Multiple time domain serial-to-parallel converter
US7408962B2 (en) 2000-09-14 2008-08-05 Nec Corporation Demultiplexer apparatus and communication apparatus using the same

Also Published As

Publication number Publication date
JPH0566049B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-09-21

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