JPS59208722A - 半導体集積回路装置用合せマ−ク - Google Patents

半導体集積回路装置用合せマ−ク

Info

Publication number
JPS59208722A
JPS59208722A JP58082507A JP8250783A JPS59208722A JP S59208722 A JPS59208722 A JP S59208722A JP 58082507 A JP58082507 A JP 58082507A JP 8250783 A JP8250783 A JP 8250783A JP S59208722 A JPS59208722 A JP S59208722A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
alignment mark
single crystal
alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58082507A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6347331B2 (en:Method
Inventor
Hisashi Mizuide
水出　久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP58082507A priority Critical patent/JPS59208722A/ja
Publication of JPS59208722A publication Critical patent/JPS59208722A/ja
Publication of JPS6347331B2 publication Critical patent/JPS6347331B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P95/00—

Landscapes

  • Element Separation (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
JP58082507A 1983-05-13 1983-05-13 半導体集積回路装置用合せマ−ク Granted JPS59208722A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58082507A JPS59208722A (ja) 1983-05-13 1983-05-13 半導体集積回路装置用合せマ−ク

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58082507A JPS59208722A (ja) 1983-05-13 1983-05-13 半導体集積回路装置用合せマ−ク

Publications (2)

Publication Number Publication Date
JPS59208722A true JPS59208722A (ja) 1984-11-27
JPS6347331B2 JPS6347331B2 (en:Method) 1988-09-21

Family

ID=13776417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58082507A Granted JPS59208722A (ja) 1983-05-13 1983-05-13 半導体集積回路装置用合せマ−ク

Country Status (1)

Country Link
JP (1) JPS59208722A (en:Method)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077421A (ja) * 1983-10-05 1985-05-02 Fujitsu Ltd 位置合わせ方法
JPS60160122A (ja) * 1984-01-30 1985-08-21 Rohm Co Ltd サーマルプリントヘッドの製造方法
JPH025508A (ja) * 1988-06-24 1990-01-10 Sony Corp 半導体基板

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50153862U (en:Method) * 1974-06-07 1975-12-20

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50153862U (en:Method) * 1974-06-07 1975-12-20

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077421A (ja) * 1983-10-05 1985-05-02 Fujitsu Ltd 位置合わせ方法
JPS60160122A (ja) * 1984-01-30 1985-08-21 Rohm Co Ltd サーマルプリントヘッドの製造方法
JPH025508A (ja) * 1988-06-24 1990-01-10 Sony Corp 半導体基板

Also Published As

Publication number Publication date
JPS6347331B2 (en:Method) 1988-09-21

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