JPS59206878A - グラフイツクメモリのアクセス制御方式 - Google Patents

グラフイツクメモリのアクセス制御方式

Info

Publication number
JPS59206878A
JPS59206878A JP58081341A JP8134183A JPS59206878A JP S59206878 A JPS59206878 A JP S59206878A JP 58081341 A JP58081341 A JP 58081341A JP 8134183 A JP8134183 A JP 8134183A JP S59206878 A JPS59206878 A JP S59206878A
Authority
JP
Japan
Prior art keywords
graphic
data
memory
bit
plane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58081341A
Other languages
English (en)
Japanese (ja)
Other versions
JPS649636B2 (enrdf_load_stackoverflow
Inventor
伸二 小川
洋史 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP58081341A priority Critical patent/JPS59206878A/ja
Publication of JPS59206878A publication Critical patent/JPS59206878A/ja
Publication of JPS649636B2 publication Critical patent/JPS649636B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)
JP58081341A 1983-05-10 1983-05-10 グラフイツクメモリのアクセス制御方式 Granted JPS59206878A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58081341A JPS59206878A (ja) 1983-05-10 1983-05-10 グラフイツクメモリのアクセス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58081341A JPS59206878A (ja) 1983-05-10 1983-05-10 グラフイツクメモリのアクセス制御方式

Publications (2)

Publication Number Publication Date
JPS59206878A true JPS59206878A (ja) 1984-11-22
JPS649636B2 JPS649636B2 (enrdf_load_stackoverflow) 1989-02-17

Family

ID=13743665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58081341A Granted JPS59206878A (ja) 1983-05-10 1983-05-10 グラフイツクメモリのアクセス制御方式

Country Status (1)

Country Link
JP (1) JPS59206878A (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62267793A (ja) * 1986-05-15 1987-11-20 オムロン株式会社 ビツトマツプデイスプレイ装置
JPS6352247A (ja) * 1986-08-21 1988-03-05 Ascii Corp メモリ装置
JPS63121946A (ja) * 1986-11-11 1988-05-26 Fuji Electric Co Ltd メモリアクセス制御回路
JPS6446170A (en) * 1987-08-14 1989-02-20 Sharp Kk Drawing device
JPH03123391A (ja) * 1989-09-29 1991-05-27 Internatl Business Mach Corp <Ibm> 高解像度ビデオ表示システム

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62267793A (ja) * 1986-05-15 1987-11-20 オムロン株式会社 ビツトマツプデイスプレイ装置
JPS6352247A (ja) * 1986-08-21 1988-03-05 Ascii Corp メモリ装置
JPS63121946A (ja) * 1986-11-11 1988-05-26 Fuji Electric Co Ltd メモリアクセス制御回路
JPS6446170A (en) * 1987-08-14 1989-02-20 Sharp Kk Drawing device
JPH03123391A (ja) * 1989-09-29 1991-05-27 Internatl Business Mach Corp <Ibm> 高解像度ビデオ表示システム

Also Published As

Publication number Publication date
JPS649636B2 (enrdf_load_stackoverflow) 1989-02-17

Similar Documents

Publication Publication Date Title
US5282177A (en) Multiple register block write method and circuit for video DRAMs
US4779232A (en) Partial write control apparatus
US6065132A (en) Information processing system having a CPU for controlling access timings of separate memory and I/O buses
JP2593060B2 (ja) ダイナミックランダムアクセスメモリ、ダイナミックランダムアクセスメモリのアクセス方法及びシステム
JP2735173B2 (ja) ワンチップメモリデバイス
JPS62237542A (ja) メモリ
JPS629456A (ja) デ−タ転送装置
JPS59206878A (ja) グラフイツクメモリのアクセス制御方式
US4594690A (en) Digital storage apparatus including sections exhibiting different access speeds
US5265234A (en) Integrated memory circuit and function unit with selective storage of logic functions
JPS6334795A (ja) 半導体記憶装置
JPH09508745A (ja) 連続ページランダムアクセスメモリと、連続ページランダムアクセスメモリを使用するシステムおよび方法
JPS61264378A (ja) 記憶回路
JPS5960488A (ja) カラ−グラフイツクメモリのデ−タ書き込み装置
US5113487A (en) Memory circuit with logic functions
JP2886855B2 (ja) 画像表示装置
JP3036441B2 (ja) 1チップメモリデバイス
JPH01188962A (ja) 電子機器
KR0154717B1 (ko) 상태 천이 머신을 가지는 시스템의 메모리 관리 구조 및 그 처리방법
JPH0525331B2 (enrdf_load_stackoverflow)
JP2547256B2 (ja) Dma装置
KR960006881B1 (ko) 좌표지정을 이용한 비디오 램 인터페이스 제어회로
JP2591515B2 (ja) 1チップメモリデバイス
JPH04153984A (ja) ダイナミックメモリの制御方法
JPH06301772A (ja) 画像処理用lsi