JPS59190712A - ジヨセフソン論理回路 - Google Patents

ジヨセフソン論理回路

Info

Publication number
JPS59190712A
JPS59190712A JP6364683A JP6364683A JPS59190712A JP S59190712 A JPS59190712 A JP S59190712A JP 6364683 A JP6364683 A JP 6364683A JP 6364683 A JP6364683 A JP 6364683A JP S59190712 A JPS59190712 A JP S59190712A
Authority
JP
Japan
Prior art keywords
flip
signal
circuit
transfer circuit
current transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6364683A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0220015B2 (enrdf_load_stackoverflow
Inventor
Toshihiro Nakamura
中村 智弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP6364683A priority Critical patent/JPS59190712A/ja
Publication of JPS59190712A publication Critical patent/JPS59190712A/ja
Publication of JPH0220015B2 publication Critical patent/JPH0220015B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/38Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of superconductive devices

Landscapes

  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
JP6364683A 1983-04-13 1983-04-13 ジヨセフソン論理回路 Granted JPS59190712A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6364683A JPS59190712A (ja) 1983-04-13 1983-04-13 ジヨセフソン論理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6364683A JPS59190712A (ja) 1983-04-13 1983-04-13 ジヨセフソン論理回路

Publications (2)

Publication Number Publication Date
JPS59190712A true JPS59190712A (ja) 1984-10-29
JPH0220015B2 JPH0220015B2 (enrdf_load_stackoverflow) 1990-05-07

Family

ID=13235318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6364683A Granted JPS59190712A (ja) 1983-04-13 1983-04-13 ジヨセフソン論理回路

Country Status (1)

Country Link
JP (1) JPS59190712A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148463A (en) * 1978-05-15 1979-11-20 Nec Corp Jk flip-flop

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148463A (en) * 1978-05-15 1979-11-20 Nec Corp Jk flip-flop

Also Published As

Publication number Publication date
JPH0220015B2 (enrdf_load_stackoverflow) 1990-05-07

Similar Documents

Publication Publication Date Title
Geiger et al. VLSI design techniques for analog and digital circuits
JPH0219015A (ja) 多機能フリップフロップ型回路
US3976949A (en) Edge sensitive set-reset flip flop
JPS6096021A (ja) トリガ回路
JPH06232707A (ja) しきい値制御された集積回路用入力回路
Hassen et al. Approximate in-memory computing on reram crossbars
JPS59190712A (ja) ジヨセフソン論理回路
US4839633A (en) Asymmetric voltage monitor for series supplies
Wang et al. A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process
JPH0469890A (ja) 基準電圧発生回路
Hatano et al. A 4-bit Josephson data processor chip
Majumder et al. Variation aware design of 50-Gbit/s, 5.027-fJ/bit serializer using latency combined mux-dual latch for inter-chip communication
Kawahito et al. Design of VLSI‐oriented radix‐4 signed‐digit arithmetic circuits using multiple‐valued logic
JPH0377537B2 (enrdf_load_stackoverflow)
JP2712411B2 (ja) テスト回路
JPS5877328A (ja) Cmos集積回路装置
CN116665744A (zh) 熔丝分辨电路及模数转换器
JPH0461417A (ja) 半導体集積回路装置
JPH0220016B2 (enrdf_load_stackoverflow)
JPS61240172A (ja) 集積回路の試験方法
JPS583274A (ja) 半導体装置
JPS6153814A (ja) ラツチ回路
JPS6074725A (ja) 演算回路
JPH0492292A (ja) 半導体集積記憶回路装置
Hanyu et al. A Josephson latch-decoder