JPS5917979B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5917979B2
JPS5917979B2 JP53163035A JP16303578A JPS5917979B2 JP S5917979 B2 JPS5917979 B2 JP S5917979B2 JP 53163035 A JP53163035 A JP 53163035A JP 16303578 A JP16303578 A JP 16303578A JP S5917979 B2 JPS5917979 B2 JP S5917979B2
Authority
JP
Japan
Prior art keywords
flip
bonding area
electrode
flip chip
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53163035A
Other languages
Japanese (ja)
Other versions
JPS5591134A (en
Inventor
康郎 三井
学 渡瀬
通博 小引
睦之 大坪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP53163035A priority Critical patent/JPS5917979B2/en
Publication of JPS5591134A publication Critical patent/JPS5591134A/en
Publication of JPS5917979B2 publication Critical patent/JPS5917979B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Description

【発明の詳細な説明】 本発明は半導体装置、特にフリップチップ構成の3端子
半導体チップを有する半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having a three-terminal semiconductor chip of flip-chip configuration.

第1図は従来のフリップチップ構成GaAsFETの一
例を示す要部斜視図である。
FIG. 1 is a perspective view of essential parts of an example of a conventional flip-chip GaAsFET.

同図において。1は厚メッキを施して形成されたソース
突起電極。
In the same figure. 1 is a source protrusion electrode formed by thick plating.

2および3はそれぞれドレイン電極パッド4およびゲー
ト電極パッド5上に形成されたドレイン突起電極および
ゲート突起電極である。
2 and 3 are a drain protrusion electrode and a gate protrusion electrode formed on the drain electrode pad 4 and the gate electrode pad 5, respectively.

6および□はそれぞれドレイン電極およびゲート電極で
あシ。
6 and □ are the drain electrode and gate electrode, respectively.

このドレイン電極6、ゲート電極7およびソース突起電
極1は互いに所定距離離して周期的に連続O して形成
されている。第2図は第1図に示した従来のフリップチ
ップ構成GaAsFETをフリップチップ装着体に装着
したときの第1図におけるA−A’面の断面図を示した
ものである。
The drain electrode 6, the gate electrode 7, and the source protruding electrode 1 are formed periodically and continuously at a predetermined distance from each other. FIG. 2 is a sectional view taken along the line AA' in FIG. 1 when the conventional flip-chip GaAsFET shown in FIG. 1 is mounted on a flip-chip mounting body.

同図において、8はソース接地5 のGaAsFETの
フーリツプチツプ、9はGaAsFETのフリップチッ
プ8が装着されるフリップチップ装着体、10はフリッ
プチップ装着体9の接地用金属基板、11は接地用金属
基板10の表面に設けられた凸部であV、この凸部11
はソー’0 ス突起電極1がボンディング接続されるソ
ースボンディングエリアである。12aおよび12bは
それぞれの表面にドレイン突起電極2およびゲート突起
電極3に対応してドレインボンディングエリア13およ
びゲートボンディングエリア14が■5 形成された第
1および第2のセラミック基板であろ。
In the figure, 8 is a GaAsFET flip chip with a common source 5, 9 is a flip chip mounting body to which the GaAsFET flip chip 8 is mounted, 10 is a grounding metal substrate of the flip chip mounting body 9, and 11 is a grounding metal substrate 10. V is a convex portion provided on the surface of V, and this convex portion 11
is a source bonding area to which the source protruding electrode 1 is bonded. Reference numerals 12a and 12b are first and second ceramic substrates on which drain bonding areas 13 and gate bonding areas 14 are formed in correspondence with the drain protrusion electrodes 2 and gate protrusion electrodes 3, respectively.

そして、この第1および第2のセラミック基板12a、
12bは、それぞれ接地用金属基板10の表面にソース
ボンディングエリア11をはさんで取り付けられている
。30このような構成において、フリップチップ8をフ
リップチップ装着体10にボンディングする場合、凸部
11、ドレインボンディングエリア13およびゲートボ
ンディングエリア14の各表面が同一平面上に形成され
ていなければ、ソース突起35電極1、ドレイン突起電
極2およびゲート突起電極3と、これに対応する凸部I
liドレインボンディングエリア13およびゲートボン
デイングエリア14とが全体にわたつて確実に接続され
ないことになる。
The first and second ceramic substrates 12a,
12b are each attached to the surface of the grounding metal substrate 10 with the source bonding area 11 in between. 30 In such a configuration, when bonding the flip chip 8 to the flip chip mounting body 10, if the surfaces of the convex portion 11, drain bonding area 13, and gate bonding area 14 are not formed on the same plane, the source protrusion 35 electrode 1, drain protrusion electrode 2, gate protrusion electrode 3, and corresponding protrusion I
The li drain bonding area 13 and the gate bonding area 14 will not be reliably connected throughout.

例えば.GaAsFETのフリツプチツプ8上の各突起
電極1,2,3の厚さが数十ミクロン程度、幅が数百ミ
クロン以下,また各突起電極1,2,3間の間隔が数百
ミクロン以下の場合6凸部11.ドレインボンデイング
エリア136ゲートボンデイングエリア14の各表面の
段差が数十ミクロンオーダ以上では、突起電極とボンデ
イングエリア間に隙間が生じた勺、突起電極が変形を受
けたり6あるいは全く接触しない場合もある。しかしな
がら、フリツプチツプ装着体の表面段差を数十ミクロン
以下に抑えることは実用上困難なため,このような構成
のフリツプチツプでは、組立時の歩留の低下}よびソー
ス、ドレイン、ゲート各電極部の接触抵抗の増大をもた
らし6素子特性の劣化を招く原因となつていた。したが
つて,本発明は上述の欠点に鑑みてなされたものであり
6フリツプチツプ上の各突起電極とフリツプチツプ装着
体との電気的接続を確実に行ない6電極部接触抵抗を低
減した高出力用フリツプチツプ構成半導体装置を提供す
ることを目的としている。
for example. When the thickness of each of the protruding electrodes 1, 2, and 3 on the flip chip 8 of the GaAsFET is approximately several tens of microns, the width is several hundred microns or less, and the distance between each of the protruding electrodes 1, 2, and 3 is several hundred microns or less6. Convex portion 11. If the level difference on each surface of the drain bonding area 136 and the gate bonding area 14 is on the order of several tens of microns or more, the protruding electrodes may be deformed or may not contact each other at all due to a gap between the protruding electrode and the bonding area. However, it is practically difficult to suppress the surface level difference of a flip chip mounting body to less than a few tens of microns, so flip chips with such a configuration lead to a decrease in assembly yield and to problems with contact between the source, drain, and gate electrodes. This caused an increase in resistance and a deterioration of the six-element characteristics. Therefore, the present invention has been made in view of the above-mentioned drawbacks, and provides a high-output flip chip that ensures electrical connection between each protruding electrode on the 6-flip chip and the flip-chip mounting body and reduces the contact resistance of the 6-electrode portion. The object of the present invention is to provide a structural semiconductor device.

以下図面を用いて本発明の実施例を詳細に説明する。第
3図は本発明に係わるフリツプチツプ構成用GaAsF
ETの一例を示す要部斜視図、第4図は上記GaAsF
ETを本発明に係るフリツプチツプ装着体に装着した状
態を示す要部断面図であり、第1図、第2図と同記号は
同一要素となるのでその説明は省略する。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 3 shows GaAsF for flip-chip construction according to the present invention.
FIG. 4 is a perspective view of the main part showing an example of ET.
FIG. 2 is a sectional view of a main part showing a state in which an ET is mounted on a flip-chip mounting body according to the present invention, and since the same symbols as in FIGS. 1 and 2 represent the same elements, a description thereof will be omitted.

まず.第3図において、15は各ドレイン突起電極2同
志を接続して波状に連結された金リボンなどの導体から
なるドレイン接続緩衝体,16は上記同様各ゲート突起
電極3を接続して波状に連結された金リボンなどの導体
からなるゲート接続緩衝体である。また、第4図におい
て、ソースボンデイングエリアを形成する凸部11の表
面は.ドレインボンデイングエリア13およびゲートボ
ンデイングエリア14の各表面よりも予めやや高く設定
されている。このように第3図に示すフリツプチツプを
第4図に示すフリツプチツプ装着体に装着する構成では
、ソースボンデイングエリア11の表面がドレインボン
デイングエリア13}よびゲートボンデイングエリア1
4の各表面よ如も高くなつてお抵かつ装着されるべきフ
リツプチツプ8上のドレイン接続緩衝体15訃よびゲー
ト接続緩衝体16がスプリングの役割をするためにフリ
ツプチツプ装着体の製作精度が悪い場合でも6フリツプ
チツプ上の各電極と7リツプチツプ装着体の各ボンデイ
ングエリア同志を互いに歩留り良く確実に接続すること
が可能となる。
first. In FIG. 3, reference numeral 15 denotes a drain connection buffer made of a conductor such as a gold ribbon, which connects each of the drain protruding electrodes 2 together in a wavy manner, and 16 denotes a drain connection buffer made of a conductor such as a gold ribbon, which connects each of the gate protruding electrodes 3 and connects them in a wavy manner. gate connection buffer made of a conductor such as gold ribbon. Further, in FIG. 4, the surface of the convex portion 11 forming the source bonding area is . It is set in advance to be slightly higher than the respective surfaces of the drain bonding area 13 and the gate bonding area 14. In this way, in the structure in which the flip chip shown in FIG. 3 is mounted on the flip chip mounting body shown in FIG.
4, and the drain connection buffer 15 on the flip chip 8 to be mounted and the gate connection buffer 16 play the role of springs, so the manufacturing accuracy of the flip chip mounting body is poor. However, it becomes possible to reliably connect each electrode on the 6-flip chip to each bonding area of the 7-flip chip mounting body with a high yield.

この結果、接触部での寄生ソース抵抗RS6寄生ドレイ
ン抵抗Rdおよび寄生ゲート抵抗Rgを低減させること
ができ、素子の高周波特性が改善される。第5図は、全
ゲート幅1600μmのフリツプチツプ構成素子の単方
向利得の代表的周波数性を示した特性曲線図である。
As a result, the parasitic source resistance RS6, the parasitic drain resistance Rd, and the parasitic gate resistance Rg at the contact portion can be reduced, and the high frequency characteristics of the device are improved. FIG. 5 is a characteristic curve diagram showing a typical frequency characteristic of the unidirectional gain of a flip-chip component having a total gate width of 1600 μm.

同図において.曲線は従来のフリツプチツプ訃よびフリ
ツプチツプ装着体を用いた素子の特性曲線であり,曲線
は本発明に係わるフリツプチツプおよびフリツプチツプ
装着体を用いた素子の特性曲線である。同図に示すよう
に従来のフリツプチツプおよびフリツプチツプ装着体を
用いた素子では.最大発振周波数が約20GHzである
のに対し、本発明に係るフリツプチツプおよびその装着
体を用いた素子では最大発振周波数が約30GHzと約
10GHz向上しており、マイクロ波特性の改善に極め
て有効である。なお、上記実施例においては、ソース接
地の場合について説明したが,本発明はこれに限定され
るものではなく、ドレイン接地もしくはゲート接地の場
合にも適用することができる。
In the same figure. The curve is a characteristic curve of a device using a conventional flip chip and a flip chip mounting body, and the curve is a characteristic curve of a device using a flip chip and a flip chip mounting body according to the present invention. As shown in the figure, the conventional flip chip and the device using the flip chip mounting body. While the maximum oscillation frequency is approximately 20 GHz, the maximum oscillation frequency of the device using the flip chip and its attached body according to the present invention is approximately 30 GHz, which is an improvement of approximately 10 GHz, and is extremely effective in improving microwave characteristics. be. In the above embodiments, the case where the source is grounded is explained, but the present invention is not limited to this, and can be applied to the case where the drain is grounded or the gate is grounded.

また,上記実施例にふ・いては.GaAsFETのフリ
ツプチツプについて説明したが,本発明はこれに限定さ
れるものではなく.この他のマイクロ波電力用FET,
MOSトランジスタ,薄膜トランジスタなどのフリツプ
チツプ構成の半導体チツプおよびそれを装着するフリツ
プチツプ装着体にも適用することができる。
Also, based on the above example. Although the GaAsFET flip chip has been described, the present invention is not limited thereto. Other microwave power FETs,
It can also be applied to flip-chip semiconductor chips such as MOS transistors and thin film transistors, and flip-chip mounting bodies on which they are mounted.

また6上記実施例においては、緩衝接続部として波形の
金リボンを用いた場合について説明したが、本発明はこ
れに限定されるものではなく,スプリング効果を有する
他の形状あるいは材料.例えば金ワイヤカどを用いても
同様の効果が得られることは勿論である。
Further, in the above embodiment, a case was explained in which a corrugated gold ribbon was used as the buffer connection part, but the present invention is not limited to this, and other shapes or materials having a spring effect may be used. Of course, the same effect can be obtained by using, for example, a gold wire.

以上説明したように本発明によれば、接地すべき第1の
突起電極の両側に周期的に配設した接地しない第2およ
び第3の突起電極を導電性緩衝体により波状に接続し、
かつ接地すべき第1の突起電極が接続されるべきフリツ
プチツプ装着体上のボンデイングエリアを他の第1およ
び第2の突起電極が接続されるべきボンデイングエリア
よりも高く設定してあるので、上記フリツプチツプを上
記フリツプチツプ装着体に装着するよきにフリツプチツ
プ装着体が不可避的な工作精度上の誤差を有する場合に
も各突起電極を確実に歩留り良く各ボンデイングエリア
に接続することができる。
As explained above, according to the present invention, the second and third protruding electrodes that are not grounded are periodically arranged on both sides of the first protruding electrode that is to be grounded, and are connected in a wavy manner by a conductive buffer,
In addition, since the bonding area on the flip-chip mounting body to which the first protruding electrode to be grounded is to be connected is set higher than the bonding area to which the other first and second protruding electrodes are to be connected, the above-mentioned flip-chip Even if the flip-chip mounting body has an unavoidable error in machining accuracy when the flip-chip mounting body is mounted on the flip-chip mounting body, each protruding electrode can be reliably connected to each bonding area with a high yield.

この結果、マイクロ波特性の飛躍的な向上を図ることが
できるなどの極めて優れた効果が得られる。
As a result, extremely excellent effects such as a dramatic improvement in microwave characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のフリツプチツプ構成用GaAsFETの
一例を示す要部斜視図.第2図は第1図のフリツプチツ
プを従来のフリツプチツプ装着体に装着したときの要部
断面図、第3図は本発明のフリツプチツプ構成用GaA
sFETの一例を示す要部斜視図6第4図は第3図のフ
リツプチツプを本発明のフリツプチツプ装着体に装着し
たときの一例を示す要部断面図、第5図は本発明のフリ
ツプチツプおよびフリツプチツプ装着体を用いた素子の
単方向利得の周波数特囲を従来のフリツプチツプ構成素
子と比較した特性曲線図である。 1・・・・・・ソース突起電極62・・・・・・ドレイ
ン突起電極、3・・・・・・ゲート突起電極. 8・・
・・・・フリツプチツプ. 9・・・・・・フリツプチ
ツプ装着体、11・・・・・・ソースボンデイングエリ
ア, 13・・・・・・ドレインボンデイングエリア.
14・・・・・・ゲートボンデイングエリア、15・
・・・・・ドレイン接続緩衝体. 16・・・・・・ゲ
ート接続緩衝体。
Figure 1 is a perspective view of the main parts of an example of a conventional flip-chip GaAsFET. FIG. 2 is a cross-sectional view of the main part of the flip chip shown in FIG. 1 mounted on a conventional flip chip mounting body, and FIG.
FIG. 4 is a sectional view of essential parts showing an example of the flip chip shown in FIG. 3 mounted on the flip chip mounting body of the present invention, and FIG. 5 is a perspective view of the main parts showing an example of an sFET FIG. 3 is a characteristic curve diagram comparing the frequency range of the unidirectional gain of the device using the semiconductor device with that of the conventional flip-chip component. 1... Source protrusion electrode 62... Drain protrusion electrode, 3... Gate protrusion electrode. 8...
...flip chip. 9...Flip chip attachment body, 11...Source bonding area, 13...Drain bonding area.
14...Gate bonding area, 15.
...Drain connection buffer. 16...Gate connection buffer.

Claims (1)

【特許請求の範囲】[Claims] 1 接地すべき第1の突起電極の両側に周期的に配設し
た接地しない第2の突起電極同志および第3の突起電極
同志を導電性緩衝体により接続したフリップチップ構成
の半導体チップを、上記接地すべき第1の突起電極を装
着するボンディングエリアの表面を上記第2および第3
の突起電極を装着するボンディングエリアの表面よりも
高くしたフリップチップ装着体に装着したことを特徴と
する半導体装置。
1. A semiconductor chip having a flip-chip configuration in which second protruding electrodes that are not grounded and third protruding electrodes that are not grounded and are periodically arranged on both sides of a first protruding electrode that is to be grounded are connected to each other by a conductive buffer. The surface of the bonding area where the first protruding electrode to be grounded is attached is connected to the second and third electrodes.
What is claimed is: 1. A semiconductor device mounted on a flip-chip mounting body that is higher than the surface of a bonding area to which a protruding electrode is mounted.
JP53163035A 1978-12-28 1978-12-28 semiconductor equipment Expired JPS5917979B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53163035A JPS5917979B2 (en) 1978-12-28 1978-12-28 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53163035A JPS5917979B2 (en) 1978-12-28 1978-12-28 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5591134A JPS5591134A (en) 1980-07-10
JPS5917979B2 true JPS5917979B2 (en) 1984-04-24

Family

ID=15765938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53163035A Expired JPS5917979B2 (en) 1978-12-28 1978-12-28 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5917979B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245475Y2 (en) * 1980-12-10 1987-12-04
US4843440A (en) * 1981-12-04 1989-06-27 United States Of America As Represented By The Administrator Of The National Aeronautics & Space Administration Microwave field effect transistor
CA1200017A (en) * 1981-12-04 1986-01-28 Ho C. Huang Microwave field effect transistor
JPS62144346A (en) * 1985-12-19 1987-06-27 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit element

Also Published As

Publication number Publication date
JPS5591134A (en) 1980-07-10

Similar Documents

Publication Publication Date Title
EP0018091B1 (en) A semiconductor device having a plurality of semiconductor chip portions
JPS6135714B2 (en)
US7067743B2 (en) Transmission line and device including the same
JPS5917979B2 (en) semiconductor equipment
US3471752A (en) Semiconductor device with an insulating body interposed between a semiconductor element and a part of a casing
US7042053B2 (en) Semiconductor device with polymer insulation of some electrodes
JPS6241433B2 (en)
JPS5892277A (en) Manufacture of field effect transistor
KR930020746A (en) Compound Semiconductor Integrated Circuits and Manufacturing Method Thereof
KR19990071662A (en) Power Microwave Hybrid Integrated Circuits
JPH06101532B2 (en) Semiconductor integrated circuit device
JPS61172376A (en) Semiconductor device
JPH0697352A (en) Resin sealed semiconductor device
US20230005800A1 (en) Semiconductor device and package
JP2970622B2 (en) Semiconductor device and manufacturing method thereof
JPS586152A (en) Manufacture of transistor package
JP2773685B2 (en) Semiconductor device
JPS63140556A (en) Semiconductor device
JPH05343578A (en) Semiconductor device and manufacture thereof
JP3302811B2 (en) Microwave semiconductor device
JPS5844731A (en) Semiconductor device
JPS5840339B2 (en) high frequency transistor
JPS5844732A (en) Semiconductor device
JP2711801B2 (en) Semiconductor device and manufacturing method thereof
JPS6217394B2 (en)