JPS5844732A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5844732A JPS5844732A JP14359881A JP14359881A JPS5844732A JP S5844732 A JPS5844732 A JP S5844732A JP 14359881 A JP14359881 A JP 14359881A JP 14359881 A JP14359881 A JP 14359881A JP S5844732 A JPS5844732 A JP S5844732A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- metal base
- semiconductor substrate
- notch
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置とくにフリップチップ形マイクロ
波半導体装置に関するものである。詳しく言えば、フリ
ップチップ形のマイクロ波半導体装置の性能向上が実現
可能な構造を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a flip-chip microwave semiconductor device. Specifically, the present invention provides a structure that can improve the performance of a flip-chip type microwave semiconductor device.
ここでは、マイクロ波半導体素子としてショットキバリ
ア形電界効果トランジスタ(息下5BFETと呼ぶ)を
例にとって説明する。Here, a Schottky barrier field effect transistor (referred to as 5BFET) will be explained as an example of a microwave semiconductor element.
第1図は従来のフリップチップ形5BFETの一例を示
す斜視図である。フリップチップ形5BFET−は、第
1図に示すように、半導体基体(1)の−主面上にソー
ス電極(2)、ゲート電1ii (1)およびドレイン
電極(4)を配設し、フリップチップボンディングのた
め、上記ソース電極(2)、ゲート電極(3)およびド
レイン電極(4)上にそれぞれソース突起電極(ハ)、
ゲート突起電極01)、ドレイン突起電極(2)を備え
た構造を有している。第2図はこのような5BFET−
を金属ベース(6)上にフリップテップボンディングさ
れた状態を示したもので、第1図に示した5BFETを
台座にボンディングしたものを第1図の1−1線で切断
した状態を示す断面図である。第2図に於いて、’(6
)は金属ベース、(6)はアルミナセラミック等の絶縁
物、(7)はセラミック上に設けられた金属線路、(8
)はセラミック(6)と金属ベース(5)の接着のため
設けられたセラミックのメタライズ膜である。FIG. 1 is a perspective view showing an example of a conventional flip-chip type 5BFET. As shown in FIG. 1, a flip-chip type 5BFET has a source electrode (2), a gate electrode 1ii (1), and a drain electrode (4) arranged on the main surface of a semiconductor substrate (1), and is a flip-chip type 5BFET. For chip bonding, source protruding electrodes (c) are provided on the source electrode (2), gate electrode (3) and drain electrode (4), respectively.
It has a structure including a gate protrusion electrode 01) and a drain protrusion electrode (2). Figure 2 shows such a 5BFET-
This is a cross-sectional view taken along line 1-1 in Figure 1 of the 5BFET shown in Figure 1 bonded to the pedestal by flip-step bonding on the metal base (6). It is. In Figure 2, '(6
) is a metal base, (6) is an insulator such as alumina ceramic, (7) is a metal line provided on ceramic, (8
) is a ceramic metallized film provided for bonding the ceramic (6) and the metal base (5).
第8図は第2図の状態を別角度から見た場合、すなわち
、第1図1−1線で切断した状態を示す断面図である。FIG. 8 is a sectional view showing the state shown in FIG. 2 viewed from a different angle, that is, the state taken along the line 1--1 in FIG.
−
仁のような従来のフリップチップ形5BFETでは、第
8図かられかるように、ソース電極(2)が台座として
の作用を行なう金属ベース(5)に接地され、そして、
金属ベース(6)の表面−と狭い空隙でドレイン電極(
4)と対向する構造となっている。そのため、ドレイン
電極(りと接地の金属ベース(5)の間には寄生容量が
生じる結果となり、よく知られている様に、この寄!生
容量の増大によってGIA8FETの性能を低下させる
欠点を有している。- In a conventional flip-chip type 5BFET such as Jin, the source electrode (2) is grounded to a metal base (5) which acts as a pedestal, as can be seen in Figure 8;
The surface of the metal base (6) and the drain electrode (
4). As a result, a parasitic capacitance is generated between the drain electrode and the grounded metal base (5), and as is well known, this increase in parasitic capacitance has the disadvantage of degrading the performance of the GIA8FET. are doing.
この発明は上記の点に鑑みてなされたものであり、以下
図面の実施例について説明する。This invention has been made in view of the above points, and embodiments shown in the drawings will be described below.
第4図は仁の発明の一実施例であるフリップチップ形5
BFETを示す断面図である。図中(5)は金属ベース
で、この金属ベース(5)はその表面が半、 導体基
体−に形成されたゲート電極(3)およびドレイン電極
(4)に対向する部分に切り欠き部−が形成されている
。Figure 4 shows a flip chip type 5 which is an embodiment of Jin's invention.
It is a sectional view showing a BFET. In the figure, (5) is a metal base, and this metal base (5) has a half surface and a notch in the part facing the gate electrode (3) and drain electrode (4) formed on the conductive base. It is formed.
そのために接地金属ベース(5)の表面と対向する大き
くなるため、従来装置に比して寄生容量が減少ける。従
って、従来装置に比して性能、とくに高周波特性の改善
を計ることができる。Therefore, since the surface facing the ground metal base (5) is large, the parasitic capacitance is reduced compared to the conventional device. Therefore, performance, especially high frequency characteristics, can be improved compared to conventional devices.
さらに、ソース突起電極に)を金属ベース(5)に半田
等を用いて接着する場合、余剰半田が、流れてもこの切
り欠き部−に吸収されるため、隣接する他の電極、すな
わちゲート電極(3)との短絡を防止することができる
ため、きわめて作業性が改善される。Furthermore, when bonding the source projecting electrode (to the source projecting electrode) to the metal base (5) using solder, etc., excess solder, even if it flows, is absorbed into this notch, so that it may not be applied to other adjacent electrodes, i.e., the gate electrode. (3) Since short circuits with the above can be prevented, work efficiency is greatly improved.
以上の説明では、ソース電極(2)を接地とし、ドレイ
ン電極(4)およびゲート電極(3)に対向する部分の
金属ベース(5)の表面に切り欠き部−を設けているが
、本発明はこれに限定されるものではなく、5BFET
パターンの配置によってはソース電極(2)に対応する
金属ベースの表面に切り欠き部を設ける場合もある。In the above description, the source electrode (2) is grounded and a notch is provided on the surface of the metal base (5) in a portion facing the drain electrode (4) and gate electrode (3). is not limited to this, but 5BFET
Depending on the arrangement of the pattern, a notch may be provided on the surface of the metal base corresponding to the source electrode (2).
以上説明したように、この発明によれば、フリップチッ
プ形5BFETの性能向上が可能となり実用上大きな利
点を有する。As explained above, according to the present invention, it is possible to improve the performance of a flip-chip type 5BFET, and it has a great practical advantage.
第1図は従来のフリップチップ形5BFETの電極配置
を示す斜視図、#I2図はフリップチップボンディング
した状態を11図1−1線で切断した断面図1.第8図
は同様に11線で切断した断面図、第4図は本発明装置
の一実施例を示す断面図である。
図中、(1)は半導体基体、(2)はソース電極、(3
)はゲート電極、(4)はドレイン電極、縛はソース突
起電極、(2)はゲート、突起電極、師はドレイン突起
電極、−は本発明による切り欠き部を表す。
また、(6)は台座の金属ベース、(6)はセラミック
部、(7)は金属線路、(8)はメタライズ膜を表す。
なお、図中同一符号はそれぞれ同一または相当部分を示
す。
代理人 葛野信−
第1図
第2図Fig. 1 is a perspective view showing the electrode arrangement of a conventional flip-chip type 5BFET, and Fig. #I2 is a cross-sectional view taken along the line 1-1 in Fig. FIG. 8 is a sectional view similarly taken along line 11, and FIG. 4 is a sectional view showing an embodiment of the apparatus of the present invention. In the figure, (1) is a semiconductor substrate, (2) is a source electrode, and (3) is a semiconductor substrate.
) represents the gate electrode, (4) represents the drain electrode, (2) represents the gate electrode, the source represents the protruding electrode, (2) represents the gate electrode, the source represents the drain protruding electrode, and - represents the notch according to the present invention. Further, (6) represents the metal base of the pedestal, (6) represents the ceramic portion, (7) represents the metal line, and (8) represents the metallized film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 1 Figure 2
Claims (1)
極、上記第1電極に設けられた第1突起電極、上記半導
体基体の一主面の第二表面に形成された第2電極、上記
半導体基体の一主面が対向するように上記第1突起電極
を介して第1電極が接続される金属ベースを備え、上記
第2電極が対向する部分の金属ベースの表面ζζ切り欠
き部を設けたことを特徴とする半導体装置。(a first electrode formed on the first surface of one main surface of the semiconductor substrate, a first protruding electrode provided on the first electrode, a second electrode formed on the second surface of one main surface of the semiconductor substrate) an electrode, a metal base to which a first electrode is connected via the first protruding electrode so that one principal surface of the semiconductor substrate faces each other, and a ζζ notch on the surface of the metal base in a portion facing the second electrode; A semiconductor device characterized in that a semiconductor device is provided with a section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14359881A JPS5844732A (en) | 1981-09-10 | 1981-09-10 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14359881A JPS5844732A (en) | 1981-09-10 | 1981-09-10 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5844732A true JPS5844732A (en) | 1983-03-15 |
Family
ID=15342439
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14359881A Pending JPS5844732A (en) | 1981-09-10 | 1981-09-10 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5844732A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6166436A (en) * | 1997-04-16 | 2000-12-26 | Matsushita Electric Industrial Co., Ltd. | High frequency semiconductor device |
US6856075B1 (en) * | 2001-06-22 | 2005-02-15 | Hutchinson Technology Incorporated | Enhancements for adhesive attachment of piezoelectric motor elements to a disk drive suspension |
-
1981
- 1981-09-10 JP JP14359881A patent/JPS5844732A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6166436A (en) * | 1997-04-16 | 2000-12-26 | Matsushita Electric Industrial Co., Ltd. | High frequency semiconductor device |
US6856075B1 (en) * | 2001-06-22 | 2005-02-15 | Hutchinson Technology Incorporated | Enhancements for adhesive attachment of piezoelectric motor elements to a disk drive suspension |
US7211935B1 (en) | 2001-06-22 | 2007-05-01 | Hutchinson Technology Incorporated | Enhancements for adhesive attachment of piezoelectric motor elements to a disk drive suspension |
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