JPS59123250A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59123250A
JPS59123250A JP57229705A JP22970582A JPS59123250A JP S59123250 A JPS59123250 A JP S59123250A JP 57229705 A JP57229705 A JP 57229705A JP 22970582 A JP22970582 A JP 22970582A JP S59123250 A JPS59123250 A JP S59123250A
Authority
JP
Japan
Prior art keywords
substrate
recess
insulator
insulator substrate
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57229705A
Other languages
Japanese (ja)
Inventor
Hiromoto Yamawaki
山脇　汪元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57229705A priority Critical patent/JPS59123250A/en
Publication of JPS59123250A publication Critical patent/JPS59123250A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a semiconductor device which has good thermal dissipation and a small grounding side parasitic inductance and is appropriate for high frequency large power by a method wherein an insulator substrate with a semiconductor chip fixed on the surface is arranged in a recess of a metallic substrate, and the length of the side of the insulator substrate is set at a specific length. CONSTITUTION:The insulator substrate 1 is placed in the recess 5A formed in the metallic substrate 5, and the insulator substrate 1 and the metallic substrate 5 are connected to each other by means of a metallized film 2 formed under capacitor chips 7. The length l of the insulator substrate 1 is so set that an angle theta of thermal dissipation becomes 45 deg. or more. Since the thermal dissipation of the semiconductor chip 6 is well performed, and the ground thereof is performed at a relatively short distance, excellent effects such as the difficulty in being affected by the grounding side parasitic inductance can be obtained.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、高周波大電力用として好適な構造を有する半
導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device having a structure suitable for high frequency, high power use.

従来技術と問題点 従来、高周波大電力用半導体装置では、接地側寄住イン
クククンスの低減及び熱放散が重要な要素の一つとなっ
ている。Prior Art and Problems Conventionally, in high frequency, high power semiconductor devices, reduction of parasitic ink noise on the ground side and heat dissipation have become important factors.

第１図は従来の高周波大電力用半導体装置を表わす要部
切断側面図である。FIG. 1 is a cross-sectional side view of essential parts of a conventional high-frequency, high-power semiconductor device.

図に於いて、■は酸化へリリウム等からなる絶縁物基体
、２ば絶縁基体上に形成されたツクライス膜、３はアル
ミナ等からなる絶縁物枠体、４はリート、５は金属基体
、６は半導体チップ、７ばＭＯ３容量等からなるコンデ
ンサ・千ノブをそれぞれ示している。In the figure, ■ is an insulating substrate made of helium oxide, etc., 2 is a tsukurisu film formed on the insulating substrate, 3 is an insulating frame made of alumina, etc., 4 is REET, 5 is a metal substrate, and 6 1 and 2 respectively indicate a semiconductor chip and a capacitor consisting of a MO3 capacitor and the like.

図示の半導体装置では、半導体チップ６及びコンデンサ
・チップ７等の接地はメタライス膜２をつ〆［ｉ＋；Ｌ
！と介して金属基体５に接続することに依り行なってい
る。（足って、高周波を扱う際、界雷に大きい寄生イン
クククンスとなり、半導体装置のゲインを低下させる原
因となっている。In the illustrated semiconductor device, the semiconductor chip 6, capacitor chip 7, etc. are grounded through the metallization film 2 [i+;
! This is done by connecting to the metal base 5 through the. (In addition, when dealing with high frequencies, parasitic ink distortion occurs which is extremely large, causing a reduction in the gain of semiconductor devices.

このような欠点を解消しようとして、第２図に見られる
ような半導体装置か開発された。尚、図では、第１図に
関して説明した部分と同部分は同記号で指示しである。In an attempt to overcome these drawbacks, a semiconductor device as shown in FIG. 2 was developed. In the figure, the same parts as those explained in connection with FIG. 1 are indicated by the same symbols.

この従来例か第１図に関して説明した従来例と相違する
点は、絶縁物基体１が半導体チップ６を丁度搭載できる
ような大きさになっていて、その絶縁物基体１ば金属基
体（ｊに形成された凹所５Ａ内に配設され、また、コン
デンサ・チップ７は金属基体５の表面に載置されている
構造を採っていることである。The difference between this conventional example and the conventional example explained with reference to FIG. The capacitor chip 7 is placed in the formed recess 5A, and the capacitor chip 7 is placed on the surface of the metal base 5.

この構成に依れば、半導体チップ６ば殆と直接的に金属
基体５に接地され、且つ、コンデンサ・チップ７も勿論
金属基体５に直接に接地されることになり、高周波的に
は大変優れた特性か得られる。According to this configuration, the semiconductor chip 6 is almost directly grounded to the metal base 5, and the capacitor chip 7 is of course also directly grounded to the metal base 5, which is very excellent in terms of high frequencies. properties can be obtained.

然し乍ら、この半導体装置では、絶縁物基体１が小さく
なり過きていること及び絶縁物基体１の側壁と金属基体
５の凹所５Ａに於ける側壁との間に間隙が発生ずること
等の理由から熟成（ＩＪｉが悪くなる欠点が生ずる。However, in this semiconductor device, the insulator base 1 is too small and a gap is generated between the side wall of the insulator base 1 and the side wall of the recess 5A of the metal base 5. From ripening (IJi deteriorates).

発明の目的 本発明は、熱放散か良好で、且つ、接地側寄生インダク
タンスが小さく、高周波大電力用とじて好適な半導体装
置を提供する。OBJECTS OF THE INVENTION The present invention provides a semiconductor device that has good heat dissipation, low parasitic inductance on the ground side, and is suitable for high frequency and high power applications.

発明の実施例 第３図は本発明一実施例の要部切断側面図であり、第１
図及び第２図に関して説明した部分と同部分は同記号で
指示しである。Embodiment of the invention FIG. 3 is a cutaway side view of essential parts of an embodiment of the invention, and
The same parts as those described with reference to the figures and FIG. 2 are designated by the same symbols.

図に於いて、！は絶縁物基体１に於ける所定辺の長さ、
θは前記所定辺に対応する半導体チップ６の一辺に於け
るエツジに立てた垂線から外方に向かう熱放散角度をそ
れぞれ示している。In the figure! is the length of a predetermined side in the insulator substrate 1,
θ represents a heat dissipation angle outward from a perpendicular to the edge of one side of the semiconductor chip 6 corresponding to the predetermined side.

本発明では、絶縁物基体１の長さａとして、熟成ｔ１に
角度θが４５°以上となるような長さを採ることに依り
％４５　ｉり敗の面では第１図に見られる装置と殆と変
りない性能を維持し、また、その絶縁物基体１は第２図
に見られる装置と同様に金属基体５乙こ形成された凹所
５Ａ中に載置され、而も、絶縁物基体１と金属基体５と
の間はコンデンサ・チップ７の下面に形成されたメクラ
イス膜２て接続されているので接地側寄生インダクタン
スの影響は第２図に見られる装置と殆と変りない程度に
なっている。尚、絶縁物基体１と金属基体５との間隙に
は熱伝導良好な金属を埋めるようにしても良い。In the present invention, the length a of the insulating substrate 1 is set to such a length that the angle θ is 45 degrees or more during the aging t1, so that the device shown in FIG. The insulator base 1 is placed in the recess 5A formed in the metal base 5, similar to the device shown in FIG. 1 and the metal substrate 5 are connected through the Mecklace film 2 formed on the bottom surface of the capacitor chip 7, so the influence of the parasitic inductance on the ground side is almost the same as in the device shown in FIG. ing. Incidentally, the gap between the insulating substrate 1 and the metal substrate 5 may be filled with a metal having good thermal conductivity.

発明の効果 本発明の半導体装置は、金属基体に絶縁物基体を受容す
る為の凹所を形成し、その凹所中には半導体チップが表
面に固着された絶縁物基体が配設され、その絶縁物基体
の所定辺の長さは、その所定辺に対応する単導体チップ
の一辺のエツジに立てた垂線から外方へ向かう熱放散角
が４５°以上を維持できる程度に長くされ、しかも、前
記金属基体と前記絶縁物基体とば、その間隙を跨ぐ状態
で配置されたコンデンサ・チップのメタライズ膜で接続
された構成になっている為、半導体チップの熱放散は良
好に行なわれ、また、半導体チップの接地もかなり短い
距離で行なわれるので接地側寄生インダクタンスの影響
は受は難い等の優れた効果を奏することができ、従って
、高周波大電力用の半導体装置として有効である。Effects of the Invention In the semiconductor device of the present invention, a recess is formed in a metal base to receive an insulating base, and an insulating base having a semiconductor chip fixed to the surface thereof is disposed in the recess. The length of the predetermined side of the insulating substrate is made long enough to maintain an outward heat dissipation angle of 45° or more from a perpendicular to the edge of one side of the single conductor chip corresponding to the predetermined side, and Since the metal base and the insulator base are connected by a metallized film of a capacitor chip disposed across the gap between them, heat dissipation of the semiconductor chip is performed well, and Since the semiconductor chip is also grounded over a fairly short distance, it can produce excellent effects such as being hardly affected by parasitic inductance on the ground side, and is therefore effective as a semiconductor device for high frequency and high power use.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図は従来例の要部切断側面図、第３図は
本発明一実施例の要部切断側面図である。 図に於いて、１は絶縁物基体、２はメクライス膜、３は
絶縁物枠体、４はリード、５は金属基体、特許出願人　
　　富士通株式会社 代理人弁理士　　玉蟲　久五部 （外３名）1 and 2 are cutaway side views of essential parts of a conventional example, and FIG. 3 is a cutaway side view of essential parts of an embodiment of the present invention. In the figure, 1 is an insulator base, 2 is a Meklais film, 3 is an insulator frame, 4 is a lead, 5 is a metal base, and the patent applicant
Fujitsu Ltd. Representative Patent Attorney Kugobe Tamamushi (3 others)

Claims (1)

【特許請求の範囲】[Claims] 絶縁物′基体を受容する凹所を有する金属基体、表面に
半導体チップか固着され所定辺の長さが該所定辺に対応
する半導体チンプの一辺のニックから外方に向かう熱放
散角が充分大きく且つ前記金属基体の凹所中に配設され
た絶縁物基体、前記金属基体と該金属基体に形成された
凹所中に配設された前記絶縁物基体との間隙を跨く状態
でそれ等各基体表面に配設され且つ下面のメクライス膜
でそれ等各基体間を接続するコンデンサ・千ノブを備え
てなることを特徴とする半導体装置。A metal base having a recess for receiving an insulator base, on the surface of which a semiconductor chip is fixed, the length of a predetermined side corresponds to the predetermined side, and the heat dissipation angle outward from a nick on one side of the semiconductor chip is sufficiently large. and an insulator base disposed in a recess of the metal base, and the like in a state spanning a gap between the metal base and the insulator base disposed in the recess formed in the metal base. 1. A semiconductor device comprising a capacitor and a capacitor disposed on the surface of each substrate and connected between the substrates by a Meklais film on the lower surface.
JP57229705A 1982-12-28 1982-12-28 Semiconductor device Pending JPS59123250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57229705A JPS59123250A (en) 1982-12-28 1982-12-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57229705A JPS59123250A (en) 1982-12-28 1982-12-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59123250A true JPS59123250A (en) 1984-07-17

Family

ID=16896401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57229705A Pending JPS59123250A (en) 1982-12-28 1982-12-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59123250A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04129314A (en) * 1990-09-20 1992-04-30 Murata Mfg Co Ltd Piezoelectric resonator
US6380623B1 (en) * 1999-10-15 2002-04-30 Hughes Electronics Corporation Microcircuit assembly having dual-path grounding and negative self-bias
CN102760703A (en) * 2011-04-28 2012-10-31 苏州科医世凯半导体技术有限责任公司 Composite substrate for high-power component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04129314A (en) * 1990-09-20 1992-04-30 Murata Mfg Co Ltd Piezoelectric resonator
US6380623B1 (en) * 1999-10-15 2002-04-30 Hughes Electronics Corporation Microcircuit assembly having dual-path grounding and negative self-bias
CN102760703A (en) * 2011-04-28 2012-10-31 苏州科医世凯半导体技术有限责任公司 Composite substrate for high-power component

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