JPH0724289B2 - High frequency hybrid integrated circuit - Google Patents
High frequency hybrid integrated circuitInfo
- Publication number
- JPH0724289B2 JPH0724289B2 JP62033955A JP3395587A JPH0724289B2 JP H0724289 B2 JPH0724289 B2 JP H0724289B2 JP 62033955 A JP62033955 A JP 62033955A JP 3395587 A JP3395587 A JP 3395587A JP H0724289 B2 JPH0724289 B2 JP H0724289B2
- Authority
- JP
- Japan
- Prior art keywords
- line
- integrated circuit
- conductor
- hybrid integrated
- ground conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Waveguides (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路に関し、特に回路動作の安定化、
及び回路の小形化ならびに高密度化を可能にした、高周
波用混成集積回路に関する。The present invention relates to a hybrid integrated circuit, and more particularly to stabilization of circuit operation,
The present invention also relates to a high-frequency hybrid integrated circuit that enables miniaturization and high density of the circuit.
従来この種の高周波用混成集積回路は、誘電体基板の一
方の面に形成された線路導体と、前記誘電体基板の他方
の面に形成された接地導体により非対称型ストリップ線
路を構成し、前記線路導体上に能動素子及び受動素子を
搭載してある種の回路動作(発振,増巾等)をする混成
集積回路を構成し、下部開口を有する箱形の誘電体キャ
ップをかぶせて内部を気密封止しておった。Conventionally, this type of high-frequency hybrid integrated circuit forms an asymmetrical strip line by a line conductor formed on one surface of a dielectric substrate and a ground conductor formed on the other surface of the dielectric substrate. A hybrid integrated circuit that carries out some kind of circuit operation (oscillation, amplification, etc.) by mounting active and passive elements on the line conductor, and covers the inside with a box-shaped dielectric cap having a lower opening. It was tightly sealed.
上述した従来の高周波用混成集積回路では、低インピー
ダンスの線路によって回路を構成する必要がある場合に
は、線路導体の線路巾を広くする必要がある。従って、
この場合回路全体の面積も広くなる。また、逆相で励振
されている線路導体が近接して配線されていると、電界
の結合が生じて、帰還による異常発振の原因となるた
め、この様な場合には、線路導体の間隔を広くする必要
がある。これらのため、回路の小型化,高密度化が困難
であった。In the above-described conventional high-frequency hybrid integrated circuit, when it is necessary to configure the circuit with a low-impedance line, it is necessary to widen the line width of the line conductor. Therefore,
In this case, the area of the entire circuit also becomes large. Also, if line conductors that are excited in opposite phase are wired close to each other, electric field coupling will occur, causing abnormal oscillation due to feedback.In such a case, the line conductor spacing should be reduced. Need to be wide. For these reasons, it has been difficult to reduce the circuit size and increase the density.
本発明の高周波用混成集積回路は、誘電体基板の素子搭
載面上に線路導体パターンが形成され、誘電体キャップ
をかぶせ封止した高周波用混成集積回路において、誘電
体キャップの線路導体パターンと対向する部分に突起部
を有し、突起部に誘電体基板の下部接地導体と接続され
た導体層が形成されている。The high frequency hybrid integrated circuit of the present invention is a high frequency hybrid integrated circuit in which a line conductor pattern is formed on an element mounting surface of a dielectric substrate and is covered with a dielectric cap to face the line conductor pattern of the dielectric cap. The conductive layer is formed on the protruding portion, and is connected to the lower ground conductor of the dielectric substrate.
次に本発明について、図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第1図は本発明の一実施例の部分断面図である。第1図
において、誘電体基板1の一方の面には、線路導体パタ
ーン3a,3bが形成され、基板1の下面には接地導体2が
形成されている。また、下部開口を有する箱形の誘電体
キャップ4の内面には、線路導体パターン3bと対向する
部分に突起部5が形成され、突起部5の表面には、接地
導体6が形成されている。接地導体6のいずれかの端は
第2図に示すように、誘電体基板1の接地導体2と半田
等のロウ材7により接続されている。接地導体6が形成
された部分のストリップ線路3bの電界は、第3図の
(b)に示す様に、線路導体3bと接地導体2、及び、線
路導体3bと接地導体6の間に形成されて、ストリップ線
路のインピーダンスを接地導体6がない場合、〔第3図
(a)〕に比べて同じ回路面積で低くすることが可能と
なる。例えば、誘電体基板1として厚さ0.635mmのアル
ミナ基板を使用し、線路導体パターン3bの巾を0.6mmと
した時に線路導体3bと接地導体6との間隔を0.6mmにな
る様に突起部5を設計すると、線路インピーダンスは約
35Ωとなり、キャップ内面の接地導体6がない場合(約
50Ω)に比べて約15Ω線路インピーダンスを下げること
ができる。FIG. 1 is a partial sectional view of an embodiment of the present invention. In FIG. 1, line conductor patterns 3a and 3b are formed on one surface of a dielectric substrate 1, and a ground conductor 2 is formed on the lower surface of the substrate 1. Further, a protrusion 5 is formed on the inner surface of the box-shaped dielectric cap 4 having a lower opening at a portion facing the line conductor pattern 3b, and a ground conductor 6 is formed on the surface of the protrusion 5. . As shown in FIG. 2, one end of the ground conductor 6 is connected to the ground conductor 2 of the dielectric substrate 1 by a brazing material 7 such as solder. The electric field of the strip line 3b where the ground conductor 6 is formed is formed between the line conductor 3b and the ground conductor 2 and between the line conductor 3b and the ground conductor 6 as shown in FIG. 3 (b). Thus, when the strip line does not have the ground conductor 6, the impedance of the strip line can be reduced in the same circuit area as in FIG. 3 (a). For example, when an alumina substrate having a thickness of 0.635 mm is used as the dielectric substrate 1 and the width of the line conductor pattern 3b is set to 0.6 mm, the protrusion 5 is formed so that the distance between the line conductor 3b and the ground conductor 6 becomes 0.6 mm. , The line impedance is about
35 Ω, without the ground conductor 6 on the inner surface of the cap (approx.
The line impedance can be reduced by about 15Ω compared to 50Ω).
第4図は本発明の第2の実施例の部分断面図である。誘
電体基板1、例えば厚さ0.65mmのアルミナ基板上に、線
路導体8及び線路導体9が例えば50Ω線路であれば間隔
0.6mm程度に近接して配線されていて線路導体8と線路
導体9は逆相で励振されている。誘電体キャップ4は、
線路導体8及び9の上にあたるところに突起5が形成さ
れ、突起5の表面には接地導体6が形成されている。接
地導体6のいずれかの端は基板の下面の接地導体2と半
田等のロウ材7により接続されている。本実施例の構造
では、キャップ内面突起部の接地導体6がない場合の第
5図(a)に示すような電界の結合が、接地導体6によ
り第5図(b)の様にシールドされて結合しなくなり、
帰還による異常発振を防止できる。FIG. 4 is a partial sectional view of the second embodiment of the present invention. If the line conductor 8 and the line conductor 9 are, for example, 50Ω lines on the dielectric substrate 1, for example, an alumina substrate having a thickness of 0.65 mm,
The line conductors 8 and 9 are arranged close to each other by about 0.6 mm and are excited in opposite phases. The dielectric cap 4 is
A protrusion 5 is formed on the line conductors 8 and 9 and a ground conductor 6 is formed on the surface of the protrusion 5. One end of the ground conductor 6 is connected to the ground conductor 2 on the lower surface of the substrate by a brazing material 7 such as solder. In the structure of this embodiment, the electric field coupling as shown in FIG. 5 (a) in the case where there is no ground conductor 6 on the cap inner surface protrusion is shielded by the ground conductor 6 as shown in FIG. 5 (b). No longer join,
Abnormal oscillation due to feedback can be prevented.
第6図は本発明の第3の実施例の部分断面図である。第
6図において、誘電体基板1上の線路導体10に対向させ
ている接地導体6は、誘電体キャップ4の内面に露出さ
せずに、誘電体層の内部に設けられて、線路導体10と短
絡する心配がなくされている。FIG. 6 is a partial sectional view of the third embodiment of the present invention. In FIG. 6, the ground conductor 6 facing the line conductor 10 on the dielectric substrate 1 is provided inside the dielectric layer without being exposed to the inner surface of the dielectric cap 4, and is connected to the line conductor 10. There is no need to worry about short circuits.
以上説明した様に本発明は、誘電体基板の一方の面に非
対称型のストリップ線路で構成された回路の一部を、前
記基板の上にかぶせる箱形の誘電体キャップの対向する
部分に設けて近似的に対称型のストリップ線路構造にす
ることにより、回路面積を広げることなく、低インピー
ダンス線路を実現できる効果がある。又、回路の高密度
化に伴う線路間結合による異常発振を防止できる効果も
ある。As described above, according to the present invention, a part of a circuit composed of an asymmetrical strip line is provided on one surface of a dielectric substrate at a facing portion of a box-shaped dielectric cap which is placed on the substrate. By using a strip line structure that is approximately symmetrical, a low impedance line can be realized without increasing the circuit area. Further, there is also an effect that abnormal oscillation due to coupling between lines due to high density of the circuit can be prevented.
第1図は本発明の一実施例の部分断面図、第2図は第1
図のA-A矢視断面図、第3図(a),(b)は第1図の
実施例の電界分布を示す図、第4図は本発明の第2の実
施例の部分断面図、第5図(a),(b)は第4図の実
施例の電界分布を示す図、第6図は誘電体キャップ内面
の導電体層の変形例を示す断面図である。 1……誘電体基板、2……基板下面の接地導体、3a,3b,
8,9,10……線路導体、4……誘電体キャップ、5……キ
ャップ内壁の穴起部、6……キャップ内壁突起部の接地
導体、7……ロウ材。FIG. 1 is a partial sectional view of an embodiment of the present invention, and FIG.
Fig. 3 is a sectional view taken along the line AA, Figs. 3 (a) and 3 (b) are views showing the electric field distribution of the embodiment of Fig. 1, and Fig. 4 is a partial sectional view of the second embodiment of the present invention. 5 (a) and 5 (b) are views showing the electric field distribution in the embodiment of FIG. 4, and FIG. 6 is a sectional view showing a modification of the conductor layer on the inner surface of the dielectric cap. 1 ... Dielectric substrate, 2 ... Ground conductor on the bottom of the substrate, 3a, 3b,
8,9,10 ...... Line conductor, 4 ... Dielectric cap, 5 ... Cap inner wall hole, 6 ... Cap inner wall projection conductor, 7 ... Brazing material.
Claims (1)
ーンが形成され、誘電体キャップをかぶせ封止した高周
波用混成集積回路において、前記誘電体キャップの前記
線路導体パターンと対向する部分に突起部を有し、前記
突起部に前記誘電体基板の下部接地導体と接続された導
体層が形成されていることを特徴とする高周波用混成集
積回路。1. A high-frequency hybrid integrated circuit in which a line conductor pattern is formed on an element mounting surface of a dielectric substrate and is covered with a dielectric cap, and in a portion opposed to the line conductor pattern of the dielectric cap. A hybrid integrated circuit for high frequency, comprising: a protrusion, wherein a conductor layer connected to the lower ground conductor of the dielectric substrate is formed on the protrusion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62033955A JPH0724289B2 (en) | 1987-02-16 | 1987-02-16 | High frequency hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62033955A JPH0724289B2 (en) | 1987-02-16 | 1987-02-16 | High frequency hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63200545A JPS63200545A (en) | 1988-08-18 |
JPH0724289B2 true JPH0724289B2 (en) | 1995-03-15 |
Family
ID=12400914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62033955A Expired - Lifetime JPH0724289B2 (en) | 1987-02-16 | 1987-02-16 | High frequency hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0724289B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2823461B2 (en) * | 1992-12-11 | 1998-11-11 | 三菱電機株式会社 | High frequency band IC package |
JP3967289B2 (en) | 2003-04-30 | 2007-08-29 | 富士通メディアデバイス株式会社 | Duplexer and electronic device |
JPWO2022113739A1 (en) * | 2020-11-30 | 2022-06-02 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59130448A (en) * | 1984-01-06 | 1984-07-27 | Matsushita Electric Ind Co Ltd | Device for sealing circuit element |
-
1987
- 1987-02-16 JP JP62033955A patent/JPH0724289B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS63200545A (en) | 1988-08-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7098531B2 (en) | Jumper chip component and mounting structure therefor | |
JPH0724289B2 (en) | High frequency hybrid integrated circuit | |
JPH11283707A (en) | Connector device for microstrip | |
JPH0451602A (en) | Dielectric filter | |
JPH0575313A (en) | Hybrid integrated circuit device | |
JP2000243877A (en) | Package for semiconductor device and its packaging structure | |
JPH0720919Y2 (en) | Package for microwave integrated circuit | |
JP3600729B2 (en) | High frequency circuit package | |
JPS5881303A (en) | Resonance circuit and electronic circuit | |
JP3259338B2 (en) | Adjusting the inductance of a three-layer stripline inductor | |
JP2000049526A (en) | Dielectric plane antenna | |
JPH0611618Y2 (en) | High frequency oscillator | |
JP2000101306A (en) | Dielectric filter | |
JP2567210B2 (en) | Microwave ground structure | |
JP2002111329A (en) | Dielectric resonator and filter | |
JPH06164206A (en) | Dielectric filter and combination structure of dielectric filter and circuit board | |
JPH0744023Y2 (en) | Package for microwave integrated circuit | |
JP2000323595A (en) | Semiconductor device | |
JP2974034B2 (en) | Circuit board and crystal oscillator using the same | |
JPS63288097A (en) | High-frequency circuit board | |
JP2643858B2 (en) | Composite microwave integrated circuit | |
JP2557081Y2 (en) | Micro stripline filter | |
JPH0122770B2 (en) | ||
JPS605612A (en) | Oscillator | |
JPH10126108A (en) | Circuit device containing dielectric resonator |