JPH0575313A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

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Publication number
JPH0575313A
JPH0575313A JP3231678A JP23167891A JPH0575313A JP H0575313 A JPH0575313 A JP H0575313A JP 3231678 A JP3231678 A JP 3231678A JP 23167891 A JP23167891 A JP 23167891A JP H0575313 A JPH0575313 A JP H0575313A
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JP
Japan
Prior art keywords
surface
dielectric substrate
formed
opening
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3231678A
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Japanese (ja)
Inventor
Hideaki Sato
秀暁 佐藤
Original Assignee
Oki Electric Ind Co Ltd
沖電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Ind Co Ltd, 沖電気工業株式会社 filed Critical Oki Electric Ind Co Ltd
Priority to JP3231678A priority Critical patent/JPH0575313A/en
Publication of JPH0575313A publication Critical patent/JPH0575313A/en
Application status is Pending legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Abstract

PURPOSE:To reduce the effect of an inductance by a thin metallic wire for interconnection by placing the surface of a semiconductor element mounted onto a 1st dielectric board to be almost on a same face as a 3rd metallizing layer being a microwave strip line and a ground layer connected to the surface. CONSTITUTION:Microstrip lines 7a, 7b are formed on the surface of a 1st dielectric board and 3rd metallizing layers 5a, 5b are formed on a part other than the forming part of the lines 7a, 7b. The metallizing layers 5a, 5b are used for the ground layer similarly to the case with the 1st and 2nd metallizing layers 6, 4 and coupled with the 1st and 2nd metallizing layers 6, 4. Then an opening is provided to a desired part of the 1st dielectric board and the depth of the opening is made almost the same as the thickness of an element 9 to be mounted. Thus, when the element 9 is mounted to the opening, the surface is almost made flush with the lines 7a, 7b and the metallizing layers 5a, 5b.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は混成集積回路装置に係り、特に高周波特性が良好でかつ高密度実装に適した混成集積回路装置に関する。 The present invention relates relates to a hybrid integrated circuit device, and particularly high-frequency characteristics regarding hybrid integrated circuit device which is suitable for good and high-density mounting.

【0002】 [0002]

【従来の技術】従来のこの種の装置は、例えば特開平2 Conventionally this type of device, for example, JP-A-2
−135802号公報に開示されているものが知られている。 Those disclosed in -135,802 JP are known. 図3は上述の公報に開示された混成集積回路装置を示す斜視図である。 Figure 3 is a perspective view showing a disclosed in Japanese above hybrid integrated circuit device.

【0003】第1の誘電体基板10の表面にはマイクロ波ストリップライン50a,50b,50cが形成され、裏面には第1の裏面金属化層30が形成されている。 [0003] The first is on the surface of the dielectric substrate 10 microwave stripline 50a, 50b, 50c are formed, the first back metal layer 30 is formed on the back surface. 第1の誘電体基板10には第2の誘電体基板20が表面同志が密着するように積層されており、その裏面には第2の裏面金属化層40が形成されている。 The first dielectric substrate 10 are stacked such that the second dielectric substrate 20 comes into close contact surface comrades, on its back surface are formed second back metallization layer 40.

【0004】第2の誘電体基板20の所定部分には部品を搭載して接続するための穴部が形成され、この穴部を介してストリップライン50a,50b間又はストリップライン50bと第2の裏面金属化層40とを図示しない半田で接合するチップコンデンサー60a,60bが搭載される。 [0004] The second in a predetermined portion of the dielectric substrate 20 is formed a hole portion for connecting mounting parts, stripline 50a through the hole, 50b or between the strip line 50b and the second chip capacitors 60a joining with solder (not shown) and a backside metallization layer 40, 60b is mounted.

【0005】また、別の穴部にはストリップライン50 Further, the strip line 50 to another hole
c上に半田で接合された半導体素子70が搭載される。 A semiconductor element 70 joined with solder on c are mounted.
そしてこの半導体素子70上の図示しない電極と第2の裏面金属化層40とは金属細線80により接続されている。 And they are connected by thin metal wires 80 and the electrode and the second back metal layer 40 (not shown) on the semiconductor device 70.

【0006】更に誘電体基板10,20の側面には第1 Furthermore the side surface of the dielectric substrate 10 and 20 first
の裏面金属化層30と第2の裏面金属化層40とを電気的に接続する側面金属化層90a,90bが形成されている。 The backside metallization layer 30 and the second side metallized layer 90a that electrically connects the backside metallization layer 40, 90b are formed.

【0007】このように従来の混成集積回路装置ではマイクロ波ストリップライン50a,50b,50cをグランド層を形成する第1及び第2の裏面金属化層30, [0007] Thus microwave strip line 50a in the conventional hybrid integrated circuit device, 50b, first and second back metal layer 30 forming a ground layer 50c,
40で両側から挟み込む構造を採用している。 It has adopted the structure sandwiched from both sides in the 40. これによりシールド効果を高め、外部からの電磁波の影響やストリップライン間の相互干渉を軽減するようにしている。 Thus enhance the shielding effect, and so as to reduce mutual interference between the electromagnetic wave effects and strip line from the outside.

【0008】又第2の誘電体基板20の所望部分に穴部を形成し、チップコンデンサー60a,60b、半導体素子70を搭載し、チップコンデンサー60bの一部電極をグランド層となる第2の金属化層40と接続し、半導体素子70のグランド用電極を金属細線80を介してグランド層となる第2の裏面金属化層40へ接続するようにして、ビアホール(Via Hole)によるインダクタンスの悪影響を防止している。 [0008] forming a hole to a desired portion of the second dielectric substrate 20, chip capacitors 60a, 60b, by mounting a semiconductor element 70, a second metal part electrode of the chip capacitor 60b becomes the ground layer connected to the layer 40, and a ground electrode of the semiconductor element 70 so as to be connected to the second back metal layer 40 serving as the ground layer via a thin metal wire 80, the adverse effects of inductance due to the via hole (via Hole) It is prevented.

【0009】 [0009]

【発明が解決しようとする課題】しかし上述した従来の混成集積回路装置では、半導体素子の表面とグランド層となる第2の裏面金属化層との間及び半導体素子表面とマイクロ波ストリップラインの接続表面との間に段差が存在した。 [0008] However, in the conventional hybrid integrated circuit device described above, the connection between and the semiconductor element surface and the microwave strip line of the second back metal layer made of the surface and the ground layer of the semiconductor element step between the surface were present.

【0010】従ってこれらの間を金属細線により接続した場合金属細線が長くなり、これに伴いインダクタンスが増加してその影響が大きくなるという問題点があった。 Accordingly it between these long thin metal wires when connected by thin metal wires, the effect is disadvantageously increased this with the inductance is increased.

【0011】本発明は上述した問題点を解消するためになされたもので、接続用金属細線の長さを短くしインダクタンスの影響を少なくして高周波特性が優れかつ小型化に適した混成集積回路装置を提供することを目的とする。 [0011] The present invention has been made to solve the above problems, a hybrid integrated circuit which is suitable for high and miniaturization is high frequency characteristics by reducing the effect of shortening the length of the connector metal thin wire inductance and to provide a device.

【0012】 [0012]

【課題を解決するための手段】本発明の混成集積回路装置は、表面にマイクロ波ストリップラインと第3金属化層とが形成され、裏面に第1金属化層が形成された第1 Hybrid integrated circuit device of the present invention According to an aspect of the microwave strip line and the third metal layer is formed on the surface, first the first metallization layer on the back surface is formed
の誘電体基板と、表面が前記第1の誘電体基板の表面に密接し、裏面に第2金属化層が形成された第2の誘電体基板と、表面が前記マイクロ波ストリップライン及び前記第3金属化層の表面と略同一面となるよう、裏面を前記第1の誘電体基板に形成された穴部に載置した半導体素子と、前記半導体装置の電極と前記マイクロ波ストリップライン及び前記第3金属化層とを略同一面上で接続する金属細線とを設けたものである。 Of the dielectric substrate, the surface is in close contact with the surface of said first dielectric substrate, a second dielectric substrate which has a second metal layer formed on a back surface, the surface is the microwave strip line and the second 3 so that the surface almost the same surface of the metal layer, and a semiconductor device mounted with the back surface of the hole formed in the first dielectric substrate, the microwave strip line and said the electrode of the semiconductor device it is provided with a metal thin wire connecting the third metallization layer on substantially the same plane.

【0013】 [0013]

【作用】本発明では第1の誘電体基板表面に、載置される半導体素子の厚みと略同一の深さを有する開口部を設けて、この開口部内に半導体素子を載置している。 A first dielectric substrate surface in the present invention, by providing an opening having a thickness substantially the same depth of the semiconductor element to be mounted, and mounting the semiconductor element within the opening. 従ってこの半導体素子の電極面は第1の誘電体基板の表面と略同一面となる。 Thus the electrode surface of the semiconductor element becomes surface almost the same surface of the first dielectric substrate.

【0014】そこで、第1の誘電体基板上に形成されているストリップラインや第3の金属化層と半導体素子の電極とを金属細線により接続した場合、この金属細線自身も略同一面上で接続されることになる。 [0014] Therefore, when the electrode of the first dielectric strip line and the third metallization layer formed on the substrate and the semiconductor element are connected by thin metal wires, the metal thin wire itself on substantially the same plane It will be connected. これにより金属細線の長さを最小限にすることができるためインダクタンスが減りその影響を小さくすることができるのである。 Thus it is of a length of thin metal wires can be reduced reduces the influence thereof inductance it is possible to minimize.

【0015】 [0015]

【実施例】以下本発明の実施例を図1及び図2に基づいて詳細に説明する。 EXAMPLES The following examples of the present invention with reference to FIGS described in detail. 図1は本発明の1実施例に係る混成集積回路装置の斜視図を示したものである。 Figure 1 shows a perspective view of the hybrid integrated circuit device according to an embodiment of the present invention.

【0016】第1の誘電体基板2と、第2の誘電体基板3とがその表面同志を密着させて積層構造を形成している。 [0016] The first dielectric substrate 2, and the second dielectric substrate 3 forms a layered structure is brought into close contact with the surface of each other. 第1の誘電体基板の裏面及び第2の誘電体基板3の裏面にはそれぞれ第1及び第2の金属化層6,4が形成されている。 A first dielectric substrate of the back surface and the second dielectric substrate, respectively the first and second metallization layers 6,4 on the back of 3 is formed.

【0017】これらの第1及び第2の金属化層6,4はグランド層として用いられ、図示しない接続手段により相互接続される。 [0017] These first and second metallization layers 6,4 is used as a ground layer, are interconnected by connecting means (not shown).

【0018】第1の誘電体基板の表面にはマイクロ波ストリップライン7a,7bが形成されると共に、第3の金属化層5a及び5bがマイクロ波ストリップライン7 The first dielectric on the surface of the substrate a microwave strip line 7a, with 7b is formed, the third metal layer 5a and 5b are microwave stripline 7
a,7bの形成部分以外の部分に形成されている。 a, it is formed in a portion other than the formation portion of 7b. この第3の金属化層5a,5bも第1及び第2の金属化層6,4と同様に第グランド層として用いられ、図示しない結合手段により第1及び第2の金属化層6,4と相互接続される。 The third metal layer 5a, 5b also used as the ground layer in the same manner as the first and second metallization layers 6,4, first and second metallization layers by coupling means not shown 6,4 It is interconnected with.

【0019】第1の誘電体基板の所望部分には開口部が設けられ、この開口部の深さは搭載される半導体素子9 [0019] The desired portion of the first dielectric substrate opening is provided, the semiconductor device the depth of the opening is mounted 9
の厚さと略同一となるように形成する。 Formed to have the thickness of the substantially the same. 従って、半導体素子9がこの開口部に搭載された場合、その表面はマイクロ波ストリップライン7a,7b及び第3の金属化層5a,5bと略同一面となる。 Therefore, when the semiconductor element 9 is mounted in the opening, its surface is microwave stripline 7a, 7b and the third metal layer 5a, the 5b substantially the same plane.

【0020】半導体素子9の表面に設けられた図示しない電極とマイクロ波ストリップライン7a,7b及び第3の金属化層5a,5bとは金属細線8により所望の箇所が接続される。 [0020] (not shown) provided on the surface electrode and the microwave strip line 7a of the semiconductor element 9, 7b and the third metal layer 5a, the desired position is connected by thin metal wires 8 and 5b. この結果、接続用の金属細線8は最短距離で略同一面上になるように接続されるため、インダクタンスが最小となり高周波におけるインダクタンスの影響を低減することができる。 As a result, the thin metal wires 8 for connection to be connected so as to be substantially on the same plane in the shortest distance, it is possible inductance to reduce the effect of the inductance in the high frequency becomes minimum.

【0021】図2は本発明の他の実施例を示す斜視図で、グランド層として設けられた第3の金属化層5a, [0021] Figure 2 is a perspective view showing another embodiment of the present invention, the third metallization layer 5a provided as a ground layer,
5bを第1及び第2の誘電体基板2,3の所定部分に設けたビアホール10a,10b,10cにより第1及び第2の金属化層6,4と相互接続してグランド層を形成したものである。 5b the first and second dielectric via holes 10a provided in a predetermined portion of the substrate 2,3, 10b, obtained by forming the ground layer interconnecting the first and second metallization layers 6,4 by 10c it is.

【0022】このように金属化層同志をビアホールにより適宜接続することにより誘電体基板の面積が大きい場合に高周波に対するシールド効果が充分でなかった欠点を補うことができる。 [0022] it is possible to compensate for the disadvantages shielding effect against high frequency is not sufficient in this case the area of ​​the dielectric substrate by appropriately connecting the metallization layer each other by a via hole is large.

【0023】さらに図2に示す実施例では第2の誘電体基板3の開口部を覆うように金属製の蓋1を設けている。 [0023] In yet embodiment shown in FIG. 2 is provided with a lid 1 metal so as to cover the opening of the second dielectric substrate 3. この金属製の蓋1により開口部を覆ってこれを第2 This covers the opening by the lid 1 of the metallic second
の金属化層4と電気的に接続することにより、半導体素子9及びマイクロ波ストリップライン7a,7bを外部の高周波から完全にシールドすることができる。 By connecting the metal layer 4 and the electrically, can be completely shielded semiconductor device 9 and a microwave strip line 7a, and 7b from the outside of the high-frequency.

【0024】 [0024]

【発明の効果】以上実施例に基づいて詳細に説明したように、本発明では第1の誘電体基板に搭載される半導体素子の表面とこれに接続されるマイクロ波ストリップライン及びグランド層となる第3の金属化層とが略同一面上に位置するように構成される。 As it was described in detail with reference to the above embodiments according to the present invention, the first dielectric microwave stripline and the ground layer connected surface to a semiconductor element mounted on the substrate in the present invention configured so that the third metallization layer is located on substantially the same plane. 従って相互接続のための金属細線によるインダクタンスの影響を低減することができる。 Therefore it is possible to reduce the influence of the inductance due to the thin metal wires for interconnections.

【0025】又マイクロ波ストリップラインを上下に吸収される金属化層によるグランド層で挟む構造となるため、マイクロ波ストリップライン間の相互干渉を抑制することができる。 [0025] Since a structure sandwiched by ground layers with a metal layer to be absorbed microwave stripline vertically, it is possible to suppress the mutual interference between microwave strip lines.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例に係る混成集積回路装置の構成を示す斜視図。 Perspective view showing the configuration of a hybrid integrated circuit device according to an embodiment of the present invention; FIG.

【図2】本発明の他の実施例を示す斜視図。 Perspective view showing another embodiment of the present invention; FIG.

【図3】従来の混成集積回路装置の構成を示す斜視図。 Figure 3 is a perspective view showing a configuration of a conventional hybrid integrated circuit device.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 金属製の蓋 2 第1の誘電体基板 3 第2の誘電体基板 4 第2の金属化層 5a,5b 第3の金属化層 6 第1の金属化層 7a,7b マイクロ波ストリップライン 8 金属細線 9 半導体素子 10a,10b,10c ビアホール 1 metal lid 2 first dielectric substrate 3 and the second dielectric substrate 4 second metal layer 5a, 5b third metallization layer 6 first metal layer 7a, 7b microwave stripline 8 fine metal wire 9 semiconductor devices 10a, 10b, 10c via hole

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 表面にマイクロ波ストリップラインと第3金属化層とが形成され、裏面に第1金属化層が形成された第1の誘電体基板と、 表面が前記第1の誘電体基板の表面に密着し、裏面に第2金属化層が形成された第2の誘電体基板と、 表面が前記マイクロ波ストリップライン及び前記第3金属化層の表面と略同一面となるよう、裏面を前記第1の誘電体基板に形成された開口部に載置した半導体素子と、 前記半導体素子の電極と前記マイクロ波ストリップラインおよび前記第3金属化層とを略同一面上で接続する金属細線とを具備してなる混成集積回路装置。 1. A microwave stripline and the third metallization layer on the surface is formed, the first dielectric substrate, wherein the surface first dielectric substrate on which the first metallization layer on the back surface is formed in close contact with the surface of the second dielectric substrate on which the second metal layer formed on the back surface, the surface that becomes the microwave strip line and surface substantially flush of the third metal layer, the back surface metal for connecting the semiconductor device placed on the opening formed in the first dielectric substrate, and electrode and the microwave strip line and said third metallization layer of the semiconductor element on substantially the same plane hybrid integrated circuit device comprising; and a thin line.
  2. 【請求項2】 前記第1乃至第3金属化層を前記第1及び第2の誘電体基板を貫通して設けたビアホール(Vi Wherein said first through hole provided in the third metal layer through said first and second dielectric substrate (Vi
    a Hole)を介して電気的に接続したことを特徴とする請求項1記載の混成集積回路装置。 a Hole) hybrid integrated circuit device according to claim 1, wherein the electrically connected via a.
  3. 【請求項3】 前記第2の誘電体基板に、前記半導体素子及びその接続部を露出させる開口部を設け、この開口部を覆い、前記第1金属化層と電気的に接続される金属製の蓋を設けたことを特徴とする請求項1記載の混成集積回路装置。 To wherein said second dielectric substrate, said semiconductor element and the opening exposing the connection portion is provided to cover the opening, the first metal layer electrically connected to the metal hybrid integrated circuit device according to claim 1, characterized in that a lid.
JP3231678A 1991-09-11 1991-09-11 Hybrid integrated circuit device Pending JPH0575313A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3231678A JPH0575313A (en) 1991-09-11 1991-09-11 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3231678A JPH0575313A (en) 1991-09-11 1991-09-11 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0575313A true JPH0575313A (en) 1993-03-26

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Family Applications (1)

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Country Status (1)

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JP (1) JPH0575313A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923540A (en) * 1993-11-30 1999-07-13 Fujitsu Limited Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power
US6166613A (en) * 1996-07-18 2000-12-26 Matsushita Electric Industrial Co., Ltd. Voltage-controlled resonator, method of fabricating the same, method of tuning the same, and mobile communication apparatus
US6426686B1 (en) * 1999-06-16 2002-07-30 Microsubstrates Corporation Microwave circuit packages having a reduced number of vias in the substrate
US6774748B1 (en) 1999-11-15 2004-08-10 Nec Corporation RF package with multi-layer substrate having coplanar feed through and connection interface
KR100686003B1 (en) * 2000-02-23 2007-02-23 엘지전자 주식회사 Radio frequency device for package and manufacturing method thereof
US20090244869A1 (en) * 2008-04-01 2009-10-01 Nec Electronics Corporation Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring
WO2014083967A1 (en) * 2012-11-29 2014-06-05 オリンパスメディカルシステムズ株式会社 Board structure

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923540A (en) * 1993-11-30 1999-07-13 Fujitsu Limited Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power
US6166613A (en) * 1996-07-18 2000-12-26 Matsushita Electric Industrial Co., Ltd. Voltage-controlled resonator, method of fabricating the same, method of tuning the same, and mobile communication apparatus
US6426686B1 (en) * 1999-06-16 2002-07-30 Microsubstrates Corporation Microwave circuit packages having a reduced number of vias in the substrate
US6774748B1 (en) 1999-11-15 2004-08-10 Nec Corporation RF package with multi-layer substrate having coplanar feed through and connection interface
KR100686003B1 (en) * 2000-02-23 2007-02-23 엘지전자 주식회사 Radio frequency device for package and manufacturing method thereof
US20090244869A1 (en) * 2008-04-01 2009-10-01 Nec Electronics Corporation Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring
US8363421B2 (en) * 2008-04-01 2013-01-29 Renesas Electronics Corporation Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring
WO2014083967A1 (en) * 2012-11-29 2014-06-05 オリンパスメディカルシステムズ株式会社 Board structure
JP5548324B1 (en) * 2012-11-29 2014-07-16 オリンパスメディカルシステムズ株式会社 Board structure
US9060447B2 (en) 2012-11-29 2015-06-16 Olympus Medical Systems Corp. Substrate structure

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