JPS59130448A - Device for sealing circuit element - Google Patents

Device for sealing circuit element

Info

Publication number
JPS59130448A
JPS59130448A JP100184A JP100184A JPS59130448A JP S59130448 A JPS59130448 A JP S59130448A JP 100184 A JP100184 A JP 100184A JP 100184 A JP100184 A JP 100184A JP S59130448 A JPS59130448 A JP S59130448A
Authority
JP
Japan
Prior art keywords
conductor
substrate
conductive layer
cap body
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP100184A
Other languages
Japanese (ja)
Inventor
Masahiko Nitta
新田　政彦
Koichi Kiriyama
桐山　鉱一
Mutsuo Yoshimatsu
吉松　睦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP100184A priority Critical patent/JPS59130448A/en
Publication of JPS59130448A publication Critical patent/JPS59130448A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a device for sealing circuit elements having a good sealing degree by a method wherein a conductor is formed in a ring form in the periphery of the upper surface of a substrate provided with the circuit elements, the upper surface of this insulator is covered with a cap body, a conductive layer is formed on the inner surface of the groove at the part wherein this cap body abuts against the conductor, and this conductive layer is joined to the conductor with solder. CONSTITUTION:An Si substrate 2 is installed on a heat sink 1 with an Si adhesive, the patterns 3 of silver palladium and the circuit elements 4 such as transistors are formed on this substrate 2. Besides, the conductor 5 is formed in a ring form in the periphery of the upper surface of the substrate 2, which conductor 5 is provided at a time by means of silver palladium at the time of forming the patterns 3. On the other hand, the cap body 6 covering the upper surface of the substrate 2 is formed of an ABS resin or a Noryl series resin. The groove 7 is formed in a ring form at the part wherein this cap body 6 abuts against the conductor 5, and thereafter a conductive layer 8 is formed by plating the inner wall of the cap body 6 with the alloy of Sn and Ni series. Then, the groove 7 is filled with low melting point solder 9 and heat-treated, and then the conductive layer 8 and the conductor 5 are adhered with the solder 9, resulting in a sealed structure.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はハイブリッドＩＣ等の回路素子を蓋体によって
確実に密封しようとする回路素子密封装置を提供しよう
とするものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a circuit element sealing device that reliably seals a circuit element such as a hybrid IC with a lid.

従来例の構成とその問題点 回路素子を上面に設けた基板を樹脂製の蓋体で覆い密封
する場合、蓋体と基板との接合面をエポキシ系接着シー
トで接着している。この接着シートによる密封構造ｄ耐
湿性に欠け、内部の回路素子に悪影響を与える欠点があ
る。Conventional Structure and Problems When a substrate on which a circuit element is provided is covered and sealed with a resin lid, the bonding surfaces of the lid and the substrate are bonded with an epoxy adhesive sheet. The sealing structure using this adhesive sheet lacks moisture resistance and has the drawback of adversely affecting internal circuit elements.

発明の目的 本発明は、上記従来の欠点を除去し、よシ密封の度合が
良好な回路素子密封装置を提供しようとするものである
。OBJECTS OF THE INVENTION The present invention aims to eliminate the above-mentioned conventional drawbacks and provide a circuit element sealing device with a good degree of sealing.

発明の構成 本発明においては、上面にトランジスタ等の回路素子を
設けた基板の上面周囲にリング状に導電体を形成し、こ
の絶縁体の上面を学う樹脂性の蓋体を設け、この蓋体の
リング状の導電体に当接する部分にリング状に溝を形成
し、少なくともこの溝の内壁に導電層を形成し、この導
電層と導電体とを半田によって結合するようにして、密
封度の良好な密封を行うようにしているＯ 実施例の説明 以下、本発明の一実施例について、図面を参照して説明
する。図示のように放熱板１の上にシリコン接着゛剤に
よってシリコン基板２を取付ける。Structure of the Invention In the present invention, a conductor is formed in a ring shape around the upper surface of a substrate on which circuit elements such as transistors are provided, and a resin lid is provided to cover the upper surface of the insulator. A ring-shaped groove is formed in the part of the body that comes into contact with the ring-shaped conductor, a conductive layer is formed on at least the inner wall of this groove, and the conductive layer and the conductor are bonded by solder to improve the sealing. DESCRIPTION OF EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings. As shown in the figure, a silicon substrate 2 is attached onto a heat sink 1 using a silicon adhesive.

この基板２の上には銀パラジウムによるパターン３およ
びトランジスタ等の回路素子４が形成されている。基板
２の上面の周囲にはリング状に導電体５が形成されてい
る。この導電体５はパターン３を形成するとき銀パラジ
ウムによって一度に設ける。一方、基板２の上面を覆う
蓋体６をＡＢＳ樹脂あるいはノリル系樹脂によって形成
する。この蓋体６の上記導電体６の当接する部分にリン
グ状に溝７を形成する。その後蓋体６の内壁にＳｎとＮ
ｉ系の合金によるメッキをほどこし導電層８を形成する
。溝７の中に低融点半田９を入れ、加熱処理をして半田
９によって導電層８と導電体５を接着し密封構造とする
。加熱は半田がとける程度の温度の室に入れて行なう。On this substrate 2, a pattern 3 made of silver palladium and circuit elements 4 such as transistors are formed. A ring-shaped conductor 5 is formed around the upper surface of the substrate 2 . This conductor 5 is provided at once with silver palladium when forming the pattern 3. On the other hand, a lid 6 covering the upper surface of the substrate 2 is formed of ABS resin or Noryl resin. A ring-shaped groove 7 is formed in the portion of the lid 6 that is in contact with the conductor 6. After that, Sn and N were applied to the inner wall of the lid body 6.
A conductive layer 8 is formed by plating with an i-based alloy. A low melting point solder 9 is placed in the groove 7 and heat treated to bond the conductive layer 8 and the conductor 5 with the solder 9 to form a sealed structure. Heating is carried out in a chamber at a temperature that melts the solder.

発明の効果 以上のように本発明によれば、基板と蓋体との接合部全
域を半田によって確実に接着してあり、しかも半田は溝
内に入って外部から露出しておらず密封状態は確実なも
のである。Effects of the Invention As described above, according to the present invention, the entire joint between the substrate and the lid is reliably bonded with solder, and the solder enters the groove and is not exposed from the outside, resulting in a sealed state. It is certain.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例における回路素子密封装置の断正
面図である。 １・・・・・・基板、４・・・・・・トランジスタ、５
・・・・・・導電体、６・・・・・・蓋体、７・・・・
・・溝、８・・・・・・導電層、９・・・・・・半田。The figure is a sectional front view of a circuit element sealing device in one embodiment of the present invention. 1...Substrate, 4...Transistor, 5
... Conductor, 6... Lid, 7...
...Groove, 8...Conductive layer, 9...Solder.

Claims (1)

【特許請求の範囲】[Claims] 上面にトランジスタ等の回路素子を設けた基板の上面周
囲にリング状に導電体を形成し、上記絶縁体の上面を覆
う樹脂性の蓋体を設け、この蓋体の上記リング状の導電
体に当接する部分にリング状に溝を形成し、少なくとも
この溝の内壁に導電層を形成し、この導電層と上記導電
体とを半田によって結合してなる回路素子密封装置。A ring-shaped conductor is formed around the upper surface of a substrate on which circuit elements such as transistors are provided, a resin lid is provided to cover the upper surface of the insulator, and the ring-shaped conductor of this lid is covered with a ring-shaped conductor. A circuit element sealing device comprising a ring-shaped groove formed in the abutting portion, a conductive layer formed on at least the inner wall of the groove, and the conductive layer and the conductor bonded together by solder.
JP100184A 1984-01-06 1984-01-06 Device for sealing circuit element Pending JPS59130448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP100184A JPS59130448A (en) 1984-01-06 1984-01-06 Device for sealing circuit element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP100184A JPS59130448A (en) 1984-01-06 1984-01-06 Device for sealing circuit element

Publications (1)

Publication Number Publication Date
JPS59130448A true JPS59130448A (en) 1984-07-27

Family

ID=11489342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP100184A Pending JPS59130448A (en) 1984-01-06 1984-01-06 Device for sealing circuit element

Country Status (1)

Country Link
JP (1) JPS59130448A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200545A (en) * 1987-02-16 1988-08-18 Nec Corp High frequency hybrid integrated circuit
US4788626A (en) * 1986-02-15 1988-11-29 Brown, Boveri & Cie Ag Power semiconductor module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4788626A (en) * 1986-02-15 1988-11-29 Brown, Boveri & Cie Ag Power semiconductor module
JPS63200545A (en) * 1987-02-16 1988-08-18 Nec Corp High frequency hybrid integrated circuit

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