JPS6239036A - Hybrid ic - Google Patents

Hybrid ic

Info

Publication number
JPS6239036A
JPS6239036A JP60178360A JP17836085A JPS6239036A JP S6239036 A JPS6239036 A JP S6239036A JP 60178360 A JP60178360 A JP 60178360A JP 17836085 A JP17836085 A JP 17836085A JP S6239036 A JPS6239036 A JP S6239036A
Authority
JP
Japan
Prior art keywords
chip
resin
bonding
substrate
hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60178360A
Other languages
Japanese (ja)
Inventor
Toshiyuki Sato
敏幸 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP60178360A priority Critical patent/JPS6239036A/en
Publication of JPS6239036A publication Critical patent/JPS6239036A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To protect effectively an IC chip and bonding wire from the stress and contamination by the sealing resin, by bonding the protecting cap for covering the bonding ground for the wiring pattern to constitute a local sealing section, and by molding the outside of the local sealing section with resin. CONSTITUTION:A local sealing section 12 is formed by an insulating layer 14 of glass to surround an IC chip 4 and bonding ground 10 on a substrate 2, and a protecting metal cap 16 which covers the IC chip 4, bonding wire 8 and bonding ground 10 is bonded onto the insulating layer 14. Moreover, the outside of the local sealing section 12 and the substrate 2 is being molded with sealing resin 22 of epoxy resin. In this way, the stress resulted from the resin hardening and the contamination of the IC chip by the sealing resin can be prevented from being applied to the IC chip and bonding wire, without causing the resin to be contacted directly to the IC chip.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、ハイブリッドICに関する。[Detailed description of the invention] (b) Industrial application field The present invention relates to a hybrid IC.

(ロ)従来技術とその間層点 ハイブリッドICは、異なった機能のICチップを組み
合わせて高密度の実装ができる、回路設計の自由度が大
きい、高耐電圧、大電力が必要な回路に使用できるなど
の利点を有する。
(b) Conventional technology and interlayer points Hybrid ICs allow high-density packaging by combining IC chips with different functions, have a large degree of freedom in circuit design, and can be used in circuits that require high withstand voltage and large power. It has the following advantages.

ところで、このような特長を有するハイブリッドICの
製造にあたっては、通常、配線パターンが形成された基
板上にICチップを配置し、このICチップ上の電極と
基板上のボンディングランドとをボンディングワイヤー
を介して電気的に接続する。次いで、ICチップ、ボン
ディングワイヤー、ボンディングランドをエポキシ樹脂
等で覆って局所封止をし、さらに、これら全体をエポキ
シ樹脂でモールドすることが行なわれている。
By the way, in manufacturing a hybrid IC having such features, an IC chip is usually placed on a substrate on which a wiring pattern is formed, and the electrodes on the IC chip and the bonding lands on the substrate are connected via bonding wires. Connect electrically. Next, the IC chip, bonding wires, and bonding lands are covered with epoxy resin or the like for local sealing, and then the whole is molded with epoxy resin.

上記のように、ICチップ部分を局所封止するのは、全
体を直接に樹脂でモールドすると、樹脂の硬化時の収縮
等によってICチップ部分に大きな応力が加わりICチ
ップが歪んだり、ボンディングワイヤーの接続部が剥が
れたりすることがあるのでこれを防止するためである。
As mentioned above, the reason for locally sealing the IC chip part is that if the whole part is directly molded with resin, a large stress will be applied to the IC chip part due to shrinkage when the resin hardens, causing the IC chip to become distorted and bonding wires to be fused. This is to prevent the connection from peeling off.

しかしながら、このように局所封止を予め行なう場合で
も、局所封止用の樹脂が直接1cチップ表面に塗布され
るので、ICチップ表面が樹脂の含有成分等によって汚
染されることがある。また、依然として局所封止用の樹
脂の硬化時にICチップやボンディングワイヤー等に応
力が加わる。このため、ハイブリッドICの信頼性、素
子の劣化等の問題が未だ十分に解消されていない。
However, even when local sealing is performed in advance in this way, the resin for local sealing is directly applied to the surface of the 1c chip, so the IC chip surface may be contaminated by components contained in the resin. Moreover, stress is still applied to IC chips, bonding wires, etc. when the local sealing resin is cured. For this reason, problems such as reliability of hybrid ICs and deterioration of elements have not yet been sufficiently resolved.

本発明は、このような事情に鑑みてなされたものであっ
て、ハイブリッドtCの信頼性の向上を図り、従来では
実現できなかった高性能なICチップが搭載できるよう
にすることを目的とする。
The present invention has been made in view of the above circumstances, and aims to improve the reliability of hybrid TC and to enable it to be equipped with a high-performance IC chip that could not be realized in the past. .

(ハ)問題点を解決するための手段 本発明は、上記の目的を達成するために、配線パターン
が形成された基板上にICチップを配置する一方、前記
基板に対して前記ICチップおよびICチップが電気的
に接続される前記配線パターンのボンディングランドを
覆う保護キャップを固着して局所封止部を構成し、この
局所封止部の外部を樹脂でモールド1.ている。
(C) Means for Solving the Problems In order to achieve the above object, the present invention arranges an IC chip on a substrate on which a wiring pattern is formed, and at the same time, the IC chip and the IC A protective cap covering the bonding land of the wiring pattern to which the chip is electrically connected is fixed to form a local sealing part, and the outside of the local sealing part is molded with resin. ing.

(ニ)作用 本発明によれば、ICチップとボンディングランドを含
む部分が保護キャップで覆われているので、樹脂でモー
ルドしても樹脂が直接1Gチツプなどに接触することが
ない。このため、対土用の樹脂によるICチップの汚染
や、樹脂の硬化で発生ずる応力がICチップやボンディ
ングワイヤーに加わるといったことが防止される。
(D) Function According to the present invention, since the portion including the IC chip and the bonding land is covered with a protective cap, even when molded with resin, the resin does not come into direct contact with the 1G chip or the like. Therefore, contamination of the IC chip by the earth-bound resin and application of stress generated by hardening of the resin to the IC chip and bonding wire can be prevented.

(ホ)実施例 第1図は本発明の実施例に係るハイブリッドICの断面
図、第2図は竿1図のハイブリッドICの組み立て途中
の状態を示す斜視図である。これらの図において、符号
lはハイブリッドIC12は例えば、セラミック製の基
板、4はこの基板2上に配置されたICチップ、6は基
板2上に形成された配線パターンである。配線パターン
らにはICチップ4の固定位置の周りにこのICチップ
4がボンディングワイヤー8を介して電気的に接続され
るボンディングランドlOが設けられている。
(e) Embodiment FIG. 1 is a sectional view of a hybrid IC according to an embodiment of the present invention, and FIG. 2 is a perspective view showing the hybrid IC shown in FIG. 1 in a state in the middle of being assembled. In these figures, reference numeral 1 indicates a substrate of the hybrid IC 12 made of, for example, ceramic, 4 indicates an IC chip disposed on this substrate 2, and 6 indicates a wiring pattern formed on the substrate 2. The wiring patterns are provided with bonding lands 10 around the fixed positions of the IC chips 4 to which the IC chips 4 are electrically connected via bonding wires 8.

12は局所封止部であって、この局所封止部12は、基
板2上にICチップ4およびボンディングランド10を
取り囲んでガラスでできた絶縁層14が形成され、この
絶縁層14の上にICチップ4、ボンディングワイヤー
8およびボンディングランドlOを覆う金属製の保護キ
ャップ16を接着剤18で固着して構成されている。こ
れにより、ICチップ4と保護キャップ16との間に一
定容量の空間部20が形成される。そして、上記局所封
止部12および基板2の外部がエポキシ樹脂でできた封
止用樹脂22でモールドされている。
Reference numeral 12 denotes a local sealing section, in which an insulating layer 14 made of glass is formed on the substrate 2 surrounding the IC chip 4 and the bonding land 10; It is constructed by fixing a metal protective cap 16 that covers the IC chip 4, bonding wire 8, and bonding land 1O with an adhesive 18. As a result, a space 20 having a certain capacity is formed between the IC chip 4 and the protective cap 16. The local sealing portion 12 and the outside of the substrate 2 are molded with a sealing resin 22 made of epoxy resin.

なお、24は配線パターン6の一端部に接続されたリー
ドフレームである。
Note that 24 is a lead frame connected to one end of the wiring pattern 6.

このハイブリッドICIの組み立てに際しては、配線パ
ターン6が形成された基板2上にガラスペーストを印刷
等によって塗布、焼成して絶縁層14を形成し、次いで
、ICチップ4を配置してICチップ4とボンディング
ランド10とをボンディングワイヤー8で電気的に接続
する。ボンディング後、絶縁層14の上に接着剤18を
塗布して保護キャップ16を接着する。続いて、他の部
品を搭載した後、全体をエポキシ樹脂などの封止用樹脂
22でモールドする。
When assembling this hybrid ICI, a glass paste is coated by printing or the like on the substrate 2 on which the wiring pattern 6 is formed, and then baked to form the insulating layer 14, and then the IC chip 4 is placed and the IC chip 4 and The bonding land 10 is electrically connected with the bonding wire 8. After bonding, an adhesive 18 is applied onto the insulating layer 14 to adhere the protective cap 16. Subsequently, after mounting other parts, the whole is molded with a sealing resin 22 such as epoxy resin.

なお、この実施例では保護キャップ16として金属製の
ものを使用しているので、ICチップに対する電磁シー
ルの役l]を果すことになるので都合がよい、1.かじ
、これに限定されるものではなく、保護キャップとして
は、プラスチック製やガラス製のものを使用することし
可能である。その場合には、絶縁層14を省略すること
ができる。
In this embodiment, since a metal material is used as the protective cap 16, it serves as an electromagnetic shield for the IC chip, which is convenient.1. The protective cap is not limited to the rudder, and the protective cap may be made of plastic or glass. In that case, the insulating layer 14 can be omitted.

(へ)効果 以上のように本発明によれば、ICチップを中心として
ボンディングワイヤー、ボンディングランドが保護キャ
ップで被覆されているので、封止用樹脂による汚染や応
力から有効に保護することができる。このため、ハイブ
リッドICの信頼性が一層向上し、従来では実現できな
かった高性能なICチップが搭載できるようになる等の
優れた効果が発揮される。
(f) Effects As described above, according to the present invention, since the bonding wires and bonding lands around the IC chip are covered with a protective cap, they can be effectively protected from contamination and stress caused by the sealing resin. . Therefore, the reliability of the hybrid IC is further improved, and excellent effects such as being able to mount a high-performance IC chip that could not be realized in the past are exhibited.

【図面の簡単な説明】 第1図は本発明の実施例のハイブリッドICの断面図、
第2図は第1図のハイブリッドICの組み立て途中の状
態を示す斜視図である。 l・・・ハイブリッドIC,2・・・基板、4・・・I
Cチップ、6・・・配線パターン、lO・・・ボンディ
ングランド、12・・・局所封止部、I6・・・保護キ
ャップ、22・・・封止用樹脂
[Brief Description of the Drawings] Fig. 1 is a sectional view of a hybrid IC according to an embodiment of the present invention;
FIG. 2 is a perspective view showing a state in which the hybrid IC shown in FIG. 1 is being assembled. l...Hybrid IC, 2...Substrate, 4...I
C chip, 6... Wiring pattern, 1O... Bonding land, 12... Local sealing part, I6... Protective cap, 22... Sealing resin

Claims (1)

【特許請求の範囲】[Claims] (1)配線パターンが形成された基板上にICチップを
配置する一方、前記基板に対してICチップおよびIC
チップが電気的に接続される前記配線パターンのボンデ
ィングランドを覆う保護キャップを固着して局所封止部
を構成し、この局所封止部の外部を封止用樹脂でモール
ドしたことを特徴とするハイブリッドIC。
(1) While placing an IC chip on a substrate on which a wiring pattern is formed, the IC chip and the IC chip are placed on the substrate.
A protective cap covering the bonding land of the wiring pattern to which the chip is electrically connected is fixed to form a local sealing part, and the outside of the local sealing part is molded with a sealing resin. Hybrid IC.
JP60178360A 1985-08-13 1985-08-13 Hybrid ic Pending JPS6239036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60178360A JPS6239036A (en) 1985-08-13 1985-08-13 Hybrid ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60178360A JPS6239036A (en) 1985-08-13 1985-08-13 Hybrid ic

Publications (1)

Publication Number Publication Date
JPS6239036A true JPS6239036A (en) 1987-02-20

Family

ID=16047124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60178360A Pending JPS6239036A (en) 1985-08-13 1985-08-13 Hybrid ic

Country Status (1)

Country Link
JP (1) JPS6239036A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03273667A (en) * 1990-03-23 1991-12-04 Mitsubishi Materials Corp Resin seal type hybrid integrated circuit
FR2723258A1 (en) * 1994-07-27 1996-02-02 Sat Gallium arsenide bare chip encapsulation for high frequency hybrid circuit
US5917246A (en) * 1995-03-23 1999-06-29 Nippondenso Co., Ltd. Semiconductor package with pocket for sealing material
JP2015130492A (en) * 2013-12-05 2015-07-16 ローム株式会社 semiconductor module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03273667A (en) * 1990-03-23 1991-12-04 Mitsubishi Materials Corp Resin seal type hybrid integrated circuit
FR2723258A1 (en) * 1994-07-27 1996-02-02 Sat Gallium arsenide bare chip encapsulation for high frequency hybrid circuit
US5917246A (en) * 1995-03-23 1999-06-29 Nippondenso Co., Ltd. Semiconductor package with pocket for sealing material
JP2015130492A (en) * 2013-12-05 2015-07-16 ローム株式会社 semiconductor module

Similar Documents

Publication Publication Date Title
US5600181A (en) Hermetically sealed high density multi-chip package
GB2213640A (en) Electronic device package with peripheral carrier structure of a different material
JPS6394645A (en) Electronic device
JPS6239036A (en) Hybrid ic
JP2895504B2 (en) Semiconductor device
JPH08125071A (en) Semiconductor device
JP2734424B2 (en) Semiconductor device
JP2001168493A5 (en)
JPH0685126A (en) Semiconductor device
JP2904154B2 (en) Electronic circuit device including semiconductor element
JPS63244631A (en) Manufacture of hybrid integrated circuit device
JP2914679B2 (en) Hybrid integrated circuit device
JPH06334070A (en) Hybrid integrated circuit device
JPH066465Y2 (en) Assembly structure of hybrid integrated circuit
JPH05267503A (en) Semiconductor device
JPH0870057A (en) Hybrid ic
JP3413135B2 (en) Semiconductor module manufacturing method
JPS62189798A (en) Composition of hybrid ic
JPS61296743A (en) Chip carrier
JPS60242647A (en) Mounting method of hybrid integrated circuit
JPS5961094A (en) Method of producing composited electronic part
JPS62252155A (en) Hybrid integrated circuit
KR200156148Y1 (en) Semiconductor package
JPH0521342B2 (en)
KR0163214B1 (en) Integrated circuit package using ceramic substrate and manufacturing method thereof