JPS63110756A - Package for transistor - Google Patents
Package for transistorInfo
- Publication number
- JPS63110756A JPS63110756A JP61258931A JP25893186A JPS63110756A JP S63110756 A JPS63110756 A JP S63110756A JP 61258931 A JP61258931 A JP 61258931A JP 25893186 A JP25893186 A JP 25893186A JP S63110756 A JPS63110756 A JP S63110756A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- container
- cap
- metallized
- ceramic material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910010293 ceramic material Inorganic materials 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 abstract description 12
- 230000005684 electric field Effects 0.000 abstract description 5
- 239000000919 ceramic Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 238000005219 brazing Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000009291 secondary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Microwave Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はトランジスタの容器に関し、特に高周波用のト
ランジスタの容器に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a container for a transistor, and particularly to a container for a high frequency transistor.
従来、高周波用のトランジスタの容器は、端子と実装基
板側のストリップ・ラインに引出し易いようその側壁は
セラミック材料で構成されることが多く、それに伴い封
止を目的とするキャップは、一般に、側壁と同様にセラ
ミック材料で構成されている。Conventionally, the side walls of high-frequency transistor containers are often made of ceramic material so that they can be easily drawn out to the terminals and strip lines on the mounting board side. It is also made of ceramic material.
第２図は従来のトランジスタの容器の一例を示す断面図
である。FIG. 2 is a sectional view showing an example of a conventional transistor container.
第２図に示すように、従来のトランジスタの容器は、容
器内部側が部分メタライズされた部分メタライズ面２′
を有しているセラミック材料で作られたキャップ１′と
、封止ろう材３と、側壁５に設けられた１！！す壁メタ
ライズ面４と、端子６と、放熱板７とトランジスタチッ
プ９を搭載するための絶縁板（通常セラミック材料）８
とから構成されている。端子６とトランジスタチップっ
け金属細線１０によって接続配線されている。As shown in FIG. 2, a conventional transistor container has a partially metallized surface 2' where the inside of the container is partially metallized.
A cap 1' made of a ceramic material having a cap 1', a sealing brazing material 3, and a cap 1' provided on the side wall 5! ! an insulating plate (usually made of ceramic material) 8 for mounting a metallized wall surface 4, a terminal 6, a heat sink 7, and a transistor chip 9;
It is composed of. Connection wiring is made between the terminal 6 and the transistor chip metal thin wire 10.
上述した従来のトランジスタの容器は、特に高周波用、
即ち、数ＭＨ７，以上で動作するトランジスタの容２ル
には、キャップの材料としてセラミックが用いられ、そ
の場合、容器の側壁材料として用いられるセラミックと
キャップの材料との熱膨張率がほぼ同じなので優れた気
密性が得られるが反面次に示すような欠点を有している
。The conventional transistor container mentioned above is particularly suitable for high frequencies,
In other words, ceramic is used as the material for the cap of a transistor that operates at several MH7 or higher, and in that case, the coefficient of thermal expansion of the ceramic used as the side wall material of the container and the material of the cap are almost the same. Although excellent airtightness can be obtained, it has the following drawbacks.
即ち、第２図に示すように、トランジスタが高周波で大
出力を扱う場合、■・ランジスタの容器内部に搭載され
動作しているトランジスタチップ９から輻射される高周
波電力は、セラミックのキャップ１′を通して外部に漏
れ、このトランジスタの周辺に置かれている他機器な電
界を扱う装置に悪影響を及ぼす。That is, as shown in Fig. 2, when a transistor handles high frequency and large output, the high frequency power radiated from the operating transistor chip 9 mounted inside the transistor container is transmitted through the ceramic cap 1'. It leaks to the outside and has an adverse effect on other equipment that handles electric fields placed around this transistor.
また、トランジスタが高周波で小信号を扱う場合、この
トランジスタは、このトランジスタの周辺で高周波大出
力を扱う池の装置から輻射される高周波信号によって悪
影響を受けやすい。Further, when a transistor handles a small signal at a high frequency, this transistor is likely to be adversely affected by the high frequency signal radiated from a device around the transistor that handles a high frequency and large output.
本発明のトランジスタの容器は、セラミック材料で構成
されたキャップを有するトランジスタの容器において、
前記キャップの内側全面がメタライズされている。The transistor container of the present invention has a cap made of a ceramic material, and includes:
The entire inside surface of the cap is metallized.
次に、本発明の実施例について図面を９照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing one embodiment of the present invention.
本実施例と第２図に示す従来の１〜ランジスタの容器の
一例と異なる点は、第１図のトランジスタの容器におい
てキャップ１の内部側が全面メタライズされたメタライ
ズ面２を有している点である。The difference between this embodiment and the conventional example of a transistor container shown in FIG. 2 is that in the transistor container shown in FIG. be.
第１図に示すように容器内部側が全面メタライズされた
メタライズ面２を有するセラミック材料で作られたキャ
ップ１を用いたトランジスタの容器においては、トラン
ジスタチップ９とその周辺は電気的にシールドされ、従
ってトランジスタチップ９の動作時に発生する高周波電
界の外部への漏れを少くし、又、逆に、外部の高電界か
ら微弱信号を扱うトランジスタチップ９が影響を受けな
いように電気的にシールドされる。As shown in FIG. 1, in a transistor container using a cap 1 made of a ceramic material having a metallized surface 2 whose entire inside is metallized, the transistor chip 9 and its surroundings are electrically shielded, and therefore The leakage of the high frequency electric field generated during the operation of the transistor chip 9 to the outside is reduced, and conversely, the transistor chip 9, which handles weak signals, is electrically shielded from being affected by the external high electric field.
キャップ１の材質は容器内部側に全面メタライズを施さ
ない場合と同一であり、又側壁５の材料として用いられ
ているセラミック材とほぼ同一の熱膨張率を持ち、気密
性を悪化させることはない。The material of the cap 1 is the same as that in the case where the entire inside of the container is not metalized, and has almost the same coefficient of thermal expansion as the ceramic material used as the material of the side wall 5, so it does not deteriorate airtightness. .
本実施例は高出力トランジスタを例示したが、高周波小
信号トランジスタでも放熱板７の代りにセラミ・ツク等
の絶縁材が用いられ、はぼ同一の構造をとることができ
る。又封止はろう材でなく樹脂を用いてもさしつかえな
い。Although this embodiment exemplifies a high-output transistor, a high-frequency small-signal transistor can also have almost the same structure by using an insulating material such as ceramic or the like instead of the heat sink 7. Also, resin may be used instead of brazing material for sealing.
ｒ発明の効果〕
以上説明したように本発明は、セラミックを材質として
用いたキャップの容器内部側の全面メタライズすること
により、高周波トランジスタは電気的にシールドされて
内外部に及ぼす悪影響が軽減される効果がある。また容
器の内部に対してのシールド効果として、トランジスタ
チップの性能指数悪化の要因となる容器の帰還容量を同
時に軽減させる副次的効果も有する。[Effects of the Invention] As explained above, in the present invention, by metallizing the entire inside of the container of the cap using ceramic as the material, the high frequency transistor is electrically shielded and the adverse effects on the inside and outside are reduced. effective. Furthermore, as a shielding effect on the inside of the container, it also has the secondary effect of simultaneously reducing the feedback capacitance of the container, which is a factor in deteriorating the performance index of the transistor chip.
第１図は本発明の一実施例を示す断面図、第２図は従来
のトランジスタの容器の一例を示す断面図である。
１．１′・・・キャップ、２・・・メタライス面、２′
・・・部分メタライズ面、３・・・ろう材、４・・・側
壁メタライズ面、５・・・側壁、６・・・端子、７・・
・放熱板、８・・・絶縁板、９・・・トランジスタチッ
プ、１０・・・金属細線。
代理人 弁理士 内 原 １り：ｊ二゛″ｉ（−；、
。
＼、−１FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing an example of a conventional transistor container. 1.1'...cap, 2...metallic surface, 2'
...partial metallized surface, 3...brazing material, 4...side wall metallized surface, 5...side wall, 6...terminal, 7...
- Heat sink, 8... Insulating plate, 9... Transistor chip, 10... Metal thin wire. Agent Patent Attorney Uchihara 1ri:j2゛″i(-;,
. \, -1
Claims (1)
スタの容器において、前記キャップの内側全面がメタラ
イズされていることを特徴とするトランジスタの容器。1. A transistor container having a cap made of a ceramic material, wherein the entire inner surface of the cap is metallized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61258931A JPS63110756A (en) | 1986-10-29 | 1986-10-29 | Package for transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61258931A JPS63110756A (en) | 1986-10-29 | 1986-10-29 | Package for transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63110756A true JPS63110756A (en) | 1988-05-16 |
Family
ID=17327030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61258931A Pending JPS63110756A (en) | 1986-10-29 | 1986-10-29 | Package for transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63110756A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04159757A (en) * | 1990-10-23 | 1992-06-02 | Nec Corp | Semiconductor device |
| JPH0536841U (en) * | 1991-08-27 | 1993-05-18 | 京セラ株式会社 | Electronic parts storage package |
| JPH05251577A (en) * | 1991-10-02 | 1993-09-28 | Oki Electric Ind Co Ltd | Manufacture of ceramic package |
| JPH0677251U (en) * | 1993-03-29 | 1994-10-28 | 京セラ株式会社 | Package for storing semiconductor devices |
-
1986
- 1986-10-29 JP JP61258931A patent/JPS63110756A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04159757A (en) * | 1990-10-23 | 1992-06-02 | Nec Corp | Semiconductor device |
| JPH0536841U (en) * | 1991-08-27 | 1993-05-18 | 京セラ株式会社 | Electronic parts storage package |
| JPH05251577A (en) * | 1991-10-02 | 1993-09-28 | Oki Electric Ind Co Ltd | Manufacture of ceramic package |
| JPH0677251U (en) * | 1993-03-29 | 1994-10-28 | 京セラ株式会社 | Package for storing semiconductor devices |
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