JPS62291038A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62291038A JPS62291038A JP61135284A JP13528486A JPS62291038A JP S62291038 A JPS62291038 A JP S62291038A JP 61135284 A JP61135284 A JP 61135284A JP 13528486 A JP13528486 A JP 13528486A JP S62291038 A JPS62291038 A JP S62291038A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- substrate
- conductor
- fet
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 abstract description 18
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は、高周波用ｉ”ＥＴ（例えばＧａＡｓＦＥＴな
ど）の混成集積回路における接地、及び、バイアス方法
に関し、特にＦＥＴを基板上の端に接着し、更に上記基
板端の接地導体上に、コンデンサが接着され、上記ＰＥ
Ｔの接地電極を、基板上導体膜を介し、コンデンサへ接
続することに関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a grounding and biasing method in a hybrid integrated circuit for high frequency i''ETs (e.g. GaAs FETs), and in particular is glued to the edge of the board, and further a capacitor is glued onto the ground conductor at the end of the board, and the PE
This relates to connecting the ground electrode of T to the capacitor via the conductor film on the substrate.
従来、高周波用ＦＥＴを含む混成集積回路において、高
周波用ＦＥＴを接地する場合は、第２図（ａ）の平面図
、および同図（ｂ）の断面図に示す如く。Conventionally, in a hybrid integrated circuit including a high-frequency FET, when the high-frequency FET is grounded, it is as shown in the plan view of FIG. 2(a) and the cross-sectional view of FIG. 2(b).
接地導体１上に分割され固着された導体膜回路２を有す
る絶縁基板３の間に、高周波用ＦＥ ’Ｉ’ ］と両側
にコンデンサ５が接地導体２に固着されており、このコ
ンデンサ５の上面電＋ｊｌｂと、高周波用ＦＥＴＩの接
地電極７を、ワイヤー（金、アルミニウム線など）１０
で、接続することにより、高周波接地を行い、更に分割
された絶縁基板３上の導体膜回路１２とコンデンサ６を
使用して、自己バイアス回路を形成し高周波用ＦＥＴに
バイアスを印加していた。Between an insulating substrate 3 having a conductive film circuit 2 divided and fixed on a ground conductor 1, a high frequency FE 'I'] and a capacitor 5 are fixed to the ground conductor 2 on both sides. Connect the ground electrode 7 of the high frequency FETI to the wire (gold, aluminum wire, etc.) 10.
By connecting them, high-frequency grounding is performed, and a self-bias circuit is formed using the conductive film circuit 12 on the divided insulating substrate 3 and the capacitor 6 to apply bias to the high-frequency FET.
上述した従来の接地方法では、高周波ＦＥＴを、自己バ
イアスで使用する場合、基板を分割し、使用しているた
めの部品点数がＪＹＲ／１１１し、組立歩留の低下及び
、高価格となる欠点がある。In the conventional grounding method described above, when using a high-frequency FET with self-bias, the number of parts is JYR/111 because the board is divided and used, which reduces assembly yield and increases cost. There is.
上記問題点に対し、本発明では伝送基板の端に。 To solve the above problems, the present invention solves the problem at the edge of the transmission board.
素子を搭載し、素子の接地電極と、上記基板端の接地導
体上に搭載されたコンデンサの上面電極とを、基板上の
メタライズ層を介して、接続したことを特徴とする。It is characterized in that an element is mounted, and the ground electrode of the element is connected to the upper surface electrode of the capacitor mounted on the ground conductor at the end of the substrate via a metallized layer on the substrate.
次に、本発明について図面を診照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、一実施例であり、（ａｌはその断面図。FIG. 1 shows an example (al is a cross-sectional view thereof).
（ｂｌはその平面図を示す。ＦＥＴ１累子は、伝送基板
３の上に、伝送基板３とコンデンサ５は、接地導体２の
上にそれぞれ搭載されている。ＦＥＴ累子１のゲート（
電極８とドレイン電極９は、ワイヤー１０で伝送基板３
上の導体膜４に接続されている。(bl shows the plan view. The FET 1 resistor is mounted on the transmission board 3, and the transmission board 3 and the capacitor 5 are mounted on the ground conductor 2. The gate of the FET 1 (
The electrode 8 and the drain electrode 9 are connected to the transmission board 3 with a wire 10.
It is connected to the upper conductor film 4.
ソース電極７は、コンデンサ５の上面電極６とワイヤー
１０で接ｆＲＧれており％更に、コンデンサ５の上面電
極６と伝送基板３の導体膜１２が、ワイヤー１０で接続
されている。The source electrode 7 is in contact with the upper electrode 6 of the capacitor 5 through a wire 10, and the upper electrode 6 of the capacitor 5 and the conductor film 12 of the transmission board 3 are connected through the wire 10.
このような１本発明によるＦ Ｅ Ｔの搭載接地構造に
よれば、伝送基板３の厚みを薄くすれはする程、またＦ
Ｅ ’Ｉ’ １を基板３の端へ寄せれば寄せる程、接
地距離が短くなり、高周波での１ｔＦ特性におよばず影
Ｊが小さくなる。しかも伝へ基板３を分割し、コンデン
サ５を２個ＦＥＴＩの両端に搭載する必要もなく、また
基板３の端に１コンテンサ５を１個搭載するだけで自己
バイアス回路を形成することができる。According to the FET mounting and grounding structure according to the present invention, the thinner the transmission board 3 is, the more the FET is mounted and grounded.
The closer E 'I' 1 is to the edge of the substrate 3, the shorter the grounding distance becomes, and the shadow J becomes smaller without reaching the 1tF characteristic at high frequencies. Furthermore, there is no need to divide the substrate 3 and mount two capacitors 5 on both ends of the FETI, and a self-bias circuit can be formed by simply mounting one capacitor 5 on the end of the substrate 3.
以上のとおり、本発明によれは、コストパフォーマンス
が優れた半導体装置が提供される。As described above, the present invention provides a semiconductor device with excellent cost performance.
第１図（ａｌ 、 （ｂｌは夫々本発明の一実施例を説
明するための半面図、断面図、第２図（ａ） 、 （Ｉ
ｌｌは夫々従来の混成集積回路の一例の平面図と断面図
である。
■・・・・・高周波用ＦＥＴ、２・・・・・・接地導体
、３・・・・絶縁基板、４・・・・・・導体膜回路、５
・・・・・・コンデンサ、６・・・・・上面電極、７・
・・・・・接地電極、８・・・・・・ゲート電極、９・
・・・ドレイン電極、１０・・ ・ワイヤ（α）
第２
Ｘ−Ｘ’断七凹
（ｂ）
凹
（ｂ）
凹FIG. 1(al) and (bl are a half view and a sectional view for explaining one embodiment of the present invention, respectively, and FIG. 2(a), (I
ll are a plan view and a cross-sectional view, respectively, of an example of a conventional hybrid integrated circuit. ■...High frequency FET, 2...Grounding conductor, 3...Insulating substrate, 4...Conductor film circuit, 5
... Capacitor, 6 ... Top electrode, 7.
...Ground electrode, 8...Gate electrode, 9.
・・・Drain electrode, 10... ・Wire (α) 2nd X-X' section concave (b) concave (b) concave
Claims (1)
子の接地電極が上記、基板上の導体層へ接続され、更に
、基板端の接地導体上に搭載されたコンデンサへ接続さ
れて接地されることを特徴とする半導体装置。A semiconductor element is mounted on the edge of the transmission board, and the ground electrode of this semiconductor element is connected to the conductor layer on the board, and is further connected to a capacitor mounted on the ground conductor at the end of the board to be grounded. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135284A JPH07107907B2 (en) | 1986-06-10 | 1986-06-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135284A JPH07107907B2 (en) | 1986-06-10 | 1986-06-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62291038A true JPS62291038A (en) | 1987-12-17 |
| JPH07107907B2 JPH07107907B2 (en) | 1995-11-15 |
Family
ID=15148102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61135284A Expired - Lifetime JPH07107907B2 (en) | 1986-06-10 | 1986-06-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07107907B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5419666U (en) * | 1977-07-12 | 1979-02-08 | ||
| JPS5858344U (en) * | 1982-08-03 | 1983-04-20 | 富士通株式会社 | semiconductor equipment |
-
1986
- 1986-06-10 JP JP61135284A patent/JPH07107907B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5419666U (en) * | 1977-07-12 | 1979-02-08 | ||
| JPS5858344U (en) * | 1982-08-03 | 1983-04-20 | 富士通株式会社 | semiconductor equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07107907B2 (en) | 1995-11-15 |
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