JPS6241433B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor with improved output characteristics, and specifically to a flip-chip type high power field effect transistor (hereinafter referred to as F-GaAs).

First, the structure of a conventional F-GaAsFET will be briefly explained. Figure 1a shows the surface structure of a conventional GaAsFET chip. A GaAs wafer 1 on which an n-type epitaxial layer is grown on a semi-insulating substrate is covered with a source electrode 2 and a drain made of an ohmic metal such as AuGeNi. An electrode 3 and a gate electrode 4 made of a shot metal such as Al are formed. A portion of the source electrode 2, drain electrode 3, and gate electrode 4 is plated with Au or the like to a thickness of several tens of micrometers, and bonding pads 22, 33, and
Form 44. formed in this way
A GaAsFET chip is placed in a so-called flip-chip structure with its surface facing down, and as shown in the cross-sectional view of FIG. Formed dielectric substrate 6
A high-output F-GaAs FET is created by thermocompression bonding to a package mount made of .

Although the conventional F-GaAs FET having such a structure is an internal matching type and can bring out excellent characteristics at high frequencies, it has the following drawbacks.

That is, in FIG. 1a, the width w of the source electrode 2 of the chip is set to
It is necessary to make it less than 300μm, so the first
The width W of the convex portion 55 of the heat sink 5 of the package mount shown in FIG. b must be made as short as w. Otherwise, the chip width a in FIG. 1a will be unnecessarily increased, the areas of the drain electrode 3 and gate electrode 4 will be increased, the number of parasitic elements will increase, and the high frequency characteristics will deteriorate.
However, it is difficult to shorten the width W of the convex portion 55 of the heat sink 5 of the package mount due to the manufacturing process. Further, the width W of the convex portion 55 may be smaller than the height H, and the thermal resistance of that portion increases, resulting in a loss of high output characteristics.

This invention was made to eliminate the above-mentioned drawbacks, and provides an element structure that can improve output characteristics without impairing high frequency characteristics.
The present invention will be explained below with reference to the drawings.

Figure 2 shows the structure of the F-GaAsFET according to the present invention, and Figure 2a shows the surface structure of the chip.
FIG. 2b shows a cross-sectional structure in which the chip is crimped onto the package mount. In Figure 2 a, semi-insulating
On a GaAs wafer 1 on which an n-type epitaxial layer is grown on a GaAs substrate, a source electrode 2, a drain electrode 3 and
A gate electrode 4 made of a solid metal such as Al is formed. A portion of the source electrode 2, drain electrode 3, and gate electrode 4 is plated with Au or the like to a thickness of several tens of micrometers to form bonding pads 22, 33, and 44 for each electrode. Furthermore, in a part of this drain electrode 3 and gate electrode 4,
A dielectric material 7 such as BaTiO ₃ and a conductive metal such as Au are successively deposited by sputtering, and then a metal layer 3 is formed on the Au metal to a thickness of several tens of μm by Au plating or the like.
Form 7,47. formed in this way
Place the GaAsFET chip with its surface facing down and use a flip-chip type device as shown in the cross-sectional view in Figure 2.
An F-GaAs FET is obtained by thermocompression bonding to a package mount consisting of a Au-plated Cu heat sink 5 and a dielectric substrate 6 whose lower surface is metallized and whose upper surface has an electrode pattern for bonding.

According to the above-described F-GaAsFET according to the present invention, a capacitance is actively formed by the dielectric 7 shown in FIG. It provides a kind of internal consistency that is advantageous. This capacitance can be selected to any design value depending on the type and thickness of the dielectric 7. Furthermore, as shown in FIG. 2b, the width w of the source electrode of the chip can be made smaller than the width W of the convex portion 55 of the heat sink 5, making it possible to improve the high frequency characteristics of the chip. Conversely, since the width W can be increased,
Depending on the ratio of the height H of the convex portion 55, the thermal resistance of that portion can be lowered, making it possible to further improve high output characteristics.

Note that the above embodiment is a flip-chip type high output
Although the explanation was given using a GaAsFET, its application can also be extended to monolithic ICs with further advanced internal matching.

As explained in detail above, the present invention provides a dielectric material with a metal layer formed on the surface of a part of the drain electrode and a gate electrode, respectively, and connects the metal layer of these dielectric materials and the source electrode to the source electrode. The high-frequency characteristics are internally matched by the drain electrode and gate electrode, the dielectric material formed on a part of the surface of the drain electrode and gate electrode, and the metal layer on the dielectric material, which is crimped onto the convex part of the wider heat sink. Since the capacitance for the heat sink is configured, the width of the convex portion of the heat sink can be increased, which has the advantage that high output can be obtained, especially at high frequencies.

[Brief explanation of the drawing]

Figures 1a and b are a plan view of a conventional flip-chip type high-power GaAsFET chip and a sectional view showing the chip crimped to a package mount, and Figures 2a and b are flip-chip type high-power GaAsFETs according to the present invention. FIG. 3 is a plan view of the chip and a cross-sectional view showing the state in which the chip is crimped onto a package mount. In the figure, 1 is a GaAs wafer, 2, 3, and 4 are source, drain, and gate electrodes, 22, 33, and 44 are its bonding pads, and 5 is a heat sink.
Reference numeral 55 indicates the convex portion, 6 indicates a dielectric substrate, 7 indicates a dielectric formed by vapor deposition, and 37 and 47 indicate metal layers which are bonding pad portions of the dielectric. In addition,
The same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a flip-chip type GaAs field effect transistor in which the source electrode is used as a heat sink and the drain electrode and gate electrode are bonded directly and coplanarly to an electrode pattern on a dielectric substrate, the surfaces of the drain electrode and gate electrode are A dielectric material having a metal layer formed on the surface thereof is provided in a part, and the metal layer of each dielectric material and the source electrode are crimped to a convex portion of the heat sink that is larger than the width of the source electrode, and the drain electrode and The gate electrode, the drain electrode, the dielectric formed on a part of the surface of the gate electrode, and the metal layer on the dielectric constitute a capacitor for internal matching of high frequency characteristics. High power GaAs field effect transistor.