JPS6245475Y2 - - Google Patents

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Publication number
JPS6245475Y2
JPS6245475Y2 JP1980177737U JP17773780U JPS6245475Y2 JP S6245475 Y2 JPS6245475 Y2 JP S6245475Y2 JP 1980177737 U JP1980177737 U JP 1980177737U JP 17773780 U JP17773780 U JP 17773780U JP S6245475 Y2 JPS6245475 Y2 JP S6245475Y2
Authority
JP
Japan
Prior art keywords
load
control element
abnormality detection
power supply
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1980177737U
Other languages
Japanese (ja)
Other versions
JPS57101534U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1980177737U priority Critical patent/JPS6245475Y2/ja
Publication of JPS57101534U publication Critical patent/JPS57101534U/ja
Application granted granted Critical
Publication of JPS6245475Y2 publication Critical patent/JPS6245475Y2/ja
Expired legal-status Critical Current

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  • Emergency Protection Circuit Devices (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Power Conversion In General (AREA)

Description

【考案の詳細な説明】 この考案は、負荷の動作状態に応じてその電源
供給路を開閉制御する電源制御回路に関するもの
である。
[Detailed Description of the Invention] This invention relates to a power supply control circuit that controls opening and closing of a power supply path according to the operating state of a load.

従来この種の装置として第1図に示すものがあ
つた。図において、1は電源スイツチ、2は回路
を保護するヒユーズ、3は異常検出信号により
ONとなりヒユーズ2を溶断し負荷5への電源供
給を止めるためのNPNトランジスタ、4はトラ
ンジスタ3を制御する記憶回路、6は負荷異常検
出回路、7は記憶回路4との接続のためのゲート
回路である。
A conventional device of this type is shown in FIG. In the figure, 1 is the power switch, 2 is the fuse that protects the circuit, and 3 is the abnormality detection signal.
NPN transistor turns on and blows fuse 2 to stop power supply to load 5; 4 is a memory circuit that controls transistor 3; 6 is a load abnormality detection circuit; 7 is a gate circuit for connection with memory circuit 4. It is.

次に動作について説明する。 Next, the operation will be explained.

電源スイツチ1を投入しても回路に異常がなけ
れば負荷異常検出回路6からの検出信号は出力さ
れず、記憶回路4の出力はOVを維持し、電源は
負荷5及び負荷異常検出回路6に供給され続け
る。
Even if the power switch 1 is turned on, if there is no abnormality in the circuit, the detection signal from the load abnormality detection circuit 6 will not be output, the output of the memory circuit 4 will maintain OV, and the power will be supplied to the load 5 and the load abnormality detection circuit 6. continue to be supplied.

次に、負荷に異常が発生すると、負荷異常検出
回路6からの検出信号はゲート回路7を通して記
憶回路4に与えられ、記憶回路4の出力はNPN
トランジスタ3をONにさせるに十分な正電圧を
出す。このことによりヒユーズ2の定格電流を越
える電流が流れ、ヒユーズ2を強制的に溶断し、
負荷への電源供給は断たれ、負荷5が破壊するこ
とを防いでいる。
Next, when an abnormality occurs in the load, the detection signal from the load abnormality detection circuit 6 is given to the memory circuit 4 through the gate circuit 7, and the output of the memory circuit 4 is NPN.
Generates enough positive voltage to turn on transistor 3. As a result, a current exceeding the rated current of fuse 2 flows, forcibly blowing fuse 2,
The power supply to the load is cut off to prevent the load 5 from being destroyed.

従来の電源制御回路は以上の様に構成されてい
るので、ヒユーズ2を溶断するに十分な電流が流
せ得る大電力用トランジスタ3が必要である。ヒ
ユーズ記憶回路4、ゲート回路7が必要である。
等回路が複雑となり、コストが高くつく、ヒユー
ズ2を交換する必要がある等の欠点があつた。
Since the conventional power supply control circuit is configured as described above, a high power transistor 3 is required that can flow a current sufficient to blow the fuse 2. A fuse memory circuit 4 and a gate circuit 7 are required.
There were disadvantages such as the circuit was complicated, the cost was high, and the fuse 2 had to be replaced.

また、負荷異常検出回路6が故障した場合、負
荷5に異常があつても異常検出信号が出力されな
ので、負荷5が破壊されると云う欠点もあつた。
Furthermore, if the load abnormality detection circuit 6 fails, an abnormality detection signal is output even if there is an abnormality in the load 5, so there is a drawback that the load 5 may be destroyed.

この考案は上記のような従来のものの欠点を除
去するためになされたもので、負荷の電源供給路
に開閉素子を設け、この開閉素子を負荷の動作状
態に応じて制御することにより、簡単かつ安価に
負荷を確実に保護することができ、またその保守
も容易に行なえる電流制御回路を提供することを
目的としている。
This idea was made in order to eliminate the drawbacks of the conventional ones as described above, and by providing a switching element in the power supply path of the load and controlling this switching element according to the operating state of the load, it is easy and simple. It is an object of the present invention to provide a current control circuit that can reliably protect a load at low cost and that can be easily maintained.

以下、この考案の一実施例を図について説明す
る。第2図において、8はリレー駆動用PNPトラ
ンジスタ、9はリレー駆動用PNPトランジスタ8
のON/OFFを制御するNPNトランジスタ、11
は電源スイツチ1をON→OFFにした場合コンデ
ンサ10を早く放電させる為のダイオード12は
コンデンサ15と共にあつてPNPトランジスタ9
のベースにパルス状正電圧を供給する抵抗、14
は電源スイツチ1をON→OFFにした場合コンデ
ンサ15を早く放電させる為の抵抗、17は抵抗
13と共にあつて負荷異常検出回路6の信号を一
つの方向に流させ、電源スイツチ1投入時、コン
デンサ15によつて発生されたパルス状正電圧が
負荷異常検出回路6に流れ込むことを防ぐダイオ
ードである。
An embodiment of this invention will be described below with reference to the drawings. In Fig. 2, 8 is a relay driving PNP transistor, 9 is a relay driving PNP transistor 8
NPN transistor that controls ON/OFF of 11
In order to quickly discharge the capacitor 10 when the power switch 1 is turned from ON to OFF, the diode 12 is located together with the capacitor 15, and the PNP transistor 9
a resistor for supplying a pulsed positive voltage to the base of 14;
is a resistor to quickly discharge the capacitor 15 when the power switch 1 is turned from ON to OFF, and 17 is installed together with the resistor 13 to allow the signal of the load abnormality detection circuit 6 to flow in one direction. This diode prevents the pulsed positive voltage generated by the load abnormality detection circuit 6 from flowing into the load abnormality detection circuit 6.

上記これら符号8〜17により制御回路20が
構成されている。
The control circuit 20 is composed of the above-mentioned numerals 8 to 17.

18は負荷5への電源の供給のON,OFFを行
うリレーで、18aはその励磁用コイルであり、
18bはそのリレー接点である。なお、この第2
図において符号1,5,6は第1図の同符号のも
のに相当するものであるが、この場合の負荷異常
検出回路3は負荷5が正常時所定電圧(たとえ
ば″1″出力)を出力し、異常時はその出力が零
となるよう構成されている。
18 is a relay that turns on and off the supply of power to the load 5, and 18a is its excitation coil;
18b is its relay contact. Note that this second
In the figure, numerals 1, 5, and 6 correspond to the same numerals in Fig. 1, and the load abnormality detection circuit 3 in this case outputs a predetermined voltage (for example, "1" output) when the load 5 is normal. However, the output is configured to be zero in the event of an abnormality.

第2図において、電源スイツチ1を投入すると
コンデンサ15、抵抗13に依つて決定される時
定数である時間パルス状の正電圧がNPNトラン
ジスタ9のベースに印加され、NPNトランジス
タ9がこの時定数の期間一時的にONとなる。こ
の為PNPトランジスタ8はONとなり、励磁コイ
ル18aに電流が流れ、その接点18bが閉じて
負荷5に電流が供給される。一方PNPトランジス
タ8の出力電圧はコンデンサ10、抵抗12に依
つて決定される時定数で或る時間、パルス状の正
電圧が再びNPNトランジスタ9のベースに印加
されると言う具合に閉ループを描いて正電圧を加
えることにより非常に安定に或る時間の間負荷5
に電源を供給することができる。
In FIG. 2, when the power switch 1 is turned on, a time-pulsed positive voltage with a time constant determined by the capacitor 15 and the resistor 13 is applied to the base of the NPN transistor 9. It will be ON temporarily for a period of time. For this reason, the PNP transistor 8 is turned on, current flows through the excitation coil 18a, and its contact 18b closes to supply current to the load 5. On the other hand, the output voltage of the PNP transistor 8 is determined by the capacitor 10 and the resistor 12 for a certain period of time, and a pulsed positive voltage is again applied to the base of the NPN transistor 9, forming a closed loop. load 5 for a period of time very stably by applying a positive voltage.
can supply power to.

このある一定時間内の電源供給を行つている間
に負荷が正常であれば正の電圧を出力する。この
ことによりNPNトランジスタ9をONにさせ、
PNPトランジスタ8をONにしリレー18をONと
し、電源の供給が連続して行われる様になる。
If the load is normal while power is being supplied within this certain period of time, a positive voltage is output. This turns on the NPN transistor 9,
By turning on the PNP transistor 8 and turning on the relay 18, power is continuously supplied.

負荷異常検出回路6が負荷5が異常と判断した
場合、その出力はOvとなる為NPNトランジスタ
9がOFFとなり、PNPトランジスタ8をOFFと
しリレー18をOFFとさせ電源の供給が断たれ
る。
When the load abnormality detection circuit 6 determines that the load 5 is abnormal, its output becomes Ov, so the NPN transistor 9 is turned off, the PNP transistor 8 is turned off, the relay 18 is turned off, and the power supply is cut off.

なお、抵抗14は電源スイツチ1をON→OFF
にもどした場合コンデンサ15を早く放電させる
為の抵抗である。又、ダイオード11についても
電流スイツチ1をON→OFFにもどした場合コン
デンサ10を早く放電させる為のものである。
In addition, resistor 14 turns power switch 1 from ON to OFF.
This resistor is used to quickly discharge the capacitor 15 when the capacitor 15 is returned to its normal state. The diode 11 is also used to quickly discharge the capacitor 10 when the current switch 1 is turned back from ON to OFF.

なお、上記実施例では負荷5の電源供給路を開
閉する開閉素子としてリレー18を用いて説明し
たが、トランジスタ,サイリスタ等の制御素子を
用いても同様の効果を奏する。
Although the above embodiment has been described using the relay 18 as the switching element for opening and closing the power supply path of the load 5, the same effect can be obtained by using a control element such as a transistor or a thyristor.

以上の様にこの考案によれば負荷の電源供給時
に開閉素子を設け、この開閉素子を負荷の状態に
応じて制御すると共に、その制御ループの中に負
荷異常検出回路の自己チエツク機能を含ませるよ
うにしたので、負荷を確実に保護することができ
またその保守、復帰動作が容易に行なえると云う
効果がある。
As described above, according to this invention, a switching element is provided when power is supplied to the load, and this switching element is controlled according to the load condition, and the self-check function of the load abnormality detection circuit is included in the control loop. As a result, the load can be reliably protected and its maintenance and restoration operations can be easily performed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電源制御回路を示すブロツク図
第2図はこの考案の一実施例による電源制御回路
を示す接続図である。 図中、5は負荷、6は負荷異常検出回路、18
は開閉素子、20は制御回路である。なお、図
中、同一符号は同一又は相当部分を示す。
FIG. 1 is a block diagram showing a conventional power supply control circuit, and FIG. 2 is a connection diagram showing a power supply control circuit according to an embodiment of the present invention. In the figure, 5 is the load, 6 is the load abnormality detection circuit, and 18
2 is a switching element, and 20 is a control circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 負荷の電源供給路に直列接続され、その供給路
を開閉する開閉素子、この開閉素子を開閉制御す
る制御素子、上記負荷の動作状態を検出し、その
状態に応じて正常/異常信号を出力する負荷異常
検出回路、上記負荷に電源供給開始後の所定時間
の間、上記制御素子に上記負荷が正常時上記負荷
異常検出回路から出力される正常信号と同極性の
充電電流を供給する第1の充電路と、この充電電
流により駆動される上記制御素子の出力電圧によ
り充電され、この充電電流を再度上記制御素子に
供給する第2の充電路を形成して上記制御素子に
起動信号を入力すると共に、その後上記負荷異常
検出回路から出力される正常/異常信号に応じて
上記制御素子を駆動制御する制御回路を備えたこ
とを特徴とする電源制御回路。
A switching element that is connected in series to the power supply path of the load and opens and closes the supply path, a control element that controls the opening and closing of this switching element, and a control element that detects the operating state of the load and outputs a normal/abnormal signal depending on the state. a load abnormality detection circuit, a first supplying a charging current having the same polarity as a normal signal outputted from the load abnormality detection circuit when the load is normal to the control element for a predetermined time after power supply to the load is started; A charging path and a second charging path that is charged by the output voltage of the control element driven by the charging current and that supplies this charging current to the control element again are formed to input a start signal to the control element. A power supply control circuit further comprising: a control circuit for driving and controlling the control element according to a normal/abnormal signal subsequently output from the load abnormality detection circuit.
JP1980177737U 1980-12-10 1980-12-10 Expired JPS6245475Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1980177737U JPS6245475Y2 (en) 1980-12-10 1980-12-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1980177737U JPS6245475Y2 (en) 1980-12-10 1980-12-10

Publications (2)

Publication Number Publication Date
JPS57101534U JPS57101534U (en) 1982-06-22
JPS6245475Y2 true JPS6245475Y2 (en) 1987-12-04

Family

ID=29971891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1980177737U Expired JPS6245475Y2 (en) 1980-12-10 1980-12-10

Country Status (1)

Country Link
JP (1) JPS6245475Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014073045A (en) * 2012-10-01 2014-04-21 Toyota Motor Corp Switching circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591134A (en) * 1978-12-28 1980-07-10 Mitsubishi Electric Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591134A (en) * 1978-12-28 1980-07-10 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPS57101534U (en) 1982-06-22

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