JPS6217394B2 - - Google Patents
Info
- Publication number
- JPS6217394B2 JPS6217394B2 JP5993779A JP5993779A JPS6217394B2 JP S6217394 B2 JPS6217394 B2 JP S6217394B2 JP 5993779 A JP5993779 A JP 5993779A JP 5993779 A JP5993779 A JP 5993779A JP S6217394 B2 JPS6217394 B2 JP S6217394B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- electrodes
- drain
- mounting
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 18
- 238000000605 extraction Methods 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
Description
【発明の詳細な説明】
本発明は電界効果トランジスタのマウント方
法、特に素子をアツプサイドダウンにマウントす
る方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of mounting a field effect transistor, and more particularly to a method of mounting the device upside down.
GaAsシヨツトキー障壁ゲート型電界効果トラ
ンジスタ（GaAs MESFET）等の高周波電界効
果トランジスタは最大動作周波数として50GHz
以上が得られることが理論的に知られている。し
かしながら実際にこのような高周波動作を実現す
ることは容易ではなく、その原因の１つとして、
素子をヒートシンクおよび外部回路にマウントす
る際に生じる寄生要素（寄生インダクタンス、寄
生キヤパシタンス）の影響が考えられる。 High frequency field effect transistors such as GaAs Schottky barrier gate field effect transistors (GaAs MESFETs) have a maximum operating frequency of 50 GHz.
It is theoretically known that the above can be obtained. However, it is not easy to actually achieve such high frequency operation, and one of the reasons for this is that
The influence of parasitic elements (parasitic inductance, parasitic capacitance) that occur when mounting the device on a heat sink and external circuit is considered.
従つて、素子をどのようにしてマウントするか
は素子技術、回路技術において重要な課題であ
り、従来から種々の工夫がなされている。第１図
はソースインダクタンス、ゲート寄生キヤパシタ
ンスを低減せしめ、さらに熱抵抗をも低減せしめ
るマウント方法の１例を示す。図において、先ず
素子FETは第１図Ａ，Ｂに示すごとく、高抵抗
性基板１０上に形成された半導体動作層１１上に
ソース電極１２、ゲート電極１３、ドレイン電極
１４が設けられ、ソース電極１２、およびゲー
ト、ドレインリード引出し用電極１３１，１４１
上に厚メツキ１２２，１３２，１４２が各々施さ
れている。素子は同図Ｃに示すごとく、ヒートシ
ンク１５、セラミツク１６上の電極１７，１８上
に熱圧着により、アツプサイドダウンにマウント
されている。 Therefore, how to mount an element is an important issue in element technology and circuit technology, and various efforts have been made in the past. FIG. 1 shows an example of a mounting method that reduces source inductance, gate parasitic capacitance, and also reduces thermal resistance. In the figure, as shown in FIGS. 1A and 1B, the FET element is first provided with a source electrode 12, a gate electrode 13, and a drain electrode 14 on a semiconductor active layer 11 formed on a high-resistance substrate 10. 12, and gate and drain lead extraction electrodes 131, 141
Thick plating 122, 132, and 142 are applied on top, respectively. As shown in Figure C, the element is mounted upside down on a heat sink 15 and electrodes 17 and 18 on a ceramic 16 by thermocompression bonding.
しかしながら上記のマウント方法においてソー
ス１２２、ゲート１３２、ドレイン１４２が全て
完全に熱圧着されるためにはヒートシンク１５の
表面とセラミツク上の電極１７，１８の表面の高
さが±20μｍ以内精度で同一になつていることが
必要であり、チツプキヤリア、あるいはパツケー
ジの値段は極めて高価になるので実用的なマウン
ト方法とはいえない。 However, in the above mounting method, in order for the source 122, gate 132, and drain 142 to be completely bonded by thermocompression, the heights of the surface of the heat sink 15 and the surfaces of the electrodes 17 and 18 on the ceramic must be the same with an accuracy of ±20 μm. It is not a practical mounting method because the chip carrier or package cage is extremely expensive.
別のマウント方法として、ソース１２，１２
２、およびゲート、ドレインリード引出し用電極
１３１，１３２，１４１，１４２を半田を用いた
ソルダによつて固着する方法もあるが、半田の厚
みは数十μｍであるためにソース電極１２，１２
２をソルダーする際半田が半導体動作層１１の表
面に付着し、該動作上のゲート、ドレイン電極１
３，１４と接触したり、あるいは、ゲートドレイ
ン電極１３，１４が絶縁膜で覆われている場合に
は該電極との間の寄生キヤパシタンスが増大する
等の欠点がある。 As another mounting method, source 12,12
There is also a method of fixing the gate and drain lead lead electrodes 131, 132, 141, 142 with solder, but since the thickness of the solder is several tens of μm, the source electrodes 12, 12
2, solder adheres to the surface of the semiconductor operating layer 11, and the gate and drain electrodes 1 on the operating layer 11 are soldered.
3 and 14, or when the gate and drain electrodes 13 and 14 are covered with an insulating film, there are disadvantages such as an increase in parasitic capacitance between the gate and drain electrodes 13 and 14.
本発明は従来の方法における上述の不都合を取
り除き、アツプサイドダウンにマウントできる新
しい電界効果トランジスタのマウント方法を提供
するものである。 The present invention eliminates the above-mentioned disadvantages of the conventional methods and provides a new mounting method for field effect transistors that allows for upside-down mounting.
本発明によれば、第１図Ａ，Ｂに於て説明した
ごとく、半絶縁性基板上の半導体動作層上にソー
ス、ドレイン、ゲートの各電極、更に該半導体動
作層以外の半絶縁性基板表面にゲート、ドレイン
リード引出し用電極を有し、かつ前記ソース電極
およびゲート、ドレインリード引出し用電極以外
の領域が絶縁膜で覆われており、少なくとも前記
ソース電極部分に金の厚めつきが施されてなる電
界効果トランジスタのマウント方法に於て、前記
ソース電極を熱圧着法によりヒートシンクに、か
つゲート、ドレインリード引出し用電極をソルダ
により誘電体上の電極に各々固着せめることを特
徴とする電界効果トランジスタのマウント方法が
得られる。 According to the present invention, as explained in FIGS. 1A and 1B, the source, drain, and gate electrodes are formed on the semiconductor active layer on the semi-insulating substrate, and the semi-insulating substrate other than the semiconductor active layer is formed. It has a gate and a drain lead extraction electrode on its surface, and a region other than the source electrode and the gate and drain lead extraction electrode is covered with an insulating film, and at least the source electrode portion is coated with thick gold. A method for mounting a field effect transistor, characterized in that the source electrode is fixed to a heat sink by thermocompression bonding, and the gate and drain lead extraction electrodes are fixed to electrodes on a dielectric material by solder. A method for mounting a transistor is obtained.
本発明によるマウント方法に於ては、(1)ソース
電極は熱圧着によつて固着されるので前述のごと
く、動作層表面及び動作層表面のソース、ドレイ
ン電極に半田が付着することがない。(2)ゲート、
ドレインゲート引出し用電極はソルダーにより固
着されるのでヒートシンクの表面と誘電体上の電
極の平坦性に対する条件も緩やかになる。(3)ゲー
ト、ドレイン引出し電極は周囲を絶縁膜で囲まれ
ているため半田がソース電極まで到達することも
なく、再現性良くマウントすることが可能である
等の効果、利点が有る。 In the mounting method according to the present invention, (1) the source electrode is fixed by thermocompression bonding, so that solder does not adhere to the surface of the active layer and the source and drain electrodes on the surface of the active layer, as described above. (2) Gate;
Since the drain gate lead-out electrode is fixed by solder, the conditions for flatness of the electrode on the surface of the heat sink and the dielectric are also relaxed. (3) Since the gate and drain lead electrodes are surrounded by an insulating film, solder does not reach the source electrode, and there are advantages such as the possibility of mounting with good reproducibility.
以下図により本発明の実施例を説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第２図は、本発明による電界効果トランジスタ
のマウント方法の一実施例を説明するための図で
あり、同図Ａは本発明によるマウント法に適した
チツプキヤリアの例、Ｂはチツプをチツプキヤリ
アにマウントした状態、Ｃはヒートシンク上の動
作層のある部分をＢと直角方向に切つた断面図で
ある。まずチツプキヤリアは基本的には通常のも
のと同様な形状であるがヒートシンク上のスタツ
ド１５の大きさは素子FETの動作層の大きさと
同等であることが好ましく、かつ入出力電力１
７，１８の間隔はFETチツプ上のゲート、ドレ
インリード引出し用電極１３１，１４１の間隔
（例えば800μｍ）と同等であることが望ましい。
またスタツド１５の高さは、図Ｂに示すごとく、
入出力電極１７，１８の高さよりも20μｍ〜100
μｍ高い方が好ましい。素子のマウントに当つて
はまず入出力電極１７，１８の先端に例えば
AuSn合金の半田を乗せ溶融させる。半田の量
は、入出力電極１７，１８とゲート、ドレインリ
ード引出し用電極１３１，１４１の間隔、あるい
は引出し用電極の面積等により適当に調整すれば
よいが通常は0.3mm×0.3mm×0.1mm位が適当であ
る。次にチツプを図Ｂのごとくアツプサイドダウ
ンにマウントする。このときソース電極１２２は
スタツド１５に熱圧着法（温度は例えば370℃）
により固着され、ゲート、ドレイン引出し電極は
先の半田２１によりソルダされる。図Ｂ，Ｃにお
いて２２は例えばSiO2等の絶縁膜である。な
お、第２図においてはソース電極、ゲートドレイ
ンリード引出し電極とも厚めつき（例えば20μｍ
厚）が施されているが、厚めつきは熱圧着法で固
着される部分、即ちソース電極にのみ施されてい
てもよい。 FIG. 2 is a diagram for explaining one embodiment of the method for mounting a field effect transistor according to the present invention, in which A is an example of a chip carrier suitable for the mounting method according to the present invention, and B is a diagram for mounting a chip on the chip carrier. In this state, C is a cross-sectional view of a portion of the active layer on the heat sink taken in a direction perpendicular to B. First, the chip carrier basically has the same shape as a normal chip carrier, but it is preferable that the size of the stud 15 on the heat sink is equal to the size of the active layer of the element FET, and the input/output power is 1.
It is desirable that the spacing between the electrodes 7 and 18 be equal to the spacing between the gate and drain lead lead electrodes 131 and 141 on the FET chip (for example, 800 μm).
The height of the stud 15 is as shown in Figure B.
20 μm to 100 mm higher than the height of input/output electrodes 17 and 18
The higher the value by μm, the better. When mounting the device, first attach the tips of the input/output electrodes 17 and 18, for example.
Place AuSn alloy solder on it and melt it. The amount of solder may be adjusted appropriately depending on the distance between the input/output electrodes 17 and 18 and the gate and drain lead extraction electrodes 131 and 141, or the area of the extraction electrode, but it is usually 0.3 mm x 0.3 mm x 0.1 mm. The position is appropriate. Next, mount the chip upside down as shown in Figure B. At this time, the source electrode 122 is bonded to the stud 15 by thermocompression (temperature is, for example, 370°C).
The gate and drain lead electrodes are soldered with the solder 21 previously used. In FIGS. B and C, 22 is an insulating film made of, for example, SiO 2 . In addition, in Figure 2, both the source electrode and gate drain lead extraction electrode are thick (for example, 20 μm).
However, the thickening may be applied only to the portion to be fixed by thermocompression bonding, that is, the source electrode.
なお本発明によるマウント方法によれば、前述
のごとく、寄生インダクタンス、寄生キヤパシタ
ンスあるいは熱抵抗が低減されたアツプサイドダ
ウンによる素子マウントを容易に達成することが
でき、しかもチツプキヤリア、パツケージ等の寸
法精度も従来要求された程厳しくない。 According to the mounting method of the present invention, as described above, it is possible to easily achieve upside-down element mounting with reduced parasitic inductance, parasitic capacitance, or thermal resistance, and also to improve the dimensional accuracy of chip carriers, packages, etc. Not as strict as previously required.
第１図は従来の素子マウント方法（アツプサイ
ドダウン）を説明するための図であり、同図Ａ，
ＢはFETチツプ断面図、Ｃは熱圧着によりアツ
プサイドダウンにマウントされた状態を示す、第
２図は本発明の実施例を説明するための図であ
り、Ａはチツプキヤリア、Ｂ，ＣはFETがアツ
プサイドダウンにマウントされた状態を示す図で
ある。
図に於て、１０：半絶縁性基板、１１：半導体
動作層、１２：ソース電極、１３：ゲート電極、
１４：ドレイン電極、１３１，１４１：リード引
出し用電極、１２２，１３２，１４２：厚めつき
層、１５：ヒートシンク（スタツド）、１６：セ
ラミツク基板、１７，１８：入出力電極、２１：
半田、２２：SiO2膜である。
Figure 1 is a diagram for explaining the conventional device mounting method (upside down).
B is a cross-sectional view of the FET chip, C is a state in which it is mounted upside down by thermocompression bonding, and FIG. 2 is a diagram for explaining an embodiment of the present invention, A is a chip carrier, and B and C are FET chips. FIG. 2 is a diagram showing a state in which the camera is mounted upside down. In the figure, 10: semi-insulating substrate, 11: semiconductor active layer, 12: source electrode, 13: gate electrode,
14: Drain electrode, 131, 141: Lead extraction electrode, 122, 132, 142: Thick layer, 15: Heat sink (stud), 16: Ceramic substrate, 17, 18: Input/output electrode, 21:
Solder, 22: SiO 2 film.
Claims (1)
ス、ドレイン、ゲートの各電極、更に該半導体動
作層以外の半絶縁性基板上にゲート、ドレインリ
ード引出し用電極を有し、かつ前記ソース電極お
よびゲート、ドレインリード引出し用電極以外の
領域が絶縁膜で覆われており、少なくともソース
電極部分に金が厚めつきされてなる電界効果トラ
ンジスタのマウント方法に於て、前記ソース電極
を熱圧着法によりヒートシンクに、かつ前記ゲー
ト、ドレインリード引出し用電極をソルダー法に
より誘電体上の電極に各々固着することを特徴と
する電界効果トランジスタのマウント方法。1. Source, drain, and gate electrodes on the surface of a semiconductor active layer on a semi-insulating substrate, and gate and drain lead extraction electrodes on a semi-insulating substrate other than the semiconductor active layer, and the source electrode and In a mounting method for a field effect transistor in which the regions other than the gate and drain lead extraction electrodes are covered with an insulating film and at least the source electrode portion is thickly coated with gold, the source electrode is attached to a heat sink by thermocompression bonding. A method for mounting a field effect transistor, further comprising fixing the gate and drain lead lead electrodes to electrodes on a dielectric material by a soldering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5993779A JPS55151371A (en) | 1979-05-16 | 1979-05-16 | Mounting method of field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5993779A JPS55151371A (en) | 1979-05-16 | 1979-05-16 | Mounting method of field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55151371A JPS55151371A (en) | 1980-11-25 |
| JPS6217394B2 true JPS6217394B2 (en) | 1987-04-17 |
Family
ID=13127538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5993779A Granted JPS55151371A (en) | 1979-05-16 | 1979-05-16 | Mounting method of field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55151371A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3144377B2 (en) | 1998-03-13 | 2001-03-12 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
1979
- 1979-05-16 JP JP5993779A patent/JPS55151371A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55151371A (en) | 1980-11-25 |
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