JPS59169165A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59169165A
JPS59169165A JP58042211A JP4221183A JPS59169165A JP S59169165 A JPS59169165 A JP S59169165A JP 58042211 A JP58042211 A JP 58042211A JP 4221183 A JP4221183 A JP 4221183A JP S59169165 A JPS59169165 A JP S59169165A
Authority
JP
Japan
Prior art keywords
wire
bonding
semiconductor device
directly above
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58042211A
Other languages
Japanese (ja)
Other versions
JPH0447972B2 (en
Inventor
Susumu Okikawa
進 沖川
Hiromichi Suzuki
博通 鈴木
Wahei Kitamura
北村　和平
Hiroshi Mikino
三木野　博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58042211A priority Critical patent/JPS59169165A/en
Publication of JPS59169165A publication Critical patent/JPS59169165A/en
Publication of JPH0447972B2 publication Critical patent/JPH0447972B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the height of a loop of a wire, to reduce the thickness of a semiconductor device and to decrease the cost by bending the wire directly above the first bonding position of a wire bonding, extending the wire and performing the second bonding. CONSTITUTION:A wire 16 is connected between an electrode pad 15 of an element pellet 14 and a wiring circuit 11 of a printed circuit board 10 to electrically connect the both, and the pellet 14 and the wire 16 are sealed with resin 17. The wire 16 is bent substantially at a right angle at the position directly above the first bonding position B1, and extended to the second bonding position B2 in the extended state, and the second bonding is executed. In this manner, the loop height H2 of the wire can be reduced, and the thickness of the entire semiconductor device can be reduced. The wire 16 is formed of extrafine wires of aluminum alloy, and can be readily bent.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は製品の薄型化とコストの低減を図った半導体装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device that is designed to reduce the thickness and cost of the product.

〔背景技術〕[Background technology]

ＩＣ，ＬＳＩ等の牛導体累子ベレットを実装して半導体
装置を構成する場合には、リードフレームやプリント回
路基板等の装置基板上に素子ペレットを固着した上で、
この素子ペレットと装置基板とをワイヤ接続して電気的
配線を行ない、レジンやキャップ部材にて素子ペレット
な封止する構造が採られつる。例えば、第１図に示すも
のはプリント回路基板１の表面凹部２内に接着剤３を用
いて素子ペレット４を固着し、この素子ペレット４とプ
リント回路基板１の配線回路５とを極細ワイヤ６にて接
続しかつこれらなレジン７にて封止したものである。When constructing a semiconductor device by mounting a conductor pellet such as an IC or LSI, the element pellet is fixed onto a device board such as a lead frame or a printed circuit board, and then
A structure is adopted in which the element pellet and the device substrate are connected by wire for electrical wiring, and the element pellet is sealed with resin or a cap member. For example, in the case shown in FIG. 1, an element pellet 4 is fixed in a recess 2 on the surface of a printed circuit board 1 using an adhesive 3, and this element pellet 4 and a wiring circuit 5 of the printed circuit board 1 are connected using an ultrafine wire 6. and sealed with these resins 7.

ところで、この棹の半導体装置においては、装置の薄型
化が種々工夫されているが、薄型化の障害になっている
のは所謂ループ高さである。即ち。Incidentally, in this type of semiconductor device, various efforts have been made to make the device thinner, but an obstacle to making the device thinner is the so-called loop height. That is.

第１図に示すように、ワイヤ６は素子ペレット４への第
１ボンデイング部位Ｂ、上において若干の高さくループ
高さ）Ｈ２だけ略垂直に延長され、そこから曲げられて
プリント回路基板１の第２ボンデイング部位Ｂ、にまで
ループ状に曲設した構成とされているため、このループ
高さＨ７が装置の厚さを規制することになる。As shown in FIG. 1, the wire 6 is extended approximately vertically by a loop height (loop height) H2 above the first bonding site B to the device pellet 4, and is bent from there to the printed circuit board 1. Since the second bonding portion B is bent in a loop shape, the loop height H7 regulates the thickness of the device.

したがって、このループ高さＨ，を低減するために第１
ポンデイングから第２ボンデイングへのワイヤ張設時に
おけるワイヤ張力を増大することが考えられるが、これ
では第１ボンデイング部位Ｂ、に過大な張力が加わって
ボンディング部位が破壊される危険がある。また、ワイ
ヤ６のループな横方向に形成してルニプ高さを低減する
ことも考えられるが、これでは隣接するワイヤ相互間で
短絡事故が発生するおそれもある。Therefore, in order to reduce this loop height H,
It is conceivable to increase the wire tension when stretching the wire from the bonding part to the second bonding part, but in this case there is a risk that excessive tension will be applied to the first bonding part B and the bonding part will be destroyed. It is also possible to reduce the lunip height by forming the wire 6 in a loop in the horizontal direction, but this may cause a short circuit accident between adjacent wires.

更に、ループ高さＨｌが大ぎいことはそれだけ第１．第
２ボンディング間におけるワイヤ６が長くなることにな
り、ワイヤの使用量が多くなってコスト高にｒｌるう特
に、Ａｕワイヤを使ＭＨる場合には装置が高価なものに
なる。Furthermore, the fact that the loop height Hl is large causes the first problem. The wire 6 between the second bondings becomes longer, and the amount of wire used increases, leading to higher costs. In particular, when MH is performed using Au wires, the device becomes expensive.

〔発明の目的〕[Purpose of the invention]

本発明の目的は所謂ループ高さを低減することにより、
その薄型化を達成することができる半導体装置を提供す
ることにある、 また５本発明の目的はループ高さの低減に伴なってワイ
ヤ長を低減することにより、ワイヤ使用量を低減してコ
ストの低下を図ることができる半導体装置を提供するこ
とにある。The purpose of the present invention is to reduce the so-called loop height.
It is an object of the present invention to provide a semiconductor device that can achieve a reduction in the thickness of the semiconductor device.It is also an object of the present invention to reduce the wire length by reducing the loop height, thereby reducing the amount of wire used and reducing costs. An object of the present invention is to provide a semiconductor device that can reduce the amount of heat generated by the semiconductor device.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、ワイヤボンディングの第１ボンディング部位
の直上でワイヤを曲げ加工し、これを張設して第２ボン
デイングな行なう構成とすることにより、ワイヤのルー
プ高さの低減を図って装ばの薄型化を達成するものであ
る。In other words, by bending the wire directly above the first bonding part and stretching it for second bonding, the height of the wire loop can be reduced and the mounting can be made thinner. The goal is to achieve the following.

〔実施例〕〔Example〕

第２図は本発明の一実施例を示しており、表面に所定の
配線回路１１を形成したプリント回路基・板１０の表面
一部に方形の四部１２を形成し、この凹部１２内に接着
剤１３な用いて半導体素子ペレット１４を固着している
。そして、この素子ペレット１４の電極パッド１５と前
記配線回路１１との間にワイヤ１６を接続して両者な電
気的に接続し、その上でレジン１７を用いてペレット１
４゜ワイヤ１６を封止している。FIG. 2 shows an embodiment of the present invention, in which four rectangular parts 12 are formed on a part of the surface of a printed circuit board/board 10 on which a predetermined wiring circuit 11 is formed, and adhesive is glued into the recessed part 12. A semiconductor element pellet 14 is fixed using an agent 13. Then, a wire 16 is connected between the electrode pad 15 of this element pellet 14 and the wiring circuit 11 to electrically connect them, and then a resin 17 is used to connect the wire 16 to the wiring circuit 11.
4° wire 16 is sealed.

前記ワイヤ１６はＡｋに所要の金属な混合したＡ４合金
の極細線からなり、第１ボンディング部位Ｂ１はＡｋボ
ールを形成してこれをＩＩＩ！Ｉ！！パッド１５に超音
波熱圧着し、第２ボンディング部位Ｂ２はワイヤ１６の
一部を配線回路１１に超音波熱圧着している。そして、
第１ボンディング部位Ｂ１の直上箇所でワイヤ１６を略
直角に曲げ加工し、その上でこれを張設状態で第２ボン
デイング部位Ｂ、にまで延設して第２ボンデイングを行
なっている。この結果、ワイヤ１６は第１ボンディング
部位Ｂ１の上方に延長されることはない。The wire 16 is made of an ultra-fine wire of A4 alloy mixed with Ak and the necessary metals, and the first bonding portion B1 forms an Ak ball and is bonded to III! I! ! The pad 15 is bonded by ultrasonic thermocompression, and a part of the wire 16 is bonded to the wiring circuit 11 by ultrasonic thermocompression at the second bonding portion B2. and,
The wire 16 is bent at a substantially right angle at a location directly above the first bonding location B1, and is then stretched in a stretched state to the second bonding location B to perform second bonding. As a result, the wire 16 is not extended above the first bonding portion B1.

第２図は前記したワイヤボンディングを行なうためのワ
イヤボンダ２０を示す、このワイヤボンダ２０は、ＸＹ
テーブル２１上に搭載したボンディングヘッド２２から
ボンディングアーム２３を突設し、先端にキャピラリ２
４を固設すると共に、このアーム２３をカム機構２５に
よって上下に揺動できるようにしている、また、前記ア
ーム２３の上部にはクラ７パ２６乞設げ、図外のプーリ
から引き出されて前記キャピラリ２４を挿通されるＡｎ
ワイヤ１６の一部をクランプできる。FIG. 2 shows a wire bonder 20 for performing the wire bonding described above.
A bonding arm 23 is provided protruding from a bonding head 22 mounted on a table 21, and a capillary 2 is attached to the tip.
4 is fixedly installed, and the arm 23 is made to be able to swing up and down by a cam mechanism 25. Also, a clamp 7 pa 26 is provided at the upper part of the arm 23, and the arm 23 is pulled out from a pulley (not shown). An inserted through the capillary 24
A portion of the wire 16 can be clamped.

一方、前記キャピラリ２４０下方位置にはボンディング
ステージ２７を配設し、被ボンデイング物である半導体
装置を載置している。また、このボンディングステージ
２７の上部位置には、揺動アーム２８によって前記キャ
ピラリ２４の下側に進退可能な可動電極２９を設け、前
記キャピラリ２４或いはワイヤ１６と可動電極２９との
間に高電流を印加し得るようになっている。On the other hand, a bonding stage 27 is disposed below the capillary 240, and a semiconductor device to be bonded is mounted thereon. Further, a movable electrode 29 is provided at the upper part of the bonding stage 27 and can be moved forward and backward under the capillary 24 by a swing arm 28, and a high current is applied between the capillary 24 or the wire 16 and the movable electrode 29. It can be applied.

したがって、このワイヤボンダ２ｏを使用すれば、キャ
ピラリ２４の下側に可動電極２９を位置させてこれをキ
ャピラリ２４を挿通させたＡｎワイヤ１６の先端に対向
させ５両者間に高電流を通じて放電を発生させることに
より、放電エネルギによってＡｌワイヤ１６の先端にＡ
６ボールを形成できる。そして、このＡ、Ａボールを電
極パッド１５に超音波熱圧着すれば第１ボンデイングが
完了される。このとぎ、口Ｊ動ｉｔｌ！ｌ！！２９は退
避される。Therefore, if this wire bonder 2o is used, the movable electrode 29 is positioned below the capillary 24, and this is opposed to the tip of the An wire 16 through which the capillary 24 is inserted, and a high current is passed between the two to generate a discharge. As a result, A is generated at the tip of the Al wire 16 due to the discharge energy.
Can form 6 balls. Then, by ultrasonic thermocompression bonding these A and A balls to the electrode pad 15, the first bonding is completed. At this moment, it's a mouthful! l! ! 29 is evacuated.

第１ボンデイングの完ｒ後に、ＸＹテーブル２１とカム
機構２５０作用によってキャピラリ２４を殆んど上動さ
せろことなく横方向へ移動させる。After the first bonding is completed, the capillary 24 is moved laterally by the action of the XY table 21 and the cam mechanism 250 with almost no upward movement.

これにより、ワイヤ１６は第１ボンデイング部位Ｂ、の
直上で曲げ加工される。この場合、Ａ召ワイヤ１６はＡ
召合金から形成されて熱伝導率が小さくされているので
、前述のＡｐボール形成時にＡＩ３ボール近傍部位の人
がアニール（焼き戻し）されることになり、この第１ボ
ンディング部位置上の曲げ加工を芥易なものにできる。Thereby, the wire 16 is bent directly above the first bonding site B. In this case, the A wire 16 is
Since it is formed from an aluminum alloy and has a low thermal conductivity, the area near the AI3 ball is annealed (tempered) when forming the Ap ball mentioned above, and the bending process above the first bonding part position is can be made into something easy to buy.

曲げ加工後にクランパ２６の協働によりワイヤ１６を水
平方向に張設し、その上で従前と同様に配線回路ｌｌ上
に第２ボンデイングを完了すればワイヤボンディングが
完成されろ、なお、このときワイヤ１６の張設力は必要
以上に大きくしな゛ぐともよい。After the bending process, the wire 16 is stretched in the horizontal direction by the cooperation of the clamper 26, and then the second bonding is completed on the wiring circuit 11 as before to complete the wire bonding. The tensioning force 16 may not be made larger than necessary.

以上のようにして構成された半導体装置によれば、ワイ
ヤを第１ボンデイング部位Ｂ、の直上で曲げ加工してい
るので、ワイヤのループ高さＢ２な低減でき、これに伴
なって半導体装置全体を薄型化できる、因みに、第１図
の従来構造のループ高さＨｌが２５０μｍであるのに対
し、第２図のものでは１００〜１３０μｍと略半分にで
きる。According to the semiconductor device configured as described above, since the wire is bent directly above the first bonding portion B, the loop height B2 of the wire can be reduced, and the entire semiconductor device can be reduced accordingly. Incidentally, while the loop height Hl of the conventional structure shown in FIG. 1 is 250 μm, the loop height Hl of the conventional structure shown in FIG. 2 can be reduced to approximately half of 100 to 130 μm.

また、この場合、ワイヤ１６にＡ８合金な使用している
ので、第１ボンディング部位置上でのワイヤの曲げ加工
を極めて容易に行なうことができる。Further, in this case, since the wire 16 is made of A8 alloy, the wire can be bent extremely easily at the first bonding portion.

一方、ループ高さを低減してワイヤを張設しているので
、ボンディングに必要とされるワイヤ長を短かくするこ
とができ、これによりワイヤ使用量を低減してコストの
低減を図り得ろ。特にＡ６合金はＡｕよりも低価格であ
り、コストの低減な一層促進できる。On the other hand, since the loop height is reduced and the wire is stretched, the wire length required for bonding can be shortened, thereby reducing the amount of wire used and reducing costs. In particular, A6 alloy is cheaper than Au, and can further reduce costs.

なお、ワイヤボンダ２０はカム機構２５やクランパ２６
の仕様を若干変更し或いは各部の設定値を調節するだけ
でこれに対応することができろう〔効果〕 （１）　　ワイヤを第１ボンディング部ケの直上で曲げ
加工して張設しているので、ループ高さを低減でき、半
導体装置の薄型化な達成できる。Note that the wire bonder 20 has a cam mechanism 25 and a clamper 26.
This can be addressed by slightly changing the specifications or adjusting the setting values of each part. [Effects] (1) The wire is bent and stretched directly above the first bonding part. , the loop height can be reduced, and the semiconductor device can be made thinner.

（２；　　ループ高さを低減しかつワイヤを張設するこ
とにより、第１．第２ボンディング部位間のワイヤ長を
低減でき、ワイヤボンディングのワイヤ使用量の低減な
図って低コスト化な図ることができる。(2; By reducing the loop height and stretching the wire, the wire length between the first and second bonding parts can be reduced, reducing the amount of wire used in wire bonding and lowering costs. I can do it.

（３）　　ワイヤにＡ４１１１合金な使用することによ
り、第１ボンデイング直上での曲げ加工を容易にすると
共に、Ａｕを使用するものに対して低コスト化を実現で
きろ。(3) By using A4111 alloy for the wire, it is possible to easily bend the wire directly above the first bonding, and to achieve lower costs than those using Au.

（４）　　キャピラリの移動制御（エワイヤボンダのカ
ム機構等、その一部の仕様の変更、設定の調節でよいの
で、大幅な設計変更は必要としｒｌい。(4) Capillary movement control (such as the cam mechanism of the air bonder), as it is sufficient to change some of the specifications and adjust the settings; no major design changes are required.

以上本発明者によってなされた発明な実施例にもとづき
具体的に説明したが１本発明１工上記実施例に限定され
るものではなく、その要旨を逸脱しない範曲で種々変更
ｉＪ能であることはいうまでもない。たとえば、装置基
板としてリードフレームを使用する半導体装置やセラミ
ックペースを使用するものにも同様に適用することがで
きる。Although the invention has been specifically explained above based on the embodiments of the invention made by the present inventor, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say. For example, the invention can be similarly applied to semiconductor devices that use lead frames as device substrates and devices that use ceramic paste.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるボー′ルボンディン
グ方式の半導体装置に適用した場合について説明したが
、これ以外のボンディング方式、例えば超音波ボンディ
ング方式のワイヤボンディングの半導体装置にも適用す
ることができる。In the above explanation, the invention made by the present inventor was mainly applied to a semiconductor device using the ball bonding method, which is the field of application in which the invention was made, but other bonding methods, such as ultrasonic bonding method It can also be applied to wire bonding semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は考えられる半導体装置の断面図、第２図は本発
明の半導体装置の断面図、第３図はワイヤボンダの概略
構成図である。 １０・・・プリント回路基板、１４・・・素子ベンノド
、１６・・Ａｎワイヤ、１７・・・レジン、２０・・・
ワイヤボンダ、２４・・・キャピラリ、２５・・・カム
機構、２６・・・クランパ、２９・・・可動電極、Ｂ、
・・・第１ボンデイング部位、Ｂ２・・・第２ボンディ
ング部位。FIG. 1 is a sectional view of a possible semiconductor device, FIG. 2 is a sectional view of a semiconductor device of the present invention, and FIG. 3 is a schematic diagram of a wire bonder. DESCRIPTION OF SYMBOLS 10... Printed circuit board, 14... Element Bend, 16... An wire, 17... Resin, 20...
wire bonder, 24... capillary, 25... cam mechanism, 26... clamper, 29... movable electrode, B,
...first bonding site, B2...second bonding site.

Claims (1)

【特許請求の範囲】 １、半導体装置基板に固着した牛導体素子ペレットと、
前記基板とをポンディングワイヤにて電気接続してなる
半導体装置において、前記ワイヤは第１ボンデイングの
直上において曲げ加工しかつこれを張設して第２ボンデ
イングしてなること馨特徴とする半導体装置っ ２、第１ボンデイングにポールボンディング方式を用い
てなる特許請求の範囲第１項記載の半導体装置っ ３、　ボンディングワイヤにへ召合金を用いてなる特許
請求の範囲第１項又は第２項記戦の半導体装置。[Claims] 1. A conductor element pellet fixed to a semiconductor device substrate;
A semiconductor device electrically connected to the substrate by a bonding wire, characterized in that the wire is bent directly above the first bonding and then stretched to form a second bonding. 2. A semiconductor device according to claim 1 in which a pole bonding method is used for the first bonding; 3. A semiconductor device according to claim 1 or 2 in which a bonding wire is made of a bending alloy. Semiconductor equipment of war.
JP58042211A 1983-03-16 1983-03-16 Semiconductor device Granted JPS59169165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58042211A JPS59169165A (en) 1983-03-16 1983-03-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58042211A JPS59169165A (en) 1983-03-16 1983-03-16 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59169165A true JPS59169165A (en) 1984-09-25
JPH0447972B2 JPH0447972B2 (en) 1992-08-05

Family

ID=12629686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58042211A Granted JPS59169165A (en) 1983-03-16 1983-03-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59169165A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49100566A (en) * 1973-01-30 1974-09-24
JPS5730206A (en) * 1980-06-24 1982-02-18 Heraeus Gmbh W C Contact extra fine conductor for semiconductor constituent element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49100566A (en) * 1973-01-30 1974-09-24
US3908184A (en) * 1973-01-30 1975-09-23 Nippon Electric Co Ceramic substrate assembly for electronic circuits having ceramic films thereon for intercepting the flow of brazing agents
JPS5730206A (en) * 1980-06-24 1982-02-18 Heraeus Gmbh W C Contact extra fine conductor for semiconductor constituent element

Also Published As

Publication number Publication date
JPH0447972B2 (en) 1992-08-05

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