JPH05211192A - Wire binding method of semiconductor device - Google Patents

Wire binding method of semiconductor device

Info

Publication number
JPH05211192A
JPH05211192A JP3161696A JP16169691A JPH05211192A JP H05211192 A JPH05211192 A JP H05211192A JP 3161696 A JP3161696 A JP 3161696A JP 16169691 A JP16169691 A JP 16169691A JP H05211192 A JPH05211192 A JP H05211192A
Authority
JP
Japan
Prior art keywords
wire
pad
gold
semiconductor device
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3161696A
Other languages
Japanese (ja)
Inventor
Akihisa Iguchi
明久 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3161696A priority Critical patent/JPH05211192A/en
Publication of JPH05211192A publication Critical patent/JPH05211192A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
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    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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Abstract

PURPOSE:To reduces the spaces between pads and prevent sagging and curling of a wire loop, in a wire bonding method of a semiconductor device. CONSTITUTION:A wire bonding method of a semiconductor device, wherein when wire-bonding the semiconductor device a gold ball 14a is formed beforehand on a pad 12a of a semiconductor chip 12, and a gold wire 14 is jointed to an external terminal 13 of a lead frame, and the gold wire 14 is stretched, and thereafter, the gold wire 14 is wedge-bonded to the gold ball 14a formed on the pad 12a of the semiconductor chip 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路におけ
る内部配線であるワイヤボンディング方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding method for internal wiring in a semiconductor integrated circuit.

【０００２】[0002]

【従来の技術】従来、このような分野の技術としては、
例えば、以下に示すようなものがあった。図３はかかる
従来の半導体装置のワイヤボンディング工程図である。
まず、図３（ａ）に示すように、ダイパッド１上の半導
体素子２をパッケージの外部端子３に接続する場合、金
属細線４の先端を熱で溶解し、球状５としたものを、半
導体素子２上のパッドに接続した後、その金属細線４を
パッケージの外部端子３側へ導いて接合する。2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. FIG. 3 is a wire bonding process diagram of such a conventional semiconductor device.
First, as shown in FIG. 3A, when the semiconductor element 2 on the die pad 1 is connected to the external terminal 3 of the package, the tip of the metal thin wire 4 is melted by heat so that the spherical shape 5 is obtained. After connecting to the pad on 2, the thin metal wire 4 is guided to the external terminal 3 side of the package and joined.

【０００３】次に、図３（ｂ）に示すように、外部端子
３上の金属細線４を切断する。最後に、図３（ｃ）に示
すように、金属細線４の先端を球状５となし、次の箇所
のワイヤボンドに備える。なお、６はキャピラリ、７は
クランパである。Next, as shown in FIG. 3B, the thin metal wire 4 on the external terminal 3 is cut. Finally, as shown in FIG. 3C, the tip of the thin metal wire 4 is formed into a spherical shape 5 to prepare for wire bonding at the next location. In addition, 6 is a capillary and 7 is a clamper.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、従来の
ワイヤボンディング方法では、半導体素子のパッド側の
金属細線４が１５０μｍから４００μｍ程度立ち上がっ
ているために、半導体素子２上のパッド配列間隔を狭め
るためには、キャピラリ６の先端が隣の既に存在する金
属細線に干渉しないように細くするか、もしくは干渉し
ない程度のパッド配列間隔にとめる等の対策を必要とし
ていた。しかし、キャピラリ６の先端を細くする方法に
も限界があり、おのずとパッド配列間隔は制約されてし
まうという問題点があった。However, in the conventional wire bonding method, since the fine metal wire 4 on the pad side of the semiconductor element rises from 150 μm to 400 μm, the pad arrangement interval on the semiconductor element 2 is narrowed. Requires a measure such as making the tip of the capillary 6 thin so as not to interfere with the existing thin metal wire next to it, or keeping the pad arrangement interval such that it does not interfere. However, there is a limit to the method of making the tip of the capillary 6 thin, and there is a problem that the pad arrangement interval is naturally limited.

【０００５】本発明は、上記問題点を除去し、パッド間
隔の縮小化が可能で、しかもワイヤループの垂みや、カ
ールが発生することがない半導体装置のワイヤボンディ
ング方法を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a wire bonding method for a semiconductor device which eliminates the above-mentioned problems and can reduce the pad distance, and which does not cause wire loop sagging or curling. To do.

【０００６】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するために、半導体装置のワイヤボンディング方法に
おいて、予め半導体素子のパッド上に金属球を形成し、
リードフレームの外部端子に金属細線を接合し、該金属
細線を張り、前記半導体素子のパッド上の金属球にウェ
ッジボンドするようにしたものである。In order to achieve the above object, the present invention is a wire bonding method for a semiconductor device, in which a metal sphere is previously formed on a pad of a semiconductor element,
A thin metal wire is joined to the external terminal of the lead frame, the thin metal wire is stretched, and wedge-bonded to a metal ball on the pad of the semiconductor element.

【０００７】また、前記半導体素子のパッド上にはバン
プが形成されたものを用いることもできる。It is also possible to use a semiconductor device having a bump formed on the pad.

【０００８】[0008]

【作用】本発明によれば、ワイヤボンディング方法にお
いて、予め、半導体素子のパッド上に金球を接合し、金
球のみを残して金線を一旦カットし、金球の生成を行な
う。次に、２つ目に形成した金球をリードフレームの外
部端子に接合し、そこから導いた金線を先程パッド上に
接合した金球へ接合することにより、電気的導通を得
る。According to the present invention, in the wire bonding method, a gold ball is previously bonded on the pad of the semiconductor element, and the gold wire is temporarily cut while leaving only the gold ball to generate the gold ball. Next, the second formed gold ball is joined to the external terminal of the lead frame, and the gold wire introduced from the second gold ball is joined to the gold ball previously joined to the pad to obtain electrical conduction.

【０００９】従って、パッド間隔の縮小化が可能であ
り、しかも、ワイヤループの垂みや、カールが発生する
ことがない。Therefore, it is possible to reduce the pad interval, and furthermore, the wire loop does not sag or curl.

【００１０】[0010]

【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は本発明の実施例を示す前
半の半導体装置のワイヤボンディング工程断面図であ
り、図２は本発明の実施例を示す後半の半導体装置のワ
イヤボンディング工程断面図である。Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a sectional view of a wire bonding process of a semiconductor device in the first half showing an embodiment of the present invention, and FIG. 2 is a sectional view of a wire bonding process in a semiconductor device of the latter half showing an embodiment of the present invention.

【００１１】まず、図１（ａ）に示すように、キャピラ
リ１６の下方の金線１４の先端に形成された金球１４ａ
を、ダイパッド１１上に搭載された半導体素子１２のパ
ッド１２ａ上に位置合わせする。次に、図１（ｂ）に示
すように、金線１４の先端に形成された金球１４ａをキ
ャピラリ１６により半導体素子１２のパッド１２ａ上に
押し付け接合する。First, as shown in FIG. 1 (a), a gold ball 14a formed at the tip of the gold wire 14 below the capillary 16.
Are aligned with the pads 12a of the semiconductor element 12 mounted on the die pad 11. Next, as shown in FIG. 1B, the gold ball 14a formed at the tip of the gold wire 14 is pressed and bonded onto the pad 12a of the semiconductor element 12 by the capillary 16.

【００１２】次いで、図１（ｃ）に示すように、金球形
成に必要な金球長さｌをキャピラリ１６から繰り出した
ところで、クランパ１７を閉じる。次に、図１（ｄ）に
示すように、キャピラリ１６を上昇させて、金球１４ａ
から金線１４を切断する。次に、図１（ｅ）に示すよう
に、トーチ１８により、金球１４ｂを形成する。Next, as shown in FIG. 1 (c), when the gold ball length 1 required for forming the gold ball is paid out from the capillary 16, the clamper 17 is closed. Next, as shown in FIG. 1D, the capillary 16 is lifted to move the gold ball 14a.
The gold wire 14 is cut from. Next, as shown in FIG. 1E, the torch 18 is used to form the gold ball 14b.

【００１３】次いで、図２（ｆ）に示すように、リード
フレームの外部端子１３にその金球１４ｂを位置合わせ
する。次いで、図２（ｇ）に示すように、リードフレー
ムの外部端子１３にその金球１４ｂを接合する。次に、
図２（ｈ）に示すように、既存の方式により、ワイヤル
ープを形成しながら、金線１４を導いていく。Next, as shown in FIG. 2F, the gold ball 14b is aligned with the external terminal 13 of the lead frame. Next, as shown in FIG. 2G, the gold ball 14b is bonded to the external terminal 13 of the lead frame. next,
As shown in FIG. 2H, the gold wire 14 is guided while forming a wire loop by an existing method.

【００１４】次に、図２（ｉ）に示すように、金線１４
を半導体素子１２のパッド１２ａ上に既に形成された金
球１４ａ上にウェッジボンドする。次に、図２（ｊ）に
示すように、ワイヤボンドに必要な金球形成のためテー
ル１４ｔを繰り出す。次に、図２（ｋ）に示すように、
金球１４ｃをトーチ１８により作る。Next, as shown in FIG. 2 (i), the gold wire 14
Is wedge-bonded onto the gold ball 14a already formed on the pad 12a of the semiconductor element 12. Next, as shown in FIG. 2 (j), the tail 14t is extended to form a gold ball necessary for wire bonding. Next, as shown in FIG.
The gold ball 14c is made by the torch 18.

【００１５】このように、上記のサイクルを続けること
で、ワイヤボンドを行なうことができる。なお、上記実
施例においては、図１（ｄ）に示すように、半導体素子
１２のパッド１２ａ上にキャピラリ１６により金球１４
ａを形成するようにしているが、これに代えて、図４に
示すように、ダイパッド２１上に予めバンプ２３が形成
された半導体素子２２を搭載し、そのバンプ２３上に、
図２（ｉ）と同様に、金線２５をウェッジボンドするよ
うにしてもよい。２４は外部端子である。In this way, wire bonding can be performed by continuing the above cycle. In the above embodiment, as shown in FIG. 1D, the gold balls 14 are formed on the pads 12a of the semiconductor element 12 by the capillaries 16.
Although a is formed, instead of this, as shown in FIG. 4, a semiconductor element 22 in which bumps 23 are formed in advance on the die pad 21 is mounted, and on the bumps 23,
Similarly to FIG. 2I, the gold wire 25 may be wedge-bonded. 24 is an external terminal.

【００１６】上記したように、予め、金球を形成する方
式は、金球形成の位置精度が要求され、次のワイヤボン
ド時に、もう一度金球位置を画像認識補正を個々の金球
について行なうことが必要とされる時に有利である。ま
た、バンプ付き半導体素子を用いる場合は、金球形成
に要するワイヤボンドの時間を短縮することができる。
パッドがダメージを受け易い構造の場合に、全くダメ
ージを与えずに形成できるバンプをつけて、ワイヤボン
ドの衝撃を和らげることができる。As described above, the method of forming gold balls in advance requires the positional accuracy of gold ball formation, and at the time of the next wire bonding, the gold ball position is again subjected to image recognition correction for each gold ball. Is advantageous when is needed. Further, when the bumped semiconductor element is used, the wire bonding time required for forming the gold ball can be shortened.
In the case where the pad has a structure that is easily damaged, bumps that can be formed without damaging the pad can be attached to soften the impact of the wire bond.

【００１７】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

【００１８】[0018]

【発明の効果】以上、詳細に説明したように、本発明に
よれば、半導体素子のパッド間隔の縮小化を図ることが
できる。例えば、従来１８０μｍピッチであったパッド
間隔を１００μｍ以下とすることができる。その場合、
現在のワイヤボンド装置を流用して、簡単に実施するこ
とができる。As described above in detail, according to the present invention, it is possible to reduce the pad spacing of the semiconductor element. For example, the pad spacing, which was conventionally 180 μm pitch, can be set to 100 μm or less. In that case,
It can be easily implemented by using the current wire bonding device.

【００１９】更に、以下に述べる効果を奏することがで
きる。 （１）キャピラリ先端の形状は現状のままで良い。 （２）リードフレームの外部端子のボンディング強度が
リード形状に影響されることがない。 （３）リードフレームの外部端子のボンディング時に、
従来発生していたワイヤループの垂みや、カールが発生
することがない。Further, the following effects can be obtained. (1) The shape of the tip of the capillary may remain unchanged. (2) The bonding strength of the external terminals of the lead frame is not affected by the lead shape. (3) When bonding the external terminals of the lead frame,
The sagging of wire loops and the curl that have conventionally occurred do not occur.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例を示す前半の半導体装置のワイ
ヤボンディング工程断面図（その１）である。FIG. 1 is a sectional view (No. 1) of a wire bonding process of a semiconductor device in the first half showing an embodiment of the present invention.

【図２】本発明の実施例を示す後半の半導体装置のワイ
ヤボンディング工程断面図（その２）である。FIG. 2 is a sectional view (No. 2) of the wire bonding process of the semiconductor device in the latter half showing the embodiment of the present invention.

【図３】従来の半導体装置のワイヤボンディング工程図
である。FIG. 3 is a wire bonding process diagram of a conventional semiconductor device.

【図４】本発明の他の実施例を示す半導体装置のワイヤ
ボンディング状態を示す断面図である。FIG. 4 is a sectional view showing a wire bonding state of a semiconductor device showing another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１１，２１ ダイパッド １２，２２ 半導体素子 １２ａ パッド １３，２４ 外部端子 １４，２４ 金線 １４ａ，１４ｂ，１４ｃ 金球 １４ｔ テール １６ キャピラリ １７ クランパ １８ トーチ ２３ バンプ 11, 21 Die pad 12, 22 Semiconductor element 12a Pad 13, 24 External terminal 14, 24 Gold wire 14a, 14b, 14c Gold ball 14t Tail 16 Capillary 17 Clamper 18 Torch 23 Bump

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】（ａ）予め半導体素子のパッド上に金属球
を形成し、 （ｂ）次に、リードフレームの外部端子に金属細線を接
合し、 （ｃ）該金属細線を張り、前記半導体素子のパッド上の
金属球にウェッジボンドすることを特徴とする半導体装
置のワイヤボンディング方法。1. A semiconductor ball is formed in advance on a pad of a semiconductor element, and a thin metal wire is bonded to an external terminal of a lead frame. A wire bonding method for a semiconductor device, comprising wedge-bonding to a metal ball on a pad of a device. 【請求項２】 前記パッド上にはバンプが形成された半
導体素子を用いることを特徴とする請求項１記載の半導
体装置のワイヤボンディング方法。2. The wire bonding method for a semiconductor device according to claim 1, wherein a semiconductor element having a bump formed on the pad is used.
JP3161696A 1991-07-02 1991-07-02 Wire binding method of semiconductor device Withdrawn JPH05211192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3161696A JPH05211192A (en) 1991-07-02 1991-07-02 Wire binding method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3161696A JPH05211192A (en) 1991-07-02 1991-07-02 Wire binding method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05211192A true JPH05211192A (en) 1993-08-20

Family

ID=15740127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3161696A Withdrawn JPH05211192A (en) 1991-07-02 1991-07-02 Wire binding method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05211192A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0753891A2 (en) * 1995-06-28 1997-01-15 Texas Instruments Incorporated Low loop wire bonding
US6079610A (en) * 1996-10-07 2000-06-27 Denso Corporation Wire bonding method
JP2002237499A (en) * 2001-02-09 2002-08-23 Mitsubishi Electric Corp Method and apparatus for manufacturing semiconductor device
WO2002082527A1 (en) * 2001-04-05 2002-10-17 Stmicroelectronics Pte Ltd Method of forming electrical connections
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
EP1374298A1 (en) * 2001-03-23 2004-01-02 Koninklijke Philips Electronics N.V. Chip module with bond-wire connections with small loop height
KR100734269B1 (en) * 2005-07-29 2007-07-02 삼성전자주식회사 Wire bonding apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0753891A2 (en) * 1995-06-28 1997-01-15 Texas Instruments Incorporated Low loop wire bonding
EP0753891A3 (en) * 1995-06-28 1999-03-31 Texas Instruments Incorporated Low loop wire bonding
US6079610A (en) * 1996-10-07 2000-06-27 Denso Corporation Wire bonding method
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
JP2002237499A (en) * 2001-02-09 2002-08-23 Mitsubishi Electric Corp Method and apparatus for manufacturing semiconductor device
EP1374298A1 (en) * 2001-03-23 2004-01-02 Koninklijke Philips Electronics N.V. Chip module with bond-wire connections with small loop height
WO2002082527A1 (en) * 2001-04-05 2002-10-17 Stmicroelectronics Pte Ltd Method of forming electrical connections
KR100734269B1 (en) * 2005-07-29 2007-07-02 삼성전자주식회사 Wire bonding apparatus

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