KR100243555B1 - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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KR100243555B1
KR100243555B1 KR1019920027592A KR920027592A KR100243555B1 KR 100243555 B1 KR100243555 B1 KR 100243555B1 KR 1019920027592 A KR1019920027592 A KR 1019920027592A KR 920027592 A KR920027592 A KR 920027592A KR 100243555 B1 KR100243555 B1 KR 100243555B1
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bonding
wire
pad
semiconductor chip
package
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KR1019920027592A
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KR940016441A (en
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최종곤
임민빈
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윤종용
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/05554—Shape in top view being square
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4945—Wire connectors having connecting portions of different types on the semiconductor or solid-state body, e.g. regular and reverse stitches
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

이 발명은 와이어 본딩 방법의 개선으로 루프 높이를 낮춤으로써 얇은 패키지를 실현할 수 있는 반도체 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor package capable of realizing a thin package by lowering the loop height by an improvement of the wire bonding method, and a manufacturing method thereof.

종래의 표면 실장형 패키지의 경우, 패드에 1차 볼본딩을 실시한 후, 2차로 내부리드상에 스티치(Stitch) 본딩하여 패드와 내부리드간을 결선함으로써 낮은 루프높이의 실현에 한계가 있었다.In the case of the conventional surface mount package, there is a limit to the realization of the low loop height by performing the first ball bonding on the pad and then stitch bonding the inner lead to the second lead to connect the pad and the inner lead.

이 발명은 와이어 본딩 공정을 개선한 것으로, 내부리드상에 1차 볼본딩을 실시한 후, 패드에 2차로 스티치본딩을 실시하여 패키지 탑면에서 와이어 루프 절곡부위까지의 길이를 50㎛ 이상 낮춤으로써 종래의 본딩장비를 이용하여 TSOP, TQFP 등의 초박형패키지를 제조할 수 있다.The present invention is an improvement of the wire bonding process, by performing the first ball bonding on the inner lead, and then stitch bonding to the pad secondly to reduce the length from the top of the package to the wire loop bent portion by 50㎛ or more Bonding equipment can be used to manufacture ultra-thin packages such as TSOP and TQFP.

Description

반도체 패키지 및 그 제조방법Semiconductor package and manufacturing method

제1도는 종래 기술에 따른 반도체 패키지의 단면도,1 is a cross-sectional view of a semiconductor package according to the prior art,

제2도는 이 발명의 실시예에 따른 반도체 패키지의 단면도,2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention,

제3도는 제2도의 요부(A) 확대도,3 is an enlarged view of the main portion (A) of FIG.

제4도는 이 발명의 제조공정중 와이어 본딩 구조를 나타내는 사시도이고,4 is a perspective view showing the wire bonding structure in the manufacturing process of the present invention,

제5도는 종래 기술과 이 발명의 실시예의 패키지를 비교하기 위해 나타낸 비교 단면도이다.5 is a comparative cross-sectional view shown for comparing the package of the prior art with the embodiment of the present invention.

이 발명은 반도체 패키지에 관한 것으로, 특히 와이어 본딩 방법의 개선으로 루프 높이를 낮춤으로써 얇은 패키지를 실현할 수 있는 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of realizing a thin package by lowering a loop height by an improvement of a wire bonding method, and a manufacturing method thereof.

전자기기의 경박단소화 및 반도체 장치의 고집적화의 요구에 따라 반도체 미세 가공기술을 이용한 고집적 디바이스가 개발되고 있다. 반도체 장치의 집적도 증가는 칩 사이즈, 입출력 단자 등의 증가를 수반하게 된다. 그러므로 전자제품의 소형 경량화에 따른 실장 합리화를 위해서는 반도체 패키지의 개발이 중요한 과제가 되고 있다.BACKGROUND ART In accordance with the demand for light and short and small integration of electronic devices and high integration of semiconductor devices, highly integrated devices using semiconductor micromachining techniques have been developed. The increase in the degree of integration of semiconductor devices is accompanied by an increase in chip size, input / output terminals, and the like. Therefore, the development of a semiconductor package has become an important task for the rationalization of the mounting according to the compact and lightweight electronic products.

현재까지 패키지 기술은 소형화, 박형화 및 고기능화로 추진되고 있고 이러한 경향에 의해 종래의 삽입형 패키지에서 고밀도 실장을 위한 표면 실장형(Surface Mounting Type) 패키지로 전환하여 효율면에서 많은 진보를 보이고 있다.To date, package technology has been promoted to be miniaturized, thinned and highly functionalized, and this trend has made a lot of progress in efficiency by switching from a conventional insert package to a surface mounting type package for high density mounting.

상기 표면 실장형 패키지, 예를 들어 TSOP(Thin Small Outline Package), TQFP(Thin Quad Flat Package)등은 기존의 와이어 본딩방법으로 제조되는 것으로 그 두께가 매우 얇으며 무게도 종래의 SOJ(Small Outline J-form Package)에 비하여 3분의 1로 가볍기 때문에 패키지 설계 및 재료의 선택등 제조공정상 많은 문제점이 따른다.The surface mount package, for example, Thin Small Outline Package (TSOP), Thin Quad Flat Package (TQFP), etc. is manufactured by a conventional wire bonding method, and its thickness is very thin. Compared to -form package, it is lighter than one third, so there are many problems in manufacturing process such as package design and material selection.

상기 표면 실장형 패키지의 일예를 제 1 도에 나타내었다. 제 1 도는 종래의 TSOP의 단면도이다. 종래의 TSOP는 리드 프레임의 다이패드(10)상에 접착제(13)를 매개하여 반도체 칩(14)이 접착되어 있고, 상기 반도체 칩(14)의 패드(14a)와 내부리드(12a)는 금(Au) 등의 미세 금속선인 본딩 와이어(15)로 결선되어 있다. 그리고 본딩 와이어(15) 접속 후에 내부리드(12a)를 포함하는 반도체 칩(14)이 중앙에 위치하도록 상기 내부리드(12a)까지 성형수지(16)로 몰딩되어 있다. 몰딩되지 않은 외부리드(12b)들은 하향절곡되어 있다.An example of the surface mount package is shown in FIG. 1 is a cross-sectional view of a conventional TSOP. In the conventional TSOP, the semiconductor chip 14 is bonded to the die pad 10 of the lead frame via an adhesive 13, and the pad 14a and the inner lead 12a of the semiconductor chip 14 are formed of gold. It is connected by the bonding wire 15 which is a fine metal wire, such as (Au). After the bonding wire 15 is connected, the semiconductor chip 14 including the inner lead 12a is molded into the molding resin 16 up to the inner lead 12a so as to be located at the center. The unmolded outer leads 12b are bent downward.

상기 구조를 갖는 종래의 패키지는 현재 본딩 와이어(15)의 루프(loop) 높이를 낮게 조절하여 1mm 정도의 두께를 갖는 얇은 패키지를 실현하고 있다. 그러나 반도체 칩(14)의 두께, 루프 높이등의 제약, 반도체 칩(14) 등의 상하부를 완전히 에워싸는 성형수지(16), 즉 반도체 칩(14) 위의 수지두께, 리드 프레임 밑의 수지 두께에 의해 박형화에 한계가 있다.The conventional package having the above structure currently realizes a thin package having a thickness of about 1 mm by adjusting the loop height of the bonding wire 15 low. However, the thickness of the semiconductor chip 14, the restrictions on the loop height, the molding resin 16 that completely encloses the upper and lower portions of the semiconductor chip 14, that is, the resin thickness on the semiconductor chip 14, and the resin thickness under the lead frame. There is a limit to thinning.

특히, 상기 루프 높이는 얇은 패키지의 실현에 중요한 요소가 되는 것이다. 이 루프 높이 문제와 관련한 종래의 패키지 제조방법에 있어서 본딩공정을 중심으로 살펴본다.In particular, the loop height is an important factor in the realization of a thin package. In the conventional package manufacturing method related to the loop height problem, a look at the bonding process will be given.

반도체 칩(14)을 탑재하기 위한 다이패드(10)가 내부리드(12a)보다 낮게 위치된 리드 프레임을 준비하고, 다이접착(Die attach) 공정을 실시하여 상기 리드 프레임의 다이패드(10)상에 반도체 칩(14)을 접착제(13)를 매개하여 접착시킨다.The die pad 10 for mounting the semiconductor chip 14 prepares a lead frame positioned lower than the inner lead 12a, and a die attach process is performed on the die pad 10 of the lead frame. The semiconductor chip 14 is adhered to each other via an adhesive 13.

다이접착 공정 후, 반도체 칩(14)이 다이패드(10)상에 접착된 리드 프레임을 히터블록(Heater block)위에 올려놓고, 190∼330℃ 정도 가열되면 캐필러리(도시하지 않음)내에 있는 금(Au) 와이어의 끝에 전기 스파크(EPO; Electrical flame off)로 볼(Ball)을 형성하여, 상기 볼을 캐필러리(Capiliary)로 반도체 칩(14)의 패드(14a)에 일정한 압착력으로 압착시킨다. 이때 캐필러리에 초음파를 인가하여 볼에 진동을 주고, 볼을 압착할때 패드(14a)상에 문질러주어 압착이 잘되도록 한다.After the die-bonding process, the semiconductor chip 14 places the lead frame bonded on the die pad 10 on a heater block, and is heated in a capillary (not shown) when heated to 190 to 330 ° C. A ball is formed by an electrical flame off (EPO) at the end of the Au wire, and the ball is capillary pressed into the pad 14a of the semiconductor chip 14 with a constant pressing force. Let's do it. At this time, the ultrasonic wave is applied to the capillary, the ball is vibrated, and when the ball is compressed, it is rubbed on the pad 14a so that the compression is good.

상기 패드(14a)에 1차 볼본딩을 실시한 후, 계속해서 캐필러리를 수직 상승시킨 다음 내부리드(12a)로 옮겨 루핑 오퍼레이션을 실시하고, 2차로 내부리드(12a)상에 2차 스티치본딩을 행하므로 본딩공정후의 루프 높이 예를 들어 반도체 칩(14) 탑에서부터의 높이(G)가 필연적으로 높게 되는 등 공정상에도 문제가 발생한다.After the first ball bonding to the pad 14a, the capillary is vertically raised and then moved to the inner lead 12a to perform a looping operation, and the second stitch bonding on the inner lead 12a is performed secondly. This causes problems in the process, such as the loop height after the bonding step, for example, the height G from the top of the semiconductor chip 14 inevitably becomes high.

즉, 내부리드(12a)는 패키지의 중간에 위치하고 반도체 칩(14)은 그보다 위쪽에 위치하므로 와이어 본딩시 루프가 반도체 칩(14)에서 형성됨에 따라 패키지 탑(top)에서 와이어(15)까지의 거리가 짧아져 공정 컨트롤이 어려우며 몰딩시 세심한 주의가 필요하다. 얇은 패키지 두께(PH)를 실현하기 위해서는 특별한 와이어 재료와 본딩설비가 필요하게 되고, 종래의 와이어 본딩방식으로는 패키지 두께에 영향을 미치는 루프 높이를 150㎛ 이하로 유지하기가 어려우며 몰드 공정중 극히 적은 양의 패드 틸트(Tilt)가 발생되더라도 본딩 와이어가 패키지 밖으로 돌출하게 되는 현상이 발생함으로 루프 높이를 더욱 낮출 수 있는 방법이 필요하다. 또한, 멀티칩 패키지의 경우에 있어서, 한 패드와 다른 패드의 구조가 동일하여 와이어 처짐(Sagging) 발생시 반도체 칩과 본딩 와이어가 단락되는 현상이 발생한다.That is, since the inner lead 12a is located in the middle of the package and the semiconductor chip 14 is located above it, as the loop is formed in the semiconductor chip 14 at the time of wire bonding, from the package top to the wire 15. Shorter distances make process control difficult and require careful attention to molding. In order to realize a thin package thickness (PH), a special wire material and bonding equipment are required. In the conventional wire bonding method, it is difficult to keep the loop height below 150 μm affecting the package thickness and extremely small during the molding process. Even if a positive pad tilt occurs, the bonding wire protrudes out of the package. Thus, a method of further reducing the loop height is required. In addition, in the case of a multichip package, the structure of one pad and the other pad is the same, and a phenomenon in which the semiconductor chip and the bonding wire are short-circuited when wire sagging occurs.

이 발명의 목적은 와이어 본딩 공정의 개선으로 루프 높이를 낮춤으로써 박형화가 용이한 반도체 패키지 및 그 제조방법을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package and a method for manufacturing the same, which are easily thinned by lowering the loop height by improving the wire bonding process.

상기와 같은 목적을 달성하기 위한 이 발명은, 리드 프레임의 다이패드상에 접착제를 매개하여 반도체 칩이 접착되고, 상기 반도체 칩의 다수개의 패드와 다수개의 내부리드간은 본딩 와이어로 결선되고, 상기 본딩 와이어 접속 후에 내부리드를 포함하는 상기 반도체 칩이 중앙에 위치하도록 상기 내부리드까지 성형수지로 몰딩되며, 몰딩되지 않은 외부리드들은 하향절곡되게 구성된 반도체 패키지에 있어서, 상기 본딩 와이어는 루프 높이를 낮게 하기 위하여 볼본딩이 내부리드에 형성되고, 스티치본딩이 상기 패드에 이루어지며, 상기 반도체 칩의 에지부분과 패드의 외곽에 와이어 처짐에 의한 단락 방지를 위한 절연물질이 코팅된 것을 특징으로 하는 반도체 패키지를 제공한다.The present invention for achieving the above object, the semiconductor chip is bonded to the die pad of the lead frame via an adhesive, a plurality of pads and a plurality of internal leads of the semiconductor chip is connected by a bonding wire, In a semiconductor package configured to be bonded to the inner lead after the bonding wire connection, the semiconductor chip including the inner lead to the inner lead, the unmolded outer lead is bent downward, the bonding wire is low in the loop height Ball bonding is formed on the inner lead, stitch bonding is made on the pad, and a semiconductor package characterized in that an insulating material is coated on the edge of the semiconductor chip and the outer edge of the pad to prevent short circuit due to wire sag. To provide.

상기한 목적을 달성하기 위한 이 발명에 따른 반도체 패키지의 제조방법은, 다수의 내부리드가 형성된 리드 프레임의 다이패드상에 다수개의 패드를 갖는 반도체 칩을 접착시키는 공정과, 캐필러리에 접착되어 있는 소정재질의 본딩 와이어의 끝단에 볼을 형성하는 공정과, 상기 내부리드 상에 1차 볼본딩을 실시한 후 캐필러리를 수직상승시켰다가 수평하강을 하여 상기 패드에 2차로 스티치본딩을 실시하는 것을 1사이클로 본딩 해당 수만큼 반복하는 와이어 본딩공정과, 상기 반도체 칩, 본딩 와이어 및 리드 프레임을 봉합시켜 패키지 몸체를 형성하는 공정을 포함하는 반도체 패키지 제조방법에 있어서, 상기 반도체 칩을 접착시키는 공정전에 와이어 처짐에 의한 단락 불량 방지를 위하여 상기 패드 주위에 절연물질을 코팅하는 공정을 더 포함하는 것을 특징으로 하는 반도체 패키지 제조방법을 제공한다.A method of manufacturing a semiconductor package according to the present invention for achieving the above object is a step of bonding a semiconductor chip having a plurality of pads on a die pad of a lead frame having a plurality of inner leads, and is bonded to the capillary Forming a ball at the end of the bonding wire of a predetermined material, and performing a first ball bonding on the inner lead, vertically raising the capillary, and then horizontally lowering the second stitch bonding to the pad. A method of manufacturing a semiconductor package comprising a wire bonding step of repeating a corresponding number of cycles in one cycle, and a step of sealing the semiconductor chip, the bonding wire, and the lead frame to form a package body. The method may further include coating an insulating material around the pad to prevent short circuit failure due to sag. Provided is a method of manufacturing a semiconductor package.

이하, 첨부한 도면을 참조하여 이 발명에 따른 반도체 패키지 및 그 제조방법을 상세히 설명한다.Hereinafter, a semiconductor package and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

제 2 도는 이 발명의 실시예에 따른 반도체 패키지의 단면도이다. 설명의 편의상 종래와 동일부분에 대한 도면부호는 동일하게 부여하고 상세한 설명은 생략한다.2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. For convenience of description, the same reference numerals are used for the same parts as in the related art, and detailed descriptions thereof will be omitted.

제 2 도에 나타낸 바와 같이, 리드 프레임의 다이패드(10)상에 접착제(13)를 매개하여 반도체 칩(14)이 접착되어 있고, 상기 반도체 칩(14)의 패드(14a)와 내부리드(12a)는 본딩 와이어(15)로 결선되어 있다. 이때, 상기 본딩 와이어(15)는 볼본딩이 내부리드(12a)상에 형성되고, 스티치본딩이 상기 패드(14a)에 이루어져 있다. 상기 패드(14a) 주위에는 절연물질(17) 예를 들어 폴리이미드(Polyimide)등이 코팅되어 있다. 그리고 본딩 와이어(15) 접속후에 내부리드(12a)를 포함하는 반도체 칩(14)이 중앙에 위치하도록 상기 내부리드(12a)까지 성형수지(16)로 몰딩되어 있다.As shown in FIG. 2, the semiconductor chip 14 is adhered to the die pad 10 of the lead frame via the adhesive 13, and the pad 14a and the inner lead of the semiconductor chip 14 12a) is connected by the bonding wire 15. At this time, the bonding wire 15 is ball bonding is formed on the inner lead (12a), stitch bonding is made on the pad (14a). An insulating material 17, for example, polyimide, is coated around the pad 14a. After the bonding wire 15 is connected, the semiconductor chip 14 including the inner lead 12a is molded into the molding resin 16 up to the inner lead 12a so as to be positioned at the center.

이러한 패키지 구조에서, 패키지 높이(PH)에 영향을 미치는 루프 높이 예를 들어 반도체 칩(14)의 탑에서부터 높이(G)가 반도체 칩(14)과 내부 리드(12a) 상면과의 사이 높이(d) 만큼 종래의 경우에 비해 낮아짐을 알 수 있다.In this package structure, the loop height affecting the package height PH, for example, the height G from the top of the semiconductor chip 14 is the height d between the semiconductor chip 14 and the upper surface of the internal lead 12a. It can be seen that the lower as compared to the conventional case.

이 경우, 패드(14a)상의 스티치본딩에 의해 반도체 칩(14) 에지부에서 본딩 와이어(15)가 단락될 가능성에 대한 대비책으로, 제 3 도의 요부(A) 확대도에 나타낸 바와 같이, 반도체 칩(14)의 패드(14a) 외곽에 절연물질(17)을 코팅을 하여 와이어 처짐에 의한 단락 불량을 방지하도록 하였다.In this case, as a countermeasure against the possibility that the bonding wire 15 is short-circuited at the edge of the semiconductor chip 14 by stitch bonding on the pad 14a, as shown in the enlarged view of the main portion A of FIG. The insulating material 17 was coated on the outside of the pad 14a of (14) to prevent short circuit defects due to sag of wire.

제 4 도는 이 발명의 와이어본딩 구조를 나타내는 사시도이다. 타이바(Tie bar)(11)로 지지되어 있는 다이패드(10)와, 다수개의 내부리드(12a)가 형성된 리드 프레임이 마련되고, 상기 다이패드(10)상에 반도체 칩(14)이 탑재되어 있다. 반도체 칩(14)의 패드(14a)와 내부리드(12a)간에는 본딩 와이어(15)로 결선되어 있다. 상기 본딩 와이어(15)는 내부리드(12a)에 볼본딩이 되고, 패드(12a)에 스티치본딩이 이루어져 있다. 패드(14a)상에 스티치본딩이 이루어져 있기 때문에 본딩 와이어(15)와 패드(14a) 에지부분에서 단락의 가능성이 있다. 이를 방지하기 위하여 반도체칩(14) 에지부분과 패드(14a) 외곽에 절연물질(17)로 코팅되어 있다.4 is a perspective view showing the wire bonding structure of the present invention. A die pad 10 supported by a tie bar 11 and a lead frame having a plurality of internal leads 12a are provided, and the semiconductor chip 14 is mounted on the die pad 10. It is. A bonding wire 15 is connected between the pad 14a and the inner lead 12a of the semiconductor chip 14. The bonding wire 15 is ball bonded to the inner lead 12a, and stitch bonding is made to the pad 12a. Since stitch bonding is made on the pad 14a, there is a possibility of a short circuit at the edge of the bonding wire 15 and the pad 14a. In order to prevent this, the edge portion of the semiconductor chip 14 and the outer surface of the pad 14a are coated with an insulating material 17.

또한, 멀티칩 본딩시, 즉 한 반도체 칩 패드와 다른 반도체 칩 패드 간을 본딩 와이어로 연결할 경우에도 상기 각 반도체 칩 패드 외곽에 절연물질을 코팅함으로써 와이어 처짐에 의한 단락 불량을 방지할 수 있다. 알루미늄(Al) 또는 그 합금으로 형성된 패드(14a)에는 스티치본딩에 의한 데미지를 줄일 수 있도록 배리어 메탈을 형성시킬 수도 있다.In addition, in the case of multi-chip bonding, that is, even when connecting one semiconductor chip pad and another semiconductor chip pad with a bonding wire, an insulation material may be coated on the periphery of each semiconductor chip pad to prevent short circuit defects due to sagging wires. The pad 14a formed of aluminum (Al) or an alloy thereof may be formed with a barrier metal to reduce damage caused by stitch bonding.

이와 같은 구성을 갖는 이 발명에 따른 반도체 패키지의 제조방법을 설명한다.The manufacturing method of the semiconductor package which concerns on this invention which has such a structure is demonstrated.

먼저, 다이접착 공정전에 와이어 처짐에 의한 단락 불량을 방지할 수 있도록 반도체 칩의 패드(14a) 주위에 폴리이미드 등의 절연물질(17)로 코팅한다.First, before the die bonding process, an insulating material 17 such as polyimide is coated around the pad 14a of the semiconductor chip to prevent a short circuit defect due to wire sag.

절연물질(17) 코팅이 완료된 반도체 칩(14)을 통상의 제조방법으로 다이 접착공정을 실시한다.The die bonding process is performed on the semiconductor chip 14 having the insulating material 17 coated thereon by a conventional manufacturing method.

상기 절연물질(17)이 코팅된 반도체 칩(14)이 다이패드(10)에 접착된 리드 프레임을 히터블록(Heater block)위에 올려놓고, 190∼300℃ 정도 가열되면 캐필러리(도시하지 않음)내에 있는 금(Au) 와이어의 끝에 전기 스파크로 볼(Ball)을 형성하여, 상기 볼을 캐필러리가 내부리드(12a)에 일정한 압착력으로 압착시켜 1차 볼본딩을 실시한다. 이때, 캐필러리 위에 있는 와이어 클램프는 개방되어 있는 상태가 된다. 와이어 재료로서 금(Au) 대신 금(Au) 합금계, 구리(Cu) 또는 구리(Cu) 합금계 등을 이용할 수 있다.When the semiconductor chip 14 coated with the insulating material 17 is placed on the heater block, the lead frame bonded to the die pad 10 is heated, and the capillary (not shown) is heated to about 190 to 300 ° C. The ball is formed with an electric spark at the end of the Au wire in the inside, and the ball is pressed by the capillary with a constant pressing force on the inner lead 12a to perform primary ball bonding. At this time, the wire clamp on the capillary is in an open state. Instead of gold (Au), a gold (Au) alloy system, a copper (Cu), or a copper (Cu) alloy system may be used as the wire material.

상기 내부리드(12a)상에 1차 볼본딩을 실시한 후, 계속해서 캐필러리를 수직상승시켰다가 수평하강을 하여 패드(14a)로 루핑 오퍼레이션을 실시하고, 캐필러리를 패드(14a)에 2차로 스티치본딩을 실시한다. 2차 스티치본딩을 실시할 때에는 와이어 클램프가 닫혀있어 와이어를 단락(??)시켜야 하며 이렇게 함으로써 본딩 1사이클이 이루어진다.After the first ball bonding on the inner lead 12a, the capillary is vertically raised and then horizontally lowered to perform a looping operation with the pad 14a, and the capillary is applied to the pad 14a. Second stitch bonding is performed. When performing the second stitch bonding, the wire clamp is closed to short-circuit the wire, which results in one cycle of bonding.

상기와 같은 방법으로 와이어본딩이 완료된 제품은 몰드공정을 거쳐 박형 패키지를 완성한다.The wire-bonded product is completed in the same manner as described above to complete the thin package.

제 5 도에서는 종래의 TSOP의 단면도와 이 발명의 실시예에 따른 TSOP의 단면도를 동시에 나타낸 도면이다. 부호 P1은 이 발명에 따른 패키지이고, 도면부호 P2는 종래의 패키지이다. 또한, I는 패키지 탑에서 본딩 와이어까지의 길이이고, G는 칩에서 본딩 와이어까지의 길이이다. 이 도면에서 종래기술에 비해 이 발명 기술에 의한 패키지의 루프 높이가 매우 낮아짐을 쉽게 알 수 있다.5 is a cross-sectional view of a conventional TSOP and a cross-sectional view of a TSOP according to an embodiment of the present invention. Reference numeral P1 denotes a package according to the present invention, and reference numeral P2 denotes a conventional package. In addition, I is the length from the package top to the bonding wire, and G is the length from the chip to the bonding wire. In this figure it can be easily seen that the loop height of the package according to the present invention is very low compared to the prior art.

실질적으로 루프 높이는 종래의 경우 보다 높아야 안정된 본딩을 실현할 수 있으나, 내부리드(12a)와 반도체 칩(14)의 높이를 고려할 경우 패키지 탑면에서 와이어 루프 절곡부위까지의 길이(I)를 50㎛이상 낮춤으로써 초박형 패키지를 실현할 수 있다.Substantially, the loop height must be higher than the conventional case to realize stable bonding. However, considering the height of the inner lead 12a and the semiconductor chip 14, the length I from the top of the package to the wire loop bent portion is reduced by 50 μm or more. As a result, an ultra-thin package can be realized.

이상과 같이 이 발명에 의하면, 칩패드에는 스티치본딩을 실시하고, 내부리드에는 볼본딩을 실시함으로써 종래의 본딩장비를 이용하여 TSOP, TQFP 등의 박형패키지를 제조할 수 있다.As described above, according to the present invention, the chip pad is subjected to stitch bonding, and the inner lead is ball bonded to manufacture thin packages such as TSOP and TQFP using conventional bonding equipment.

Claims (7)

리드 프레임의 다이패드상에 접착제를 매개하여 반도체 칩이 접착되고, 상기 반도체 칩의 다수개의 패드와 다수개의 내부리드간은 본딩 와이어로 결선되고, 상기 본딩 와이어 접속 후에 내부리드를 포함하는 상기 반도체 칩이 중앙에 위치하도록 상기 내부리드까지 성형수지로 몰딩되며, 몰딩되지 않은 외부리드들은 하향절곡되게 구성된 반도체 패키지에 있어서, 상기 본딩 와이어는 루프 높이를 낮게 하기 위하여 볼본딩이 내부리드에 형성되고, 스티치본딩이 상기 패드에 이루어지며, 상기 반도체 칩의 에지부분과 패드의 외곽에 와이어 처짐에 의한 단락 방지를 위하여 절연물질이 코팅된 것을 특징으로 하는 반도체 패키지.The semiconductor chip is bonded onto the die pad of the lead frame by an adhesive, and the plurality of pads and the plurality of inner leads of the semiconductor chip are connected by a bonding wire, and the semiconductor chip includes an inner lead after the bonding wire is connected. In the semiconductor package is formed by molding resin to the inner lead to be located in the center, the unmolded outer lead is bent downward, the bonding wire is formed by ball bonding on the inner lead to lower the loop height, stitch Bonding is made to the pad, the semiconductor package, characterized in that the insulating material is coated on the edge portion of the semiconductor chip and the outer edge of the pad to prevent short circuit due to wire sag. 제1항에 있어서, 상기 절연물질은 폴리이미드(Polyimide)인 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the insulating material is polyimide. 제1항에 있어서, 상기 본딩 와이어의 재료는 금(Au), 구리(Cu) 또는 각각의 합금들 중 어느 하나인 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the material of the bonding wire is one of gold (Au), copper (Cu), or respective alloys. 다수의 내부리드가 형성된 리드 프레임의 다이패드상에 다수개의 패드를 갖는 반도체 칩을 접착시키는 공정과, 캐필러리에 장착되어 있는 소정재질의 본딩 와이어의 끝단에 볼을 형성하는 공정과, 상기 내부리드상에 1차 볼본딩을 실시한 후 캐필러리를 수직상승시켰다가 수평하강을 하여 상기 패드에 2차로 스티치본딩을 실시하는 것을 1사이클로본딩 해당 수만큼 반복하는 와이어 본딩공정과, 상기 반도체 칩, 본딩 와이어 및 리드 프레임을 봉합시켜 패키지 몸체를 형성하는 공정을 포함하는 반도체 패키지 제조방법에 있어서, 상기 반도체 칩을 접착시키는 공정전에 와이어 처짐에 의한 단락 방지를 위하여 상기 패드 주위에 절연물질을 코팅하는 공정을 더 포함하는 것을 특징으로 하는 반도체 패키지 제조방법.Bonding a semiconductor chip having a plurality of pads to a die pad of a lead frame having a plurality of inner leads; forming a ball at an end of a bonding wire of a predetermined material attached to the capillary; After performing the first ball bonding on the capillary vertically, and then horizontally descending, the second and second bond bonding to the pad by the cyclobonding process for repeating the corresponding number of times, the semiconductor chip, the bonding A method of manufacturing a semiconductor package including a step of sealing a wire and a lead frame to form a package body, wherein a step of coating an insulating material around the pad to prevent a short circuit caused by sagging wire before the semiconductor chip is bonded. The semiconductor package manufacturing method characterized in that it further comprises. 제4항에 있어서, 상기 절연물질은 폴리이미드(Polyimide)로 형성되는 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 4, wherein the insulating material is formed of polyimide. 제4항에 있어서, 스티치본딩 데미지를 줄이기 위하여 상기 반도체 칩을 접착시키는 공정전에 상기 패드에 배리어 메탈을 형성하는 공정을 더 포함하는 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 4, further comprising forming a barrier metal on the pad before the bonding of the semiconductor chip to reduce stitch bonding damage. 제4항에 있어서, 상기 와이어 본딩 공정시 본딩 와이어는 금(Au), 구리(Cu) 또는 각각의 합금들 중 어느 하나로 형성되는 것을 특징으로 하는 반도체 패키지 제조방법.The method of claim 4, wherein the bonding wire is formed of one of gold (Au), copper (Cu), and respective alloys during the wire bonding process.
KR1019920027592A 1992-12-31 1992-12-31 Semiconductor package and manufacturing method thereof KR100243555B1 (en)

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US7067413B2 (en) 2003-09-04 2006-06-27 Samsung Electronics Co., Ltd. Wire bonding method, semiconductor chip, and semiconductor package

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KR20010035456A (en) * 2001-02-15 2001-05-07 최성규 Semiconductor light emitting package and the methods thereof
KR20040023852A (en) * 2002-09-12 2004-03-20 송기영 luminous element and manufacturing method

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JPH04107835A (en) * 1990-08-27 1992-04-09 Matsushita Electric Ind Co Ltd Wire bonding method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812567B2 (en) 2002-11-28 2004-11-02 Samsung Electronics Co., Ltd. Semiconductor package and package stack made thereof
US7067413B2 (en) 2003-09-04 2006-06-27 Samsung Electronics Co., Ltd. Wire bonding method, semiconductor chip, and semiconductor package

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