JPS59169153A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the reliability by increasing the thickness of an interlayer insulating film thicker than the periphery at the part of a metal wiring pattern and extending the edge of a wiring pattern at the periphery, thereby suppressing a crack to occur at the interlayer insulating film. CONSTITUTION:A gate electrode 13 is formed through a gate oxidized film 12 on the surface of a p type silicon substrate 11, n type impurity regions 14, 14 to become source, drain regions and diffused wiring layer are formed, an interlayer insulating film 15 is formed, and an aluminum wiring layer 16 is formed. When the film 15 is etched with fluoric acid etchant, an overhang is extended on the part that the thickness of the film 15 is reduced at the edge of the layer 16 due to side etching. A PSG film 17 is accumulated to obtain a semiconductor device. Thermal stress concentrated at the edge of the layer 16 can be buffered by the film 17, thereby remarkably suppressing a crack to occur at the CVD-SiO2 film 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for applications requiring high reliability under severe temperature environments, and a method for manufacturing the same.

[Technical background of the invention]

FIG. 1 is a sectional view showing an example of a conventional semiconductor device.

In the figure, 1 is a p-type (or n-type) silicon substrate. On the surface layer of the silicon substrate 1, there is formed an n-type layer, which will become the source/drain region and diffusion wiring layer of the Mos transistor.
Type (or p-type) impurity regions 2, 2 are formed.

A gate oxide film 3 is formed on the surface of the silicon substrate l,
Furthermore, a polycrystalline silicon pattern 4 is formed thereon. The polycrystalline silicon layer 4 is used as a gate electrode and other interconnections on the channel region as shown.

A silicon oxide film 5 is deposited on the polycrystalline silicon R-turn 4 over the entire surface of the substrate l, and a metal wiring/pattern 6 made of aluminum or the like is formed on the silicon oxide film 5. . That is, the silicon oxide film 5 is formed between the first wiring layer of polycrystalline silicon turns 4 and the metal wiring ξ turns 6.
It functions as an interlayer insulating film that separates the second conductive wire from the second conductive wire. Furthermore, a PSG film (phosphosilicate glass film) 7 is applied as a passivation film from above the metal wiring pattern 6.
is completely covered.

As described above, recent highly integrated semiconductor devices employ a two-layer wiring structure in which the polycrystalline silicon layer 4 and the metal wiring pattern 6 are insulated by the silicon oxide film 5 serving as the glabellar insulating film.

Note that if the silicon oxide film 5 is used alone as an interlayer insulating film, a step will be created at the polycrystalline silicon groove 4, and the metal wiring line 6 formed thereon will overlap with the polycrystalline silicon groove 4. So-called step breakage is likely to occur in the alternating portions. In order to prevent such step breaks, a silicate glass film with a relatively low melting point, such as a PSG film or a BSG film (borosilicate glass film), is further stacked on top of the silicon oxide film 5, and then the silicate glass film is An interlayer insulating film whose surface is smoothed by melting it at a high temperature has also been used.

[Problems with background technology]

However, in a semiconductor device with a two-layer wiring structure as shown in FIG. 1, the coefficient of linear expansion is considerably different between the silicon oxide film 5 as an interlayer insulating film and the metal wiring nosoturn 6 formed thereon. Therefore, when a thermal load is applied, cracks 8 occur in the silicon oxide film 5 due to thermal stress generated between the two.
There is a problem in that it causes defects such as an increase in leakage current or inoperability. Particularly, semiconductor devices mounted on vehicles, for example, are used under severe temperature load conditions and are therefore prone to defects due to the above-mentioned causes. This problem,
A similar problem occurs when a PSG film is melted on top of the silicon oxide film 5 to smooth the surface and an interlayer insulating film is used. This is because the PSG film itself, which is formed using low-pressure CVD, has a linear expansion coefficient relatively close to that of metal wiring (turn 6), but the melted PSG film is densified and has a linear expansion coefficient that is relatively close to that of metal wiring (turn 6). This is because silicate glass films other than PSG films have this tendency even more.

Incidentally, the crack 8 that occurs in the silicon oxide film 5 occurs along the edge of the metal wiring pattern 6.

This is because the thermal stress is concentrated in this portion.

In particular, the end face of the metal wiring layer 6 patterned by wet etching has a tapered shape as shown in FIG. It is becoming more likely to occur.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a highly reliable semiconductor device having a structure that can significantly suppress cracks occurring in an interlayer insulating film in a semiconductor device with a two-layer wiring structure, and a method for manufacturing the same. It is.

[Summary of the invention]

In the semiconductor device according to the present invention, for example, in a semiconductor device having a two-layer wiring structure as shown in FIG. It is characterized in that the periphery of the turn 6 is also thickened, and the edge of the metal wiring pattern 6 is formed so as to extend over the thin surrounding glabellar insulating film 5.

Due to this feature, the edge of the metal wiring or turn 6 does not come into contact with the interlayer insulating film 5, and the PGG film 7 as a passivation film is interposed between the two. The coefficient of linear expansion of this unmelted PSG M7 is the interlayer insulating film 5
Since it is close to the linear expansion coefficient of the metal wiring pattern 6 compared to
Due to the buffering effect of the PSG film 7, the thermal stress applied to the interlayer insulating film 5 is significantly reduced.

In the method for manufacturing a semiconductor device according to the present invention, for example, when manufacturing a semiconductor device with a two-layer wiring structure as shown in FIG. 1, a metal wiring pattern 6 is formed on an interlayer insulating film 5, and then a PSG film 7 is deposited. This method is characterized in that the silicon oxide film 7 is partially etched using the metal wiring/turn 6 as a mask.

Due to this partial etching, the interlayer insulating film 5 becomes thicker in the region of the metal wiring pattern 6 and around it, and at this time, side etching occurs under the ends of the metal wiring pattern 6.

Therefore, the edge portion of the metal wiring pattern 6 does not come into close contact with the interlayer insulating film 5, but extends over the thinner surrounding interlayer insulating film, resulting in a structure unique to the semiconductor device of the present invention. is formed.

[Embodiments of the invention]

An embodiment of the semiconductor device according to the present invention will be described below with reference to FIGS. 3(A) to 3(D), together with a method for manufacturing the same.

(i) First, the state shown in FIG. 3(A) is obtained according to the usual method of manufacturing an MO8 type semiconductor device using polycrystalline silicon oxide processing.

That is, a field oxide film (not shown) is selectively formed on the surface of the p-type silicon substrate 110, and the SDG region (source/drain/dirt region) and the diffusion wiring region surrounded by the silicon oxide film are separated. Next, after forming a thermal oxide film on the entire surface of the SDG region and the diffusion wiring region, CV
A polycrystalline silicon layer is deposited over the entire surface by method D. Subsequently, the polycrystalline silicon layer and the thermal oxide film are sequentially /F-turned to form a dirt electrode 13 on the intended channel portion via the dirt oxide film 12, and at the same time, other polycrystalline silicon wiring layers are formed. form. Next, phosphorus is selectively diffused using the field oxide film and dirt electrode 13 as a mask to form n-type impurity regions 14.14 that will become source/drain regions and diffusion wiring layers in a self-aligned manner, and then CVD S is applied to the entire surface. i Deposit an O2 film and a BPSG film in sequence, and then melt the BPSG film to a film thickness of 1200 mm.
An interlayer insulating film No. 5 of 0X is formed.

(11) Next, after drilling the necessary contact holes,
Aluminum with a thickness of 10,000 to 15. OO and OX are deposited on the entire surface and further patterned to form an At wiring layer 16 (as shown in FIG. 3(B)).

G11) Next, using a hydrofluoric acid-based etching solution and using the aluminum wiring layer 16 as a mask, the interlayer insulating film 15 is etched to a thickness of 200 mm.
0-3000X etching (as shown in Figure 3 (C))
.

At this time, side etching occurs below the edge of the aluminum wiring layer 16, so that the aluminum wiring layer 16
The edge portion of the interlayer insulating film J5 does not come into close contact with the interlayer insulating film J5, but instead protrudes like an eave over the thinner part of the film.

Ov) Next, a film with a thickness of 10
After depositing a PSG film 17 of 000 to 20,000x, a bonding window (not shown) is opened on the bonding pad to obtain the semiconductor device of FIG. 3(D).

The thus obtained semiconductor device shown in FIG. 3) has a characteristic structure of the present invention. That is, the edge of the aluminum wiring layer 16 is not in direct contact with the interlayer insulating film 15, and the coefficient of linear expansion is approximately in the middle between them. Intervening. Therefore, the thermal stress concentrated at the edge of the aluminum wiring layer 16 is relaxed by the PSG film 17. , CVD-8102 can avoid direct load on the interlayer insulating film.
Cracks occurring in the membrane can be significantly suppressed. Furthermore, when depositing the PSG film 17 from above the aluminum wiring layer 16, a void may be created under the overhanging part of the aluminum wiring layer 16. There is no particular problem.

Reliability test against thermal environment changes: The semiconductor device obtained in the above example and the conventional semiconductor device manufactured in the same manner as in the example except that the etching shown in FIG. 3(C) was not performed. A thermal cycle test was conducted on both of them according to condition B of the US military standard A883 B 1010.2, and the failure rate was investigated. Curve A in FIG. 4 shows the results for the example product, and curve (B) shows the results for the conventional product.

As shown in the results, the reliability of the example product was significantly improved compared to the conventional product.

Although the above embodiment relates to an MO8 type semiconductor device, the present invention can be similarly applied to a bipolar type semiconductor device as long as it has a similar two-layer wiring structure.

Further, the first layer wiring pattern may be formed using high melting point metal silicide such as molybdenum silicide in addition to polycrystalline silicon.

〔Effect of the invention〕

As detailed above, according to the present invention, remarkable effects such as suppressing cracks occurring in an interlayer insulating film in a semiconductor device having a two-layer wiring structure and improving reliability can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional semiconductor device, FIG. 2 is an explanatory diagram showing the problems, and FIGS. The cross-sectional views shown in sequence, and FIG. 4, are graphs showing a comparison of the failure rate in a thermal cycle test conducted on the semiconductor device of the present invention and the conventional semiconductor device. 1 No. . . P-type silicon substrate, 12 . f-turn, 17- PSG film. Figure 3: Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) A semiconductor substrate on which an impurity region is formed, a first-layer wiring pattern formed on the semiconductor substrate via an insulating film, and an interlayer insulating film provided to cover the first-layer wiring pattern. , a metal wiring/flat turn formed on the glabellar insulating film, and a phosphosilicate glass film as a noxivation film deposited on the metal wiring pattern, and the film of the interlayer insulating film The thickness of the metal wiring pattern (by making the metal wiring pattern thicker than the surrounding area at the turn part, and by making the end At part of the metal wiring pattern protrude over the thin surrounding interlayer insulating film), A semiconductor device characterized in that the phosphosilicate glass film is interposed between an edge of a metal wiring/guttern and an interlayer insulating film. (2) On the semiconductor substrate where the impurity region is formed
After forming a first layer wiring pattern via an insulating film, forming an interlayer insulating film covering the entire surface. A step of forming a metal wiring/intermediate turn on the interlayer insulating film, a step of partially etching the interlayer insulating film using the metal wiring/turn as a mask, and etching the entire surface with phosphorus as a motherboard Mh. 1. A method for manufacturing a semiconductor device, comprising the step of depositing a silicate glass film.