JPS59161844A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the outer dimension and thus increase the density in mounting by a method wherein a cap is made as a common cap, when a plurality of chip carrier type semiconductor elements are sealed with said cap when mounting on a flat pin type substrate. CONSTITUTION:An Si chip 5 is fixed on a ceramic substrate 4, and electrode terminals provided on said chip are connected to a conductive layer 6 formed in the periphery of the substrate 4 by means of wires 7, thus being formed as the chip carrier type semiconductor element 3. Next, when a plurality of these elements 3 are mounted and formed into a multi-chip type semiconductor devide, these elements 3 are loaded at fixed intervals on the ceramic substrate 1 provided with many flat type lead pins 2 on the under surface of the periphery and conducted to the inner wiring of the substrate. Thereafter, while covering all these elements 3, they are hermetically sealed by placing the common cap 8 made of a ceramic material over the substrate 1. Thus, it is avoided to provide a hermetic sealing cap for every element 3, and accordingly the number of processes is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and more particularly to a technique particularly effective for a multi-chip type semiconductor device formed by mounting a plurality of so-called chip carrier type semiconductor devices.

[Background Art] In this type of multi-chip semiconductor device, for example, each chip carrier type semiconductor device (hereinafter referred to as a chip carrier) mounted on a ceramic substrate is hermetically sealed in a pan cage. This is the method normally considered.

However, in this case, it is necessary to hermetically seal each chip carrier, which increases the number of steps required for hermetically sealing.

Further, for example, if the lead pins provided on the ceramic substrate for mounting are of a flat pin type, it is required to reduce the mounting area of the chip carrier by the amount that the lead pins protrude around the substrate. In this method, there is no choice but to reduce the external dimensions of each chip carrier, and in that case, problems arise such as, for example, the memory chip cannot be mounted inside the chip carrier.

[Object of the Invention] An object of the present invention is to provide a semiconductor device whose external dimensions can be reduced and which can be mounted at a higher density.

Another object of the present invention is to provide a semiconductor device that can reduce the number of steps required for hermetic sealing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief outline of typical inventions disclosed in this application is as follows.

That is, by commonly sealing a plurality of chip carrier type semiconductor elements, it is possible to reduce the external dimensions, achieve high density packaging, and reduce the number of times of sealing.

[Embodiment] FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view showing a chip carrier type semiconductor element that can be used in the present invention.

In this embodiment, a large number of flat lead pins 2 are provided on the lower surface of the periphery of a substrate 1 made of, for example, ceramic, and each lead pin is electrically connected to internal wiring (not shown) of the substrate 1.

On the other hand, a plurality of chip carrier type semiconductor elements (chip carriers) 3 are mounted on the upper surface of the substrate 1, forming a so-called multi-chip type semiconductor device structure. For example, as shown in an enlarged view in FIG. 2, each chip carrier 3 has a silicon chip 5 mounted on a ceramic base 4, and wires 7 between the bonding pads of the silicon chip 5 and the conductive layer 6 of the ceramic base 4. It is possible to use a configuration in which the conductive layer 6 is electrically connected and further conductively connected to the wiring of the substrate 1, and there is no need to perform airtight sealing for each chip carrier 3 as described later.

Further, in this embodiment, the camp 8 for hermetically sealing all the chip carriers 3 in common as a camp for hermetically sealing the pan cage is made of, for example, a ceramic material, and its open end (lower end ) is hermetically sealed by adhering to the upper surface of the outer peripheral edge of the substrate 1 with a sealing material 9 such as low melting point glass.

Therefore, according to this embodiment, since the plurality of chip carriers 3 constituting a multi-chip semiconductor device are commonly hermetically sealed with only one camp 8,
It is not necessary to perform hermetic sealing for each chip carrier 3, and the number of steps for hermetic sealing can be greatly reduced.In addition, there is no need for sealing allowance for each chip carrier 3, so the external shape of the balance carrier 3 itself Dimensions can be reduced, and higher density packaging is possible within the same mounting area.

Further, an axial type can also be used as the lead pin 2 of the substrate 1.

[Effect (1): By providing a cap that commonly hermetically seals a plurality of semiconductor elements, the number of steps for hermetically sealing can be reduced.

(2) By providing a camp for hermetically sealing a plurality of semiconductor elements in common, sealing allowance for each semiconductor element becomes unnecessary, and it is possible to miniaturize the semiconductor device and achieve high-density packaging.

(3) It is also possible to reduce costs by using the above (1) and (2).

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in addition to sealing all semiconductor elements with one cap, when mounting different types of semiconductor elements, it is necessary to seal multiple semiconductor elements together in separate camps for each type. It is also possible to do the following.

[Field of Application] In the above description, the invention made by the present inventor was mainly applied to a multi-chip semiconductor device consisting of a chip carrier type semiconductor device, which is the field of application which is the background of the invention, but the present invention is not limited thereto. It can also be used, for example, in cases where other types of semiconductor elements are included.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a partially cross-sectional view showing an example of a chimbu carrier type semiconductor element that can be used in the present invention. ■... Substrate, 2... Lead bin, 3... Chimp carrier type semiconductor element, 4... Ceramic base, 5...
・Silicon chip, 6... Conductive layer, 7... Wire,
8...Camp, 9...Sealing material. Figure 1 Z Figure 2

Claims (1)

[Scope of Claims] 1. A semiconductor device comprising a plurality of semiconductor elements mounted on a substrate, characterized in that a cap is provided for commonly sealing the plurality of semiconductor elements. 2. The semiconductor device according to claim 1, wherein the semiconductor element is a chip carrier type semiconductor element. 2. The semiconductor device according to claim 1, wherein the 3° substrate is a flat pin type substrate.