JPS59161830A - 混成集積回路 - Google Patents
混成集積回路Info
- Publication number
- JPS59161830A JPS59161830A JP58036959A JP3695983A JPS59161830A JP S59161830 A JPS59161830 A JP S59161830A JP 58036959 A JP58036959 A JP 58036959A JP 3695983 A JP3695983 A JP 3695983A JP S59161830 A JPS59161830 A JP S59161830A
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- substrate
- integrated circuit
- ceramic substrate
- paths
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
本発自は、セラミック話板上に形成された薄膜集積回路
において、クロス・オーバーを容易にし、小形化をCi
J能にした混成集積回路に関する。
において、クロス・オーバーを容易にし、小形化をCi
J能にした混成集積回路に関する。
従来、薄膜楽積回路では、クロスeオーバーにはワイヤ
ホンディングによるワイヤでのクロス参オーバー、また
は、ハンダ付けによる蛇属縁でのクロス・オーバーなど
の方法か何われでいた。しかし、上dビワイヤポンディ
ングによるワイヤでは、長い距離をクロス−オーバー芒
せるとワイヤの強度が劣化して、信粗注がおちてくる。
ホンディングによるワイヤでのクロス参オーバー、また
は、ハンダ付けによる蛇属縁でのクロス・オーバーなど
の方法か何われでいた。しかし、上dビワイヤポンディ
ングによるワイヤでは、長い距離をクロス−オーバー芒
せるとワイヤの強度が劣化して、信粗注がおちてくる。
牙た、上記ハンダ付り−により、釡属紛を使用してクロ
ス・オーバーをさせる場合は、金属線をハンダ付けする
為のパッドを作る必資があり、小形化には同いていない
。′!た、ハンダディッグ、ハンタリフロー等の工程か
ない場合は、工程を坩ず必安かある。
ス・オーバーをさせる場合は、金属線をハンダ付けする
為のパッドを作る必資があり、小形化には同いていない
。′!た、ハンダディッグ、ハンタリフロー等の工程か
ない場合は、工程を坩ず必安かある。
本発明の目的は、このような従来のクロス・オーバーの
問題を改善すると同時に、小形化を町「しならしめた混
成集積回路を提供することにある。
問題を改善すると同時に、小形化を町「しならしめた混
成集積回路を提供することにある。
本発明の混取果tjt薗鮎は、薄膜巣偵回帖か形成され
たセラミック基板上に、薄膜または厚膜で形J収された
回路パターンを有する絶Ha板を搭載し、上記セラばツ
ク基板の導体部と上記上うεツクき板上に搭載された絶
縁量板上の導体部をワイヤホンディングにより電気的に
接続した構成をゼする。
たセラミック基板上に、薄膜または厚膜で形J収された
回路パターンを有する絶Ha板を搭載し、上記セラばツ
ク基板の導体部と上記上うεツクき板上に搭載された絶
縁量板上の導体部をワイヤホンディングにより電気的に
接続した構成をゼする。
本発明によれは、上記セラミック第、放上に搭載される
絶縁基板を通して、容易にクロス・オーバ−を行うこと
が可能になると同時に、上記絶縁基板上に薄p#または
厚膜で回路パターンを形成させて置くことができるので
、よシ小形化をはかることができる。
絶縁基板を通して、容易にクロス・オーバ−を行うこと
が可能になると同時に、上記絶縁基板上に薄p#または
厚膜で回路パターンを形成させて置くことができるので
、よシ小形化をはかることができる。
次に、本発明を実施例について説明する。
第1図(a)は本発明の一実施例の部分平面図、同図(
b)は同図(a)のA−A断面図である。第1図(a)
。
b)は同図(a)のA−A断面図である。第1図(a)
。
rb)において、セラミック基板1上に薄膜によ多回路
パターンを形成する。次に薄膜によ)回路パターンが形
成された絶縁基板4を上記セラミック基板1上の4電路
3.3の一部を覆って、非導電性接着剤6で搭載する。
パターンを形成する。次に薄膜によ)回路パターンが形
成された絶縁基板4を上記セラミック基板1上の4電路
3.3の一部を覆って、非導電性接着剤6で搭載する。
次にセラミック基板1上の薄膜回路の導電路2,2.・
・・と上記絶縁基板4上の薄膜回路の導電路5,5とを
ワイヤ7で接続する。
・・と上記絶縁基板4上の薄膜回路の導電路5,5とを
ワイヤ7で接続する。
上述の本発明混成集積回路では、セラミック基ることに
より小形化をはかることが可能となる。
より小形化をはかることが可能となる。
【図面の簡単な説明】
第1図(a)は本発明の一実施例の部分平面図、同図(
b)は同図(a)のA−A断面図でめる。 1・・・・・・セラミック基板、2・・・・・・セラミ
ック基板上の横方向導電路、3・・・・・・セラミック
基板上の縦方向4電路、4・・・・・・セラミック基板
上の絶縁基板、5・・・・・・絶縁基板上の導電路、6
・・・・・・非導電性接着剤、7・・・・・・ボンディ
ングワイヤ。
b)は同図(a)のA−A断面図でめる。 1・・・・・・セラミック基板、2・・・・・・セラミ
ック基板上の横方向導電路、3・・・・・・セラミック
基板上の縦方向4電路、4・・・・・・セラミック基板
上の絶縁基板、5・・・・・・絶縁基板上の導電路、6
・・・・・・非導電性接着剤、7・・・・・・ボンディ
ングワイヤ。
Claims (1)
- ?Ig膜集槓回路か形成されたセラミック基板上に、薄
膜または厚膜で形成妊れた回路パターンをMする絶縁#
板を搭載し、151J記セラミツク基叡の導体部と的m
lセラ< ツク基板上に搭載された絶縁丞板上の導体部
をワイヤボンティングにょシ゛岨気的に接続したことケ
特徴とする混成集積回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58036959A JPS59161830A (ja) | 1983-03-07 | 1983-03-07 | 混成集積回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58036959A JPS59161830A (ja) | 1983-03-07 | 1983-03-07 | 混成集積回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59161830A true JPS59161830A (ja) | 1984-09-12 |
Family
ID=12484279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58036959A Pending JPS59161830A (ja) | 1983-03-07 | 1983-03-07 | 混成集積回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59161830A (ja) |
-
1983
- 1983-03-07 JP JP58036959A patent/JPS59161830A/ja active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH07142669A (ja) | モールド型半導体装置 | |
JPH022842U (ja) | ||
JP3031323B2 (ja) | 半導体装置とその製造方法 | |
JPH0358550B2 (ja) | ||
US3405227A (en) | Multilayer universal printed circuit board | |
JPS59161830A (ja) | 混成集積回路 | |
US6888227B2 (en) | Apparatus for routing signals | |
JPS5954247A (ja) | 電子部品 | |
JPS5884412A (ja) | 積層インダクタ | |
JPH0119395Y2 (ja) | ||
JP2001024143A (ja) | 複合半導体装置 | |
JPS6079750A (ja) | チツプキヤリヤ | |
JP2743524B2 (ja) | 混成集積回路装置 | |
JPS59929A (ja) | 電気回路組立体 | |
JPS5911458Y2 (ja) | 印刷配線板 | |
JPS6141303B2 (ja) | ||
JPH0126108Y2 (ja) | ||
JPH0471260A (ja) | 電子部品 | |
JPH01120890A (ja) | 改造布線を有するプリント配線板 | |
JPH0121639B2 (ja) | ||
JPH0327588A (ja) | 回路基板の製造方法 | |
JPH04225600A (ja) | プリント板ユニットの動作試験器接続方法 | |
JPH0595174A (ja) | フレキシブルプリント配線板 | |
JPH0350889A (ja) | プリント配線基板 | |
JPH0297042A (ja) | 電子部品搭載用基板 |