JPS59157886A - メモリ制御方式 - Google Patents

メモリ制御方式

Info

Publication number
JPS59157886A
JPS59157886A JP58032571A JP3257183A JPS59157886A JP S59157886 A JPS59157886 A JP S59157886A JP 58032571 A JP58032571 A JP 58032571A JP 3257183 A JP3257183 A JP 3257183A JP S59157886 A JPS59157886 A JP S59157886A
Authority
JP
Japan
Prior art keywords
line
data
address
storage device
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58032571A
Other languages
English (en)
Japanese (ja)
Other versions
JPH046985B2 (enExample
Inventor
Makoto Kishi
誠 岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58032571A priority Critical patent/JPS59157886A/ja
Publication of JPS59157886A publication Critical patent/JPS59157886A/ja
Publication of JPH046985B2 publication Critical patent/JPH046985B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58032571A 1983-02-28 1983-02-28 メモリ制御方式 Granted JPS59157886A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58032571A JPS59157886A (ja) 1983-02-28 1983-02-28 メモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58032571A JPS59157886A (ja) 1983-02-28 1983-02-28 メモリ制御方式

Publications (2)

Publication Number Publication Date
JPS59157886A true JPS59157886A (ja) 1984-09-07
JPH046985B2 JPH046985B2 (enExample) 1992-02-07

Family

ID=12362585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58032571A Granted JPS59157886A (ja) 1983-02-28 1983-02-28 メモリ制御方式

Country Status (1)

Country Link
JP (1) JPS59157886A (enExample)

Also Published As

Publication number Publication date
JPH046985B2 (enExample) 1992-02-07

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