JPS5914062A - 二重化共有メモリ制御方法 - Google Patents

二重化共有メモリ制御方法

Info

Publication number
JPS5914062A
JPS5914062A JP57122151A JP12215182A JPS5914062A JP S5914062 A JPS5914062 A JP S5914062A JP 57122151 A JP57122151 A JP 57122151A JP 12215182 A JP12215182 A JP 12215182A JP S5914062 A JPS5914062 A JP S5914062A
Authority
JP
Japan
Prior art keywords
address
shared memory
access
debug
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57122151A
Other languages
English (en)
Japanese (ja)
Other versions
JPH041374B2 (enExample
Inventor
Yoshihiro Miyazaki
義弘 宮崎
Toshiyuki Ide
井手　寿之
Takeshi Kato
猛 加藤
Hiroaki Nakanishi
宏明 中西
Tadaaki Bando
忠秋 坂東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57122151A priority Critical patent/JPS5914062A/ja
Priority to EP83106889A priority patent/EP0099125B1/en
Priority to DE8383106889T priority patent/DE3382041D1/de
Publication of JPS5914062A publication Critical patent/JPS5914062A/ja
Priority to US07/030,266 priority patent/US4783731A/en
Publication of JPH041374B2 publication Critical patent/JPH041374B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/468—Specific access rights for resources, e.g. using capability register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)
JP57122151A 1982-07-15 1982-07-15 二重化共有メモリ制御方法 Granted JPS5914062A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57122151A JPS5914062A (ja) 1982-07-15 1982-07-15 二重化共有メモリ制御方法
EP83106889A EP0099125B1 (en) 1982-07-15 1983-07-13 Multicomputer system having dual common memories
DE8383106889T DE3382041D1 (de) 1982-07-15 1983-07-13 Mehrrechner-system mit zweifach gemeinsamen speichern.
US07/030,266 US4783731A (en) 1982-07-15 1987-03-24 Multicomputer system having dual common memories

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57122151A JPS5914062A (ja) 1982-07-15 1982-07-15 二重化共有メモリ制御方法

Publications (2)

Publication Number Publication Date
JPS5914062A true JPS5914062A (ja) 1984-01-24
JPH041374B2 JPH041374B2 (enExample) 1992-01-10

Family

ID=14828862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57122151A Granted JPS5914062A (ja) 1982-07-15 1982-07-15 二重化共有メモリ制御方法

Country Status (4)

Country Link
US (1) US4783731A (enExample)
EP (1) EP0099125B1 (enExample)
JP (1) JPS5914062A (enExample)
DE (1) DE3382041D1 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3023425B2 (ja) * 1987-10-09 2000-03-21 株式会社日立製作所 データ処理装置
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
US5251308A (en) * 1987-12-22 1993-10-05 Kendall Square Research Corporation Shared memory multiprocessor with data hiding and post-store
US5175839A (en) * 1987-12-24 1992-12-29 Fujitsu Limited Storage control system in a computer system for double-writing
US5065343A (en) * 1988-03-31 1991-11-12 Yokogawa Electric Corporation Graphic display system for process control using a plurality of displays connected to a common processor and using an fifo buffer
JPH01297764A (ja) * 1988-05-25 1989-11-30 Nec Corp プロセッサ
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
AU625293B2 (en) * 1988-12-09 1992-07-09 Tandem Computers Incorporated Synchronization of fault-tolerant computer system having multiple processors
EP0394514B1 (de) * 1989-04-25 1994-07-13 Siemens Aktiengesellschaft Verfahren zur Synchronisation von Datenverarbeitungsanlagen
US5182801A (en) * 1989-06-09 1993-01-26 Digital Equipment Corporation Apparatus and method for providing fast data transfer between multiple devices through dynamic reconfiguration of the memory space of the devices
US5168555A (en) * 1989-09-06 1992-12-01 Unisys Corporation Initial program load control
JPH03185530A (ja) * 1989-12-14 1991-08-13 Mitsubishi Electric Corp データ処理装置
US5295258A (en) * 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
US5203004A (en) * 1990-01-08 1993-04-13 Tandem Computers Incorporated Multi-board system having electronic keying and preventing power to improperly connected plug-in board with improperly configured diode connections
EP0457308B1 (en) * 1990-05-18 1997-01-22 Fujitsu Limited Data processing system having an input/output path disconnecting mechanism and method for controlling the data processing system
JPH04109352A (ja) * 1990-08-29 1992-04-10 Nec Corp オンライン情報処理装置
EP0569969B1 (en) * 1992-05-12 1998-03-04 Nec Corporation Microcomputer having instruction memory storing instructions for reading out internal conditions
US6052801A (en) * 1995-05-10 2000-04-18 Intel Corporation Method and apparatus for providing breakpoints on a selectable address range
US5659679A (en) * 1995-05-30 1997-08-19 Intel Corporation Method and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer system
US5740413A (en) * 1995-06-19 1998-04-14 Intel Corporation Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping
US5621886A (en) * 1995-06-19 1997-04-15 Intel Corporation Method and apparatus for providing efficient software debugging
WO1997011419A2 (en) * 1995-09-08 1997-03-27 Shablamm Computer, Inc. Synchronous multi-port random access memory
GB2329984B (en) * 1997-10-01 2002-07-17 Thomson Training & Simulation A Multi-Processor Computer System
US6292873B1 (en) * 1998-05-22 2001-09-18 Hewlett-Packard Company Dual-ported electronic random access memory that does not introduce additional wait states and that does not cause retransmission of data during shared access
US20150161057A1 (en) * 2013-12-05 2015-06-11 Qualcomm Incorporated System and method for providing client-side address translation in a memory management system
US9606944B2 (en) 2014-03-20 2017-03-28 International Business Machines Corporation System and method for computer memory with linked paths
US12339979B2 (en) * 2016-03-07 2025-06-24 Crowdstrike, Inc. Hypervisor-based interception of memory and register accesses
CN111968693B (zh) * 2020-08-21 2022-08-05 广芯微电子（广州）股份有限公司 一种mcu及mcu调试接口控制方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715298A (en) * 1980-07-02 1982-01-26 Panafacom Ltd Storage protection system for common memory

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573855A (en) * 1968-12-31 1971-04-06 Texas Instruments Inc Computer memory protection
US3763474A (en) * 1971-12-09 1973-10-02 Bell Telephone Labor Inc Program activated computer diagnostic system
US4025903A (en) * 1973-09-10 1977-05-24 Computer Automation, Inc. Automatic modular memory address allocation system
JPS52123137A (en) * 1976-04-09 1977-10-17 Hitachi Ltd Duplication memory control unit
US4231087A (en) * 1978-10-18 1980-10-28 Bell Telephone Laboratories, Incorporated Microprocessor support system
US4387427A (en) * 1978-12-21 1983-06-07 Intel Corporation Hardware scheduler/dispatcher for data processing system
US4354225A (en) * 1979-10-11 1982-10-12 Nanodata Computer Corporation Intelligent main store for data processing systems
US4503491A (en) * 1981-06-29 1985-03-05 Matsushita Electric Industrial Co., Ltd. Computer with expanded addressing capability
US4439830A (en) * 1981-11-09 1984-03-27 Control Data Corporation Computer system key and lock protection mechanism
US4473878A (en) * 1981-11-23 1984-09-25 Motorola, Inc. Memory management unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715298A (en) * 1980-07-02 1982-01-26 Panafacom Ltd Storage protection system for common memory

Also Published As

Publication number Publication date
EP0099125B1 (en) 1990-12-05
US4783731A (en) 1988-11-08
DE3382041D1 (de) 1991-01-17
EP0099125A2 (en) 1984-01-25
EP0099125A3 (en) 1987-04-15
JPH041374B2 (enExample) 1992-01-10

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