JPS59130447A - 電子部品のパツケ−ジ方法 - Google Patents
電子部品のパツケ−ジ方法Info
- Publication number
- JPS59130447A JPS59130447A JP58005465A JP546583A JPS59130447A JP S59130447 A JPS59130447 A JP S59130447A JP 58005465 A JP58005465 A JP 58005465A JP 546583 A JP546583 A JP 546583A JP S59130447 A JPS59130447 A JP S59130447A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- substrate
- outer diameter
- welding base
- welding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Optical Couplings Of Light Guides (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58005465A JPS59130447A (ja) | 1983-01-17 | 1983-01-17 | 電子部品のパツケ−ジ方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58005465A JPS59130447A (ja) | 1983-01-17 | 1983-01-17 | 電子部品のパツケ−ジ方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59130447A true JPS59130447A (ja) | 1984-07-27 |
| JPS6355866B2 JPS6355866B2 (enrdf_load_stackoverflow) | 1988-11-04 |
Family
ID=11611981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58005465A Granted JPS59130447A (ja) | 1983-01-17 | 1983-01-17 | 電子部品のパツケ−ジ方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59130447A (enrdf_load_stackoverflow) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6435938A (en) * | 1987-07-30 | 1989-02-07 | Toshiba Corp | Method of hermetically sealing image sensing element module |
| US8335050B2 (en) | 2007-04-03 | 2012-12-18 | Hitachi Global Storage Technologies, Netherlands B.V. | Disk drive with a solder preform hermetic seal |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0537057U (ja) * | 1991-10-22 | 1993-05-21 | フラツト合成株式会社 | さけます孵化槽用下網 |
-
1983
- 1983-01-17 JP JP58005465A patent/JPS59130447A/ja active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6435938A (en) * | 1987-07-30 | 1989-02-07 | Toshiba Corp | Method of hermetically sealing image sensing element module |
| US8335050B2 (en) | 2007-04-03 | 2012-12-18 | Hitachi Global Storage Technologies, Netherlands B.V. | Disk drive with a solder preform hermetic seal |
| US9412420B2 (en) | 2007-04-03 | 2016-08-09 | HGST Netherlands B.V. | Hermetically sealing a disk drive assembly |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6355866B2 (enrdf_load_stackoverflow) | 1988-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5661089A (en) | Method for making a semiconductor chip package with enhanced thermal conductivity | |
| US5315486A (en) | Hermetically packaged HDI electronic system | |
| US5616958A (en) | Electronic package | |
| US5939783A (en) | Electronic package | |
| CN110012597B (zh) | 一种陶瓷覆铜电路板及其制备方法 | |
| US3105868A (en) | Circuit packaging module | |
| JPS59130447A (ja) | 電子部品のパツケ−ジ方法 | |
| USH629H (en) | Non-destructive semiconductor chip bonding and chip removal | |
| CN110544632B (zh) | 在具有双面腔体的ltcc基板的封装盖板上制作bga焊盘的方法 | |
| JP2004128134A (ja) | セラミック積層基板及びその製造方法 | |
| JPS6016749B2 (ja) | 集積回路用パツケ−ジ | |
| JP2883458B2 (ja) | 混成集積回路用配線板の製造方法 | |
| JPH0430439A (ja) | ベアチップの実装構造 | |
| JPS61270850A (ja) | 半導体チツプ実装用パツケ−ジ | |
| JP2005158821A (ja) | 半導体素子収納用パッケージ及びその製造方法 | |
| KR20240166184A (ko) | 반도체 패키지 및 이의 제조방법 | |
| JPH0458550A (ja) | 半導体装置 | |
| JP2000164757A (ja) | 半導体素子収納用パッケージおよびその実装構造 | |
| JPH065731A (ja) | セラミックパッケージ及び半導体装置 | |
| EP0092019A3 (en) | Improved semiconductor package | |
| JPH07112101B2 (ja) | 混成集積回路用多層配線回路を有するハーメチックパッケージ構造体およびその製造方法 | |
| JPH0629347A (ja) | Tabパッケージ及びその製造方法 | |
| JPH0272696A (ja) | セラミックス回路基板 | |
| JPS5835952A (ja) | 半導体集積回路装置 | |
| JPH05243416A (ja) | 半導体パッケージ |