JPS59129471A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS59129471A JPS59129471A JP336183A JP336183A JPS59129471A JP S59129471 A JPS59129471 A JP S59129471A JP 336183 A JP336183 A JP 336183A JP 336183 A JP336183 A JP 336183A JP S59129471 A JPS59129471 A JP S59129471A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- resistance
- gate
- films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910021471 metal-silicon alloy Inorganic materials 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 230000008018 melting Effects 0.000 claims description 13
- 238000002844 melting Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 5
- 229910020968 MoSi2 Inorganic materials 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 description 11
- 229910045601 alloy Inorganic materials 0.000 description 10
- 239000000956 alloy Substances 0.000 description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の・蛍する技術分野）
本発明け、高融点余興硅化物又は、ＡＩをゲート電極配
線材料として用いた半導体基板上びその製造方法の改良
に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an improvement in a semiconductor substrate using a high melting point entertainment silicide or AI as a gate electrode wiring material and a method for manufacturing the same.
（従来技術とその間囲屯）
近年、多結晶シリコン・ゲート電極を有する半導体装置
の代りにＭｏ％Ｗなど高帥点金属の硅化物のゲート電極
を有する半導体装置が、台頭しつつあみ。その理由は、
多結晶シリコンと比べ約１桁以上抵抗が低く、かつ硅化
物である車から、後の酸化及びその他の熱処理工程にお
いて安定ｆ′Ａ為事である。(Prior art and its surroundings) In recent years, semiconductor devices having gate electrodes made of silicides of high-strength point metals such as Mo%W have been gaining popularity instead of semiconductor devices having polycrystalline silicon gate electrodes. The reason is,
The resistance is about one order of magnitude lower than that of polycrystalline silicon, and since it is a silicide, it has a stable f'A property during subsequent oxidation and other heat treatment steps.
しかしながら金属硅化物のみを用いる場合、その比抵抗
値が、５０〜１００μΩｍであるため、４０００Ａの厚
みにしても１．Ｑ／口均下の抵抗値を得るのは併しい。However, when only metal silicide is used, its specific resistance value is 50 to 100 μΩm, so even if the thickness is 4000A, the resistivity is 1. It is difficult to obtain the resistance value of Q/mouth.
抵抗値の低下を考えると、硅化物で々く金属単一層を用
いる方法が、あるが、耐薬品性、耐酸化性の点で、従来
の多結晶Ｓｉゲートプロセスと互換性が々く、その点で
硅化物より劣る。又、 Ａ１８ ＋ ０２系は、５００
℃程度の熱処理工程において、Ａ１が、ＳｉＯ□を還元
し、自らＡ１□０３を形成する反応のため、ゲート酸化
膜の劣化け、呻けられない。Considering the reduction in resistance value, there is a method of using a single metal layer made of silicide, but it is not compatible with the conventional polycrystalline Si gate process in terms of chemical resistance and oxidation resistance. In this respect, it is inferior to silicide. Also, A18 + 02 series is 500
In the heat treatment process at temperatures of about .degree. C., A1 reduces SiO□ and forms A1□03 by itself, so that no deterioration of the gate oxide film occurs.
又、高錦点金属の低抵抗性を生かすべく工夫もあり、例
えば、耐薬品性、耐酸化性を改善するため、高融点金属
を所望のパターンに加工した後、その上にＳｉ層を堆積
するか又はＳ ｒ Ｈ４などにより金属層の外部を硅化
物化する方法があるが、いずれの方法も後の熱処ｆＩ！
により金属と硅化物が混合し、中間相を形ｒｉ’ｉ シ
、最終的には、高融点金属層本来の長所である低抵抗性
が失われてし壕う。There are also ways to take advantage of the low resistance of high melting point metals. For example, in order to improve chemical resistance and oxidation resistance, after processing a high melting point metal into a desired pattern, a Si layer is deposited on top of it. Alternatively, there is a method of turning the outside of the metal layer into a silicide using S r H4, etc., but both methods require subsequent heat treatment fI!
This causes the metal and the silicide to mix, form an intermediate phase, and ultimately cause the high melting point metal layer to lose its inherent advantage of low resistance.
（発明の目的）
本発明は、ゲート電極もしくは配線の低抵抗化を実現す
ることを目的としている。(Objective of the Invention) The object of the present invention is to realize a reduction in resistance of a gate electrode or wiring.
（発明の概要）
本発明によるＭＩＳ型電界効果トランジスタのゲート１
１ｔ極・配線構造の基本構造は、ゲート絶縁膜上に高一
点金属−８＋合金層及びＡＩを主成分とする金属層との
積層を形成し、これをゲート電極・配線とすることを特
徴とする。高融点金属−Ｓｉ合金層は、従来からある多
結晶Ｓｒプロセスを大きく変可せずに嫡用できるためで
、その合金層上にＡｌ系金属層を積ｔ＠することで、低
抵抗化を実現している。さらに合金層は、ＡＩとゲート
絶縁膜との反応の咀市層の役割も果す。従って合金層の
代りに多結晶Ｓｉで置きか乏、ると、Ａ１／Ｓｉ共晶反
応のためＭＩＳ特性が不安定と々す、代替材料とけたり
えない。(Summary of the invention) Gate 1 of MIS type field effect transistor according to the invention
The basic structure of the 1T electrode/wiring structure is to form a stack of a high point metal-8+ alloy layer and a metal layer mainly composed of AI on the gate insulating film, and use this as the gate electrode/wiring. do. This is because the high melting point metal-Si alloy layer can be used without major changes in the conventional polycrystalline Sr process, and by stacking an Al-based metal layer on top of the alloy layer, lower resistance can be achieved. It has been realized. Furthermore, the alloy layer also serves as a barrier layer for the reaction between the AI and the gate insulating film. Therefore, if polycrystalline Si is used instead of the alloy layer, the MIS characteristics will become unstable due to the A1/Si eutectic reaction, and alternative materials cannot be used.
本発明による製造方法は、高融点金属−Ｓｉ合金層上に
砦化硅素膜を積層させることにより、パターニング後の
酸化性雰囲気熱処理で合金層上に酸化膜が形成すること
を１５目止する。又、熱処理後学化膜の選捩エツチング
を行なうことにより、レジストエ稈を設けること々く、
合金上にＡｌ系金属層とのコンタクトを実現でき、低抵
抗２層ゲート電極・配線が形成される。The manufacturing method according to the present invention prevents the formation of an oxide film on the alloy layer during heat treatment in an oxidizing atmosphere after patterning by laminating a fortified silicon film on the high melting point metal-Si alloy layer. In addition, by selectively etching the chemical film after heat treatment, a resist culm is often provided.
Contact with the Al-based metal layer can be realized on the alloy, and a low-resistance two-layer gate electrode/wiring can be formed.
（発明の実施例）
次に本発明による半導体装置及びその製造方法を第１乃
至第５図を用いて謂、明する。(Embodiments of the Invention) Next, a semiconductor device and a method for manufacturing the same according to the present invention will be described with reference to FIGS. 1 to 5.
本発明による基本的構造を第１図に示す第１図において
Ｓｒ半半導体版板１フィールド酸化膜２及びゲート絶縁
膜３が形成され、その上にゲート電極・配線として、高
融点金Ｆ％−８ｉ合金層４及びＡ１を主成分とした金属
層５の積層導電膜が形成されている。The basic structure according to the present invention is shown in FIG. 1. In FIG. 1, an Sr semi-semiconductor plate 1 field oxide film 2 and a gate insulating film 3 are formed, and a high melting point gold F%- A laminated conductive film including an 8i alloy layer 4 and a metal layer 5 mainly composed of A1 is formed.
次に高融点金Ｊｉ％Ｓｉ合金とＡ１系金属の２１＠電極
・配線を実現すべき製造方法を第２図〜第５図に示す。Next, a manufacturing method for realizing 21@ electrodes/wirings made of a high melting point gold Ji%Si alloy and an A1 metal is shown in FIGS. 2 to 5.
第２図においてＰ型（又はｎ型）Ｓｉ基板１に７０００
Ａ−’のフィールド酸化膜２及び２０ＯＡ’のゲート酸
化膜をを形成した後、例えば、約２ＯｎＯＡ’の高融点
金Ｒ−８ｉ合金、例えば、Ｍｏ Ｓ ＋ ２膜４及び１
０００Ａ’窒化硅素膜５を被着し、フォトレジストを塗
布１〜、所望のパターン６を形成した後、レジストをマ
スクとして９化硅素ｉｔα５及びＭｏ５ｔ２膜４を反応
性イオンエツチングにより第２図のように加工した後、
フォトレジストを除去し、ソース及びドレイン領域のゲ
ート酸化膜を除去し、第３図のように９化素膜５及びＭ
ｏ Ｓ Ｉ ２膜４をマスクとし、イオン注入法により
Ａｓを４ＱＫｅＶにて３Ｘ１０ ｃｍ 注入し、ソ
ース及びドレイン７を形成した移、第４図において乾燥
酸素雰囲気にて１０００℃１０分の酸化を行ないソース
及びドレイン上に酸化膜８を、ＭｏＳｉ２膜の側壁に酸
化膜９を形成し、ＭＯ８１２上の窒化硅素膜を除去し、
ＡＩ瞭を約２０ｎＯＡ’被着し、写真食刻法によりｖＪ
５ｒＩソ１のようにＮｆ ｏ Ｓ ＋ ２膜４の上にＡ
１１１α１０を形成する。以十の方法を用いれば、ゲー
ト市、極とソース又は、ドレイ／との耐圧不向の事故も
少々く、低抵抗のゲート電極・配線が実現上れる。この
方法により字句したゲート配線材料のシート抵抗値１寸
、約０．１Ω／口であり、従来の高融点金網硅化物単一
に比べ１桁以上低抵抗化される。In Fig. 2, a P-type (or n-type) Si substrate 1 has a
After forming the field oxide film 2 of A-' and the gate oxide film of 20 OA', for example, a high melting point gold R-8i alloy of about 2 On OA', for example, Mo S + 2 films 4 and 1 are formed.
000A' After depositing a silicon nitride film 5, applying photoresist 1 to 6, and forming a desired pattern 6, the silicon 9ide itα5 and Mo5t2 films 4 are etched by reactive ion etching using the resist as a mask as shown in FIG. After processing into
The photoresist is removed, the gate oxide film in the source and drain regions is removed, and the 9-oxide film 5 and the M9 film are removed as shown in FIG.
o Using the SI 2 film 4 as a mask, As was implanted to a thickness of 3×10 cm at 4Q KeV by ion implantation to form the source and drain 7. Oxidation was performed at 1000° C. for 10 minutes in a dry oxygen atmosphere as shown in FIG. An oxide film 8 is formed on the source and drain, an oxide film 9 is formed on the side wall of the MoSi2 film, and the silicon nitride film on the MO 812 is removed.
Approximately 20nOA' of AI resin was deposited, and vJ was formed by photolithography.
A on the Nf o S + 2 film 4 like 5rIso1
111α10 is formed. By using the above-mentioned methods, there is less chance of unfavorable withstand voltage between gate electrodes, electrodes and sources or drains, and gate electrodes and interconnections with low resistance can be realized. By this method, the sheet resistance value of the gate wiring material is approximately 0.1 Ω/unit, which is more than an order of magnitude lower than the conventional high melting point wire mesh silicide alone.
（発明の効果）
ｕＪ上の説明でわかるように本発明によれば、高融点金
属硅化物では実現できない低抵抗ゲート電極・明線が実
現できる。しかも、金属単層を用いた時に起こる耐薬品
性、耐酸化性における弱点がなく、第１鰯として金Ｍ−
８ｉ合金を甲いているため従来の多結晶Ｓｉ又は、金属
硅化物ゲートプロセスを適甲でき、第２層のＡ１を主成
分とした金属層が、低抵抗化ならしめる。(Effects of the Invention) As can be seen from the explanation above, according to the present invention, a low-resistance gate electrode/bright line that cannot be realized with a high melting point metal silicide can be realized. Moreover, there are no weaknesses in chemical resistance and oxidation resistance that occur when using a single metal layer, and gold M-
Since it is made of 8i alloy, conventional polycrystalline Si or metal silicide gate processes can be applied, and the second layer, a metal layer mainly composed of A1, provides low resistance.
実施例で説明した第１層のＭ ｏ Ｓ Ｉ ２は、他の
高融点金属−Ｓｉ合金でも同様の効果をもつ。又第２１
１〇Ａ１け、純ＡＩでなくてもＣｕ％Ｓｉ及び他の元紫
を添加したＡ１の場合にも同様の効果をもつ。The first layer M o S I 2 described in the examples has similar effects with other high melting point metal-Si alloys. Also the 21st
10 A1 has the same effect even if it is not pure AI but A1 to which Cu%Si and other elements are added.
第１図は、本発明によるＭＩＳ−Ｆ’Ｅ’ｌ’ゲート電
極・Ｍ襖の構造を示す断面図、ｐｌｆＪ２図〜第５図は
、本発明によるＭＩＳ−Ｔ’ＥＴ製造方法の簡単化した
工程図を示す。
１・・ｐ刑（又はｎ深ｉ、 ） Ｓ ｉ基板、２・・フ
ィールド酸（ｋ膜、３・・ゲート絶縁膜、４・・・高争
１１点金属−８ｉ合金膜、５・・窒化硅素嘩、６・・・
フォトレジスト層 ７ｎ＋（又はｐ＋）不純物注入層〔
ソース及びドレイン〕、８・・・酸化膜、９・・・酸化
膜、１０・・Ａ１を主成分とする金属際。
（７３１７） 代理人 弁理士 則近 憲 佑（１”
ｉか１名）（７）
ｗ＆ 法
＋ ０
滅 銖FIG. 1 is a cross-sectional view showing the structure of the MIS-F'E'l' gate electrode/M sliding door according to the present invention, and plfJ2 to FIG. 5 are simplified views of the MIS-T'ET manufacturing method according to the present invention. A process diagram is shown. 1...p (or n depth i) Si substrate, 2...field acid (k film, 3...gate insulating film, 4...high-strength 11 point metal-8i alloy film, 5...nitriding Silicon fight, 6...
Photoresist layer 7n+ (or p+) impurity implantation layer [
Source and drain], 8... Oxide film, 9... Oxide film, 10... Metal border containing A1 as the main component. (7317) Agent Patent Attorney Kensuke Norichika (1”
(i or 1 person) (7) w & law + 0 destruction
Claims (2)
もしくは配線が、高融点金属−硅素合金及びＡＩを主成
分とした金属層の２層構造よりなることを特徴とする半
導体装置。(1) A semiconductor device characterized in that the gate electrode or wiring of the e-edge gate type field effect transistor has a two-layer structure of a metal layer mainly composed of a high melting point metal-silicon alloy and AI.
成し、次いで第１の全４騎である高融点金属−硅素合金
膜及び、窒化硅素膜を被差し、ゲート電極もしくけ配線
パターンを形成する工程と、次いで酸化性雰囲気中にて
、熱処理を行なった後前記第１の今生層上の窒化硅素膜
を除去（〜、第２の金尋誓であるＡＩを主成分とした金
属線を被着し、ゲート電極を形成する工程とを具備する
ことを特徴とする半導体装置の製造方法。(2) Form a gate insulating film in the element formation region on the semiconductor substrate, then cover with the first four components, a refractory metal-silicon alloy film and a silicon nitride film, and form a gate electrode and wiring pattern. After the step of forming, and then heat treatment in an oxidizing atmosphere, the silicon nitride film on the first layer is removed. 1. A method for manufacturing a semiconductor device, comprising the steps of depositing a gate electrode and forming a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP336183A JPS59129471A (en) | 1983-01-14 | 1983-01-14 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP336183A JPS59129471A (en) | 1983-01-14 | 1983-01-14 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59129471A true JPS59129471A (en) | 1984-07-25 |
| JPH0532910B2 JPH0532910B2 (en) | 1993-05-18 |
Family
ID=11555206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP336183A Granted JPS59129471A (en) | 1983-01-14 | 1983-01-14 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59129471A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5687342A (en) * | 1979-12-18 | 1981-07-15 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5730328A (en) * | 1980-06-30 | 1982-02-18 | Ibm | Method of forming high melting point metallic silicide layer |
| JPS57149776A (en) * | 1981-03-12 | 1982-09-16 | Sony Corp | Formation of high-melting point metal and silicon compound thin film |
-
1983
- 1983-01-14 JP JP336183A patent/JPS59129471A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5687342A (en) * | 1979-12-18 | 1981-07-15 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5730328A (en) * | 1980-06-30 | 1982-02-18 | Ibm | Method of forming high melting point metallic silicide layer |
| JPS57149776A (en) * | 1981-03-12 | 1982-09-16 | Sony Corp | Formation of high-melting point metal and silicon compound thin film |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0532910B2 (en) | 1993-05-18 |
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