JPS59127859A - Manufacture of rom semiconductor device - Google Patents

Abstract

PURPOSE:To make the titled device correspond to any progrom change easily by a method wherein inverse conductive type source. drain regions are diffused on one conductive type semiconductor substrate and a guard region is diffused on a field region wherein no transistor is formed and then one conductive type impurity is diffused or ion-planted. CONSTITUTION:P<+> type source and drain regions 22, 23 extended like a belt in parallel with an N type silicon substrate 21 are selectively diffused. An N<+> type guard region 26 is diffused on a field region 25 excluding a channel regions 24 to form transistor. Next an N<+> type impurity is diffused or ion-planted into the channel regions 24 not forming the transistor to write a program. Then a gate oxide film is formed all over the substrate 21 serving also as a field oxide film. A gate electrode 27 formed on the channel regions 24 are extended to form grids with the drain regions 22, 23. Through these procedures, a program may be changed easily and promtly since any programing process may be postponed to the later one as late as possible.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention is a ROM (Read Only Memory).
) The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing a ROM semiconductor device using a thin field oxide film of 1000 A or less.

(b) In conventional mask ROM semiconductor devices, programs are stored using a mask depending on the presence or absence of transistors. Therefore, the program is changed by changing whether or not transistors are formed.

FIG. 1 is a circuit diagram of a P-channel type NAND ROM, in which a plurality of channels are formed between a common source and drain.

In a typical ROM semiconductor device, the substrate (1
) A thin gate oxide film (2) of approximately 800 A" is provided on the surface where a transistor will be formed, and a channel region (3) and field region (3) where no transistor will be formed are provided.
4) On top is a thick field oxide film of about 8000A° (
5) was established. Then, a gate electrode (6) was attached, and only the gate electrode (6) on the gate oxide film (2) functioned as a transistor.

However, in the above structure, a thick field oxide film (5
), which makes the manufacturing process complicated, and in limited low-voltage applications, a structure in which the field oxide film is thinned to about the same thickness as the gate oxide film is sometimes adopted. This type of structure diffuses guard regions into the field region to prevent parasitic effects.

A method of manufacturing the NAND ROM semiconductor device described above using such a structure is shown in FIGS. 3A and 3B%C.

First, as shown in FIG. 3A, P type source and drain regions Q extending in a band shape on the surface of an N type silicon substrate 01) are diffused. The source and drain regions (a) and (to) are separated by a width that provides a channel region. Next, as shown in FIG. 3B, N
The guard region OQ of the mold is diffused to prevent parasitic effects. Note that the channel region Q where no transistor is formed in this process
4, an N type guard region α0 is also diffused. Then, a gate oxide film having a thickness of about 100 OA or less is formed over the entire surface of the substrate (1). Further, as shown in FIG. 3C, a gate electrode 0η made of vapor-deposited aluminum is formed on the gate oxide film above the channel region α→. As a result, transistors are formed at the x marks in FIG. 3C.

However, in the above method for manufacturing a ROM semiconductor device, the transistor is formed at the same time as the guard region 00 is diffused.
In order to perform diffusion in the channel region α→, it is necessary to change the diffusion mask of the guard region αQ when changing the program. Moreover, the guard area OQ is usually N-channel MO8)
This is often done at the same time as the source and drain regions of a transistor, and is located early in the manufacturing process. As a result, there is a drawback that the program cannot be easily changed because the processes in the earliest order are changed.

(c) Objective The present invention was made in view of new patients and provides a method for manufacturing a ROM semiconductor device that can easily accommodate program changes.

) configuration The present invention is comprised of the following steps.

(1) - Step of diffusing source and drain regions of opposite conductivity type into a semiconductor substrate of conductivity type. (2) Step of diffusing guard regions of one conductivity type into the field region except for all channel regions where transistors are formed. (3) Step of selectively diffusing or ion-implanting impurities of one conductivity type into the channel region where no transistor is formed (4) Step of forming a gate electrode on the channel region (e) Example P channel to which the present invention is applied An embodiment of a type NAND ROM semiconductor device will be described.

In this embodiment, first, as shown in FIG. 4A, P-type source and drain regions @(e) are diffused into an N-type silicon substrate 01) by selective diffusion.

In this step, the P-type source and drain regions @ (c) rolled into strips parallel to the n-type silicon substrate (c) are selectively diffused. A channel region (c) for forming a transistor according to a program is provided between the source and drain regions (a).

Next, as shown in FIG. 4B, an N-type guard region (H) is diffused into the field region (C) except for all the channel region (C). This step is one of the features of the present invention; channel regions (c) of all transistors constituting the ROM are formed, and no program is written in this step. Therefore, in this step, the channel regions of all the transistors constituting the ROM before programming are formed. This is called a mother ROM pattern.

Next, as shown in FIG. 4C, N type impurities are selectively diffused or ion-implanted into the channel region (c) of the mother ROM pattern where no transistor is formed. This step is one of the features of the present invention. For example, as shown in the figure, bio-ions are implanted into the third channel region (c) from the left using a photoresist film as a mask to make it N-type, and the transistor in this channel region @ prevent the formation of

In this way, in this process, N is applied to the desired channel region (goods).
Program writing is performed by diffusion of type impurities or ion implantation. After that, approximately 100
A gate oxide film having a thickness equal to or less than the OA thickness is generated and is also used as a field oxide film. Note that this step is performed after N+ diffusion for the source and drain diffusion of transistors (on the guard region and N channel region) in the previous step, and then on the P channel and N channel regions.
It is effective to perform ion implantation for controlling the threshold voltage of the channel MOS transistor, after completing all other diffusion steps, and immediately before the contact formation step. In other words, this is because the effect becomes greater as this step is carried out as late as possible.

Further, as shown in the fourth diagram, a gate electrode (A) is formed on the channel region (C). The gate electrode gradient is formed by selective etching of vapor-deposited aluminum, and extends in a grid pattern with the source and drain regions (a).

(F) Effect According to the present invention, the process of writing a program can be separated from the process of forming the guard region (1), and the program can be transferred to the restoring process as much as possible, so that the program can be easily changed in the later process. Changes can be made quickly.

In addition, we can promptly deliver products that require changes.

Furthermore, since the mother ROM pattern is first formed in the present invention, any changes can be made immediately and can be achieved by simply changing the mask in the program writing process.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of a general P-channel type NAND ROM semiconductor device, and FIG. 2 is a top view explaining a conventional example.
FIG. 3 is a top view illustrating the present invention. Explanation of main drawing numbers (21) is the semiconductor substrate, (22), (23) are the source and drain regions, (24) is the channel region, (27)
is the gate electrode. Procedural amendment (method) Mr. Commissioner of the Patent Office 16 Indication of the case Patent Application No. 3649 of 1982 2 Name of the invention ROM semiconductor device manufacturing method 3 Person making the amendment Patent applicant Address Keihan, Moriguchi City 2-18 Dori Name (188) Sanyo Electric Co., Ltd. Representative I Ue Kungai 1 person 4 Agent address 2-18-5 Keihan Hondori, Moriguchi City Date of amendment order (shipment date) April 1982 On the 26th, 6th, in the specification to be amended, column 7 of the brief description of the drawings, the content of the amendment, the column of the brief explanation of the drawings, will be amended as follows. Figure 1 is an equivalent circuit diagram of a general P-channel type NAND ROM semiconductor device, Figure 2 is a sectional view showing its specific configuration, and Figure 3 is a top view showing the manufacturing process of a conventional NAND ROμ semiconductor device. 4 are top views showing the manufacturing process of the ROM semiconductor device of the present invention. Explanation of the main figure numbers: 12x5 (to) is a semiconductor substrate, 12x5 (to) is a source and drain region, (to) is a channel region, @ is a gate electrode. on μ

Claims (1)

[Claims] 1. Diffusing source and drain regions of opposite conductivity type into a semiconductor substrate of one conductivity type, and diffusing guard regions of one conductivity type into a field region except for a channel region formed between the source and drain regions. a step of selectively diffusing or ion-implanting impurities of one conductivity type into the channel region where no transistor is formed; and a step of forming a gate electrode on the channel region. Method of manufacturing the device.