JPS59121957A - Manufacture of package for semiconductor device - Google Patents
Manufacture of package for semiconductor deviceInfo
- Publication number
- JPS59121957A JPS59121957A JP57228999A JP22899982A JPS59121957A JP S59121957 A JPS59121957 A JP S59121957A JP 57228999 A JP57228999 A JP 57228999A JP 22899982 A JP22899982 A JP 22899982A JP S59121957 A JPS59121957 A JP S59121957A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bonding
- package
- tungsten
- plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置用容器の製造方法に係ハ特にセラミ
ック積層型の半導体装置におけるボンティング・パッド
部の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a container for a semiconductor device, and more particularly to a method of manufacturing a bonding pad portion in a ceramic laminated semiconductor device.
従来のこの種の半導体装置は、第１図（平面図）。A conventional semiconductor device of this type is shown in FIG. 1 (plan view).
第２図（第１図のＡ−Ａｉの部分拡大の断面図）、第３
図（第１図のＢ−Ｅ線の部分拡大の断面図）に示すよう
に、セラミック積層体を形成するところの下段、中段、
上段のセラミック片１． ２． ３と、シールリンク４
と、半導体素子５と、外部取り出しのため中段セラミッ
ク片２に印刷されて焼成されたタングステンの薄膜６と
、タングステン薄膜６の上部にメッキ処理して形成され
たニッケル（Ｎｉ）膜７と、このＮｉ 膜７の上にメッ
キで形成された金（Ａｕ）膜８と、半導体素子５上に形
成された電極（図示せず）とポンディング・パッドとを
電気的に接続するための金属紙綴９とを備えている。Figure 2 (partially enlarged sectional view of A-Ai in Figure 1), Figure 3
As shown in the figure (partially enlarged cross-sectional view taken along line B-E in Figure 1), the lower, middle, and
Upper ceramic piece 1. 2. 3 and seal link 4
, a semiconductor element 5, a tungsten thin film 6 printed and fired on the middle ceramic piece 2 for external extraction, a nickel (Ni) film 7 formed by plating on the top of the tungsten thin film 6, and A metal paper binding plate is used to electrically connect a gold (Au) film 8 formed on the Ni film 7 by plating to an electrode (not shown) formed on the semiconductor element 5 and a bonding pad. 9.
このような容器の製造方法は、まずタングステン薄膜６
全印刷し、焼成後、Ｎｉメッキ７を２〜４μｍ施し、次
にＡｕメッキ８を０．５〜２μｍ施す場合の印刷法は、
例えばタングステンの粉末を有機物のバインダーの中に
しみこませ、これを中段セラミック片２に印刷Ｋｌすも
のである。しかし、寸法通り正確には印刷できず、左右
両端部が中段セラミック片２へ流れ丸みが生じてしまう
。The method for manufacturing such a container begins with a tungsten thin film 6.
The printing method is as follows: After complete printing and firing, Ni plating 7 is applied to 2 to 4 μm, and then Au plating 8 is applied to 0.5 to 2 μm.
For example, tungsten powder is impregnated into an organic binder and printed on the middle ceramic piece 2. However, it is not possible to print accurately to the dimensions, and both left and right ends flow toward the middle ceramic piece 2 and become rounded.
一般に、タングステン薄膜６の幅が十分布る場合、例え
ば第３図に示すように、８００μ以上の幅がある場合、
前記丸みが生じても全体としてはほとんど平面状態であ
り、ボンディング作業にも問題にはならないう じかし
、タングステン薄膜６の幅が、例えば、１５０μ以下の
ように狭くなれば、印刷後、第４図に示すような丸みを
帯びたタングステン薄膜σとなり、はとんど平面状態が
得られなくなる。この状態で焼成し、Ｎｉメッキ７、次
にＡｕメッキ８を施すと、第４図に示すように平面が得
られない為、金属細線９を用いてのボンディング作業は
極めて困難となる欠点があった。Generally, when the width of the tungsten thin film 6 is wide enough, for example, as shown in FIG. 3, when the width is 800μ or more,
Even if the roundness occurs, it is almost flat overall and does not pose a problem for bonding work.However, if the width of the tungsten thin film 6 is narrower, for example, 150 μm or less, the tungsten thin film 6 will be in a flat state after printing. The tungsten thin film σ becomes rounded as shown in FIG. 4, and a flat state is almost impossible to obtain. If it is fired in this state and Ni plating 7 and then Au plating 8 are applied, a flat surface cannot be obtained as shown in Fig. 4, so bonding work using thin metal wire 9 is extremely difficult. Ta.
本発明の目的は、タングステン薄膜の幅が狭い場合でも
、丸みを減少させ、平面領域を多く得。An object of the present invention is to reduce roundness and obtain a large planar area even when the width of the tungsten thin film is narrow.
ボンディング作業が容易に実施できるようにした半導体
装置用容器の製造方法を提供することにある。It is an object of the present invention to provide a method for manufacturing a container for a semiconductor device, which allows bonding work to be easily carried out.
本発明は、セラミック積層体からなる容器に半導体素子
を収容し気密に封止する製造方法において、前記容器の
少なくともボンディング・パッド部のメタライズ層には
研摩処理が施されることを特徴とする半導体装置用容器
の製造方法にある。The present invention provides a semiconductor manufacturing method in which a semiconductor element is housed in a container made of a ceramic laminate and hermetically sealed, wherein a metallized layer of at least a bonding pad portion of the container is subjected to a polishing treatment. A method for manufacturing a device container.
つぎに本発明の実施例を図面を参照しながら詳細に説明
する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
第５図は本発明の一実施例の製造方法を説明するための
断面図で、同図は第４図の従来例に対応する部分断面図
である。同図において、セラミック積層体容器のボンデ
ィング・パッド形成部のタングステン・メタライズ層６
は、印刷後焼成し。FIG. 5 is a sectional view for explaining a manufacturing method according to an embodiment of the present invention, and the same figure is a partial sectional view corresponding to the conventional example shown in FIG. In the figure, a tungsten metallized layer 6 of a bonding pad forming part of a ceramic laminate container is shown.
is fired after printing.
先端部分は平面ツールを用いた超音波加工による研摩処
理ヲ施こし、平面処理領域１０を多く得るようにしであ
る。この状態でメッキ処理して、Ｎ１膜７さらにメッキ
処理してＡｕ膜８を形成する。The tip portion is polished by ultrasonic machining using a flat tool to obtain a large flat processing area 10. In this state, a plating process is performed to form the N1 film 7 and then a plating process to form an Au film 8.
以上のように、本発明によれば、タングステン薄膜の幅
が狭い場合でも平面領域が多くなり、もって金属細線の
ボンディングが極めて容易に行なえるという効果が得ら
れる。As described above, according to the present invention, even when the width of the tungsten thin film is narrow, the planar area is increased, so that bonding of thin metal wires can be performed extremely easily.
第１図は従来のセラミック積層型半導体装置の平面図、
第２図は第１図のＡ−λ線に８って切断しその一部分を
拡大した断面図、第３図は第１図のＢ−４線に沿って切
断しその一部分を拡大した断面図、第４図は従来の幅の
狭いボンディング・パッドの断面図、第５図は第４図に
対応し本発明の実施例の製造方法を説明するための断面
図である。
同図において、 １． ２． ３・・・・・・セラミ
ック片。
４・・・・・・シールリンク、５・・・・・・半導体素
子、６１ｇ・・・・・・タングステン薄膜、７・・川・
Ｎ１メッキ層、８・・・・・・Ａｕメッキ層、９・川・
・金属細線、１０・・団・研摩された平面処理領域。
ｂ’ Ａ’
第１フ
矛Ｚ図
際３図
半４−ゾ
蜂り田Figure 1 is a plan view of a conventional ceramic laminated semiconductor device.
Fig. 2 is a cross-sectional view taken along line A-λ in Fig. 1 and partially enlarged, and Fig. 3 is a cross-sectional view taken along line B-4 in Fig. 1 and enlarged in part. , FIG. 4 is a sectional view of a conventional narrow bonding pad, and FIG. 5 is a sectional view corresponding to FIG. 4 for explaining the manufacturing method of the embodiment of the present invention. In the same figure, 1. 2. 3...Ceramic piece. 4... Seal link, 5... Semiconductor element, 61g... Tungsten thin film, 7... River...
N1 plating layer, 8... Au plating layer, 9. River.
- Fine metal wire, 10...Group - Polished plane processing area. b'A' 1st frame
Claims (1)
密封止する半導体装置用容器の製造方法において、前記
容器の少なくともボンディング・パッド部のメタライズ
層に研摩処理を施すことを特徴とする半導体装置用容器
の製造方法。A method for manufacturing a semiconductor device container in which a semiconductor confectionery is entirely housed in a container made of a ceramic laminate and hermetically sealed, the container for semiconductor devices comprising polishing a metallized layer of at least a bonding pad portion of the container. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57228999A JPS59121957A (en) | 1982-12-28 | 1982-12-28 | Manufacture of package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57228999A JPS59121957A (en) | 1982-12-28 | 1982-12-28 | Manufacture of package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59121957A true JPS59121957A (en) | 1984-07-14 |
Family
ID=16885168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57228999A Pending JPS59121957A (en) | 1982-12-28 | 1982-12-28 | Manufacture of package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121957A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660404A2 (en) * | 1993-12-27 | 1995-06-28 | Nec Corporation | Element joining pad for semiconductor device mounting board |
-
1982
- 1982-12-28 JP JP57228999A patent/JPS59121957A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660404A2 (en) * | 1993-12-27 | 1995-06-28 | Nec Corporation | Element joining pad for semiconductor device mounting board |
| EP0660404A3 (en) * | 1993-12-27 | 1996-03-27 | Nec Corp | Element joining pad for semiconductor device mounting board. |
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