JPS56167339A - Electronic parts equipped with gold conductive layer - Google Patents
Electronic parts equipped with gold conductive layerInfo
- Publication number
- JPS56167339A JPS56167339A JP7046780A JP7046780A JPS56167339A JP S56167339 A JPS56167339 A JP S56167339A JP 7046780 A JP7046780 A JP 7046780A JP 7046780 A JP7046780 A JP 7046780A JP S56167339 A JPS56167339 A JP S56167339A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metallic
- layers
- conductive layer
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
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- H01L2924/01025—Manganese [Mn]
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- H01L2924/01042—Molybdenum [Mo]
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- H01L2924/01047—Silver [Ag]
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- H01L2924/01074—Tungsten [W]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
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- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Contacts (AREA)
Abstract
PURPOSE:To lower production cost by reducing the amount of gold to be used for ceramic package, etc., by providing a metallic layer consisting of silver, vanadium or its alloy, as a metallic layer as a substrate of gold. CONSTITUTION:To a die, which is loaded with a semiconductor chip 4, and to a joint of a wire 9, a material such as conductive metallic layer of a ceramic housing 1, on which metallic layers 3 and 2 consising of such elements as Mo and Mn, etc., is applied. On the top of these metallic layers 3 and 2, metallic layers 6 and 5 are formed by Ag or Pd or their alloys, and these layers are to be used as substrate metals of Au layers 8 and 7 which are to become a surface layer of the conductive layer. It is possible, by doing so, to maintain the quality of the die and the wire bond even when the Au layer were to be made thin, and therefore, the cost can be lowered. Further, by providing an Ni layer between the metallic layers 3 and 2 and the substrate metals 6 and 5, it is possible, to make further effective reduction of amount of Au to be used.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7046780A JPS6034257B2 (en) | 1980-05-26 | 1980-05-26 | Electronic components with gold conductive layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7046780A JPS6034257B2 (en) | 1980-05-26 | 1980-05-26 | Electronic components with gold conductive layer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56167339A true JPS56167339A (en) | 1981-12-23 |
JPS6034257B2 JPS6034257B2 (en) | 1985-08-07 |
Family
ID=13432347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7046780A Expired JPS6034257B2 (en) | 1980-05-26 | 1980-05-26 | Electronic components with gold conductive layer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6034257B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60107845A (en) * | 1983-11-17 | 1985-06-13 | Toshiba Corp | Circuit substrate for semiconductor |
JPS60110127A (en) * | 1983-11-18 | 1985-06-15 | Sony Corp | Semiconductor device having laminated metal electrode |
JPS62150606A (en) * | 1985-12-23 | 1987-07-04 | 松下電工株式会社 | Electric contact |
WO1992015117A1 (en) * | 1991-02-25 | 1992-09-03 | Sumitomo Electric Industries, Ltd. | Wiring board |
JPH06283623A (en) * | 1993-03-26 | 1994-10-07 | Ngk Insulators Ltd | Semiconductor package |
DE4431847C5 (en) * | 1994-09-07 | 2011-01-27 | Atotech Deutschland Gmbh | Substrate with bondable coating |
-
1980
- 1980-05-26 JP JP7046780A patent/JPS6034257B2/en not_active Expired
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60107845A (en) * | 1983-11-17 | 1985-06-13 | Toshiba Corp | Circuit substrate for semiconductor |
JPH0454378B2 (en) * | 1983-11-17 | 1992-08-31 | Tokyo Shibaura Electric Co | |
JPS60110127A (en) * | 1983-11-18 | 1985-06-15 | Sony Corp | Semiconductor device having laminated metal electrode |
JPS62150606A (en) * | 1985-12-23 | 1987-07-04 | 松下電工株式会社 | Electric contact |
WO1992015117A1 (en) * | 1991-02-25 | 1992-09-03 | Sumitomo Electric Industries, Ltd. | Wiring board |
US5369220A (en) * | 1991-02-25 | 1994-11-29 | Sumitomo Electric Industries Ltd. | Wiring board having laminated wiring patterns |
JPH06283623A (en) * | 1993-03-26 | 1994-10-07 | Ngk Insulators Ltd | Semiconductor package |
DE4431847C5 (en) * | 1994-09-07 | 2011-01-27 | Atotech Deutschland Gmbh | Substrate with bondable coating |
Also Published As
Publication number | Publication date |
---|---|
JPS6034257B2 (en) | 1985-08-07 |
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