JPS605224B2 - Packages for integrated circuits - Google Patents
Packages for integrated circuitsInfo
- Publication number
- JPS605224B2 JPS605224B2 JP11825979A JP11825979A JPS605224B2 JP S605224 B2 JPS605224 B2 JP S605224B2 JP 11825979 A JP11825979 A JP 11825979A JP 11825979 A JP11825979 A JP 11825979A JP S605224 B2 JPS605224 B2 JP S605224B2
- Authority
- JP
- Japan
- Prior art keywords
- metallized layer
- tungsten
- lead terminal
- porous
- external lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は集積回路（ＩＣ）のパッケージ構造の改良に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in integrated circuit (IC) package structures.
近年、ＩＣは高度に集積化され、パッケージも大型とな
って、多数の外部ＩＪードを四方周囲から導出せしめた
フラット型セラミック・パッケージが多用されている。In recent years, ICs have become highly integrated and their packages have become larger, with flat ceramic packages in which a large number of external IJs are led out from the periphery on all sides being used frequently.
しかもセラミック製パッケージは他の材質のパッケージ
より環境の変化にたいしてはるかに信頼度が高いために
、多層構造のセラミック・パッケージがなお重用されて
おり、又一方、収納するＩＣチップの電気的特性は著し
く改善されてセラミック基体内での導電パターンの電気
抵抗を無視することが出来ない現状となってきた。その
ために、導電パターンを形成するメタラィズ層を例えば
多孔質のタングステンで焼成し、低抵抗の銀ろうなどを
含浸させる構造が探られる様になった。しかしながら、
この様な多孔質メタラィズ層は良好な導電体となる反面
、ち密質メタラィズ層と比べて接着強度が弱い欠点があ
り、特に外部リード様子との接着に難点がある。本発明
はかような点を除去した高導電パターンを形成せるフラ
ット型セラミック・パッケージを提供することを目的と
するもので、本発明の特徴とするところは、セラミック
基体に形成せる導電パターンは従来と同機に多孔質メタ
ラィズ層に低抵抗のろう材を含浸せしめた構造とし、且
つ外部リード端子との接着部分にはち密質メタライズ層
と多孔質メタラィズ層との二重構造としたことにある。Furthermore, because ceramic packages are much more reliable against environmental changes than packages made of other materials, multilayer ceramic packages are still being used extensively. Improvements have been made to the point where the electrical resistance of the conductive pattern within the ceramic substrate cannot be ignored. For this reason, a structure has been explored in which the metallized layer forming the conductive pattern is fired from porous tungsten, for example, and impregnated with low-resistance silver solder. however,
Although such a porous metallized layer is a good conductor, it has the disadvantage that its adhesive strength is weaker than that of a dense metallized layer, and it is particularly difficult to adhere to external leads. The present invention aims to provide a flat type ceramic package in which a highly conductive pattern can be formed by eliminating such points.The feature of the present invention is that the conductive pattern formed on the ceramic substrate is The same machine has a structure in which the porous metallized layer is impregnated with a low-resistance brazing material, and the adhesive part with the external lead terminal has a double structure of a dense metallized layer and a porous metallized layer.
以下、図面を参照して詳細に説明すると、第１図は従釆
のち密質導電パターンを形成した一例の断面図を示した
ものである。Hereinafter, a detailed explanation will be given with reference to the drawings. FIG. 1 shows a cross-sectional view of an example in which a dense conductive pattern is formed after a substructure.
図において、１はセラミック・ベースでその表面に導電
パターンのち密質タングステン・メタラィズ層１ １が
形成されており、ＩＣチップ２を取り付けたダィ・キャ
ビティ３の表面も同様のメタラィズ層１３が形成され、
又シール・フレーム４にもキャップ（図示せず）を封着
するために同様のメタラィズ層１４が形成され、これら
のメタラィズ層１１，１３，１４は該パッケージを焼成
成型の際に同時に焼成され、その後に表面には金メッキ
などがなされている。In the figure, reference numeral 1 denotes a ceramic base on which a conductive pattern of a dense tungsten metallization layer 11 is formed, and a similar metallization layer 13 is formed on the surface of a die cavity 3 in which an IC chip 2 is attached. is,
A similar metallized layer 14 is also formed on the sealing frame 4 to seal a cap (not shown), and these metallized layers 11, 13, 14 are fired at the same time when the package is fired and molded. The surface is then plated with gold.
タ そして、外部リード端子５は導電パターンのメタラ
ィズ層１１の外端部に銀ろうでろう付けされ、内端部は
ＩＣチップ２とボンデングワイヤー６で接続される。Then, the external lead terminal 5 is soldered to the outer end of the metallized layer 11 of the conductive pattern with silver solder, and the inner end is connected to the IC chip 2 with a bonding wire 6.
しかしながら、ち密質タングステン・メタライズ層１１
で形成した導電パターンは高抵抗が欠点であり、従って
第２図に示す様な導電パターンを多孔費タングステン・
メタラィズ層２１として低抵抗のろう村を含浸した構造
が用いられ、導電性は非常に改善された。However, the dense tungsten metallization layer 11
The disadvantage of conductive patterns formed with tungsten is high resistance. Therefore, conductive patterns such as those shown in Fig.
A structure impregnated with a low-resistance wax film was used as the metallized layer 21, and the conductivity was greatly improved.
しかし、この場合には外部リード端子５と多孔質タング
ステン・メタラィズ層との接着が弱くなり、外部リード
端子５がはがれ易い致命的問題があらわれてきた。第３
図は本発明のパッケージの一例の断面図で、第１図及び
第２図と同じく１はセラミック・ベース、２はＩＣチッ
プ、３はダイ・キヤビティ、４はシール・フレーム、５
は外部リード端子、６はボンディング・ワイヤ一を示し
ており、タングステン・メタラィズ層１３，１４は従来
と同様にち密質ある。However, in this case, a fatal problem has arisen in that the adhesion between the external lead terminal 5 and the porous tungsten metallized layer becomes weak, and the external lead terminal 5 easily peels off. Third
The figure is a cross-sectional view of an example of the package of the present invention, in which 1 is a ceramic base, 2 is an IC chip, 3 is a die cavity, 4 is a seal frame, and 5 is a sectional view of an example of the package of the present invention.
6 indicates an external lead terminal, and 6 indicates a bonding wire, and the tungsten metallized layers 13 and 14 are dense as in the conventional case.
しかし導電パターンは多孔質タングステン・メタラィズ
層３１で形成して、低抵抗の銀ろうを含浸せしめて導電
性を良くしており、一方外部リード端子５の下部の多孔
質タングステン・メタラィズ層３１とセラミック・ベー
ス１との間にち密質タングステン・メタラィズ層３１′
を介在せしめて、外部リード端子５の接着強度を強くし
てある。第４図は第３図の破線で囲んだ外部リード端子
５の接着部分の平面図で、ち密質タングステン・メタラ
ィズ層３１′を出来るだけ広く形成して接着強度を保持
する様にはかっていることを示している。However, the conductive pattern is formed of a porous tungsten metallized layer 31 and impregnated with low-resistance silver solder to improve conductivity, while the porous tungsten metallized layer 31 and the ceramic layer at the bottom of the external lead terminal 5 are impregnated with low resistance silver solder.・Dense tungsten metallization layer 31' between base 1
is interposed to strengthen the adhesive strength of the external lead terminal 5. FIG. 4 is a plan view of the adhesive part of the external lead terminal 5 surrounded by the broken line in FIG. 3, and the dense tungsten metallized layer 31' is formed as wide as possible to maintain adhesive strength. It shows.
この様な本発明のパッケ−ジ構造の製造工程は従来と変
わりなく形成することができ、例えばち密質タングステ
ン・メタラィズ層形成部分にはタングステン粉末を多く
含んだペーストを塗布し、又導霜パターンの多孔質タン
グステン・メタラィズ層部分にはタングステン粉末を少
なくして飛散物を多くしたペーストを塗布し、同時に１
５００こＣ程度の高温度で焼成成型すればよい。The manufacturing process of the package structure of the present invention can be formed in the same way as in the past. For example, a paste containing a large amount of tungsten powder is applied to the area where the dense tungsten metallization layer is to be formed, and a frost-conducting pattern is formed. A paste containing less tungsten powder and more flying particles was applied to the porous tungsten metallized layer, and at the same time
It is sufficient to perform firing and molding at a high temperature of about 500°C.
又、外部リード端子５の銀ろう付けと同時に、多孔質タ
ングステン・メタラィズ層に銀ろうを含浸させれば毛細
管作用で浸み込んで低抵抗の導電パターンに形成される
。Furthermore, if the porous tungsten metallized layer is impregnated with silver solder at the same time as the external lead terminal 5 is soldered with silver, the silver solder permeates through capillary action and forms a conductive pattern with low resistance.
以上の説明から判る様に、本発明は導電パターンの導電
性を改善して且つ外部リード端子の接着強度を強くした
構造であるから、ＩＣの信頼性向上に極めて有効である
。As can be seen from the above description, the present invention has a structure in which the conductivity of the conductive pattern is improved and the adhesive strength of the external lead terminal is strengthened, so that it is extremely effective in improving the reliability of the IC.
尚、上記例はタングステン・メタラィズ層で説明したが
、その他の高融点メタルでもよく、又ろう材も銀ろうに
限定されるものではない。Although the above example has been explained using a tungsten metallized layer, other high melting point metals may be used, and the brazing material is not limited to silver brazing material.
第１図及び第２図は従来のパッケージの一例の断面図、
第３図は本発明のパッケージの一例の断面図である。
第４図は第３図の部分平面図である。図中、５は外部リ
ード端子、１１，１３，１４，３１′はち密質タングス
テン・メタラィズ層、３１は多孔質タングステン・メタ
ラィズ層を示す。
多′図
多２図
多３図
第４図Figures 1 and 2 are cross-sectional views of an example of a conventional package;
FIG. 3 is a cross-sectional view of an example of the package of the present invention. FIG. 4 is a partial plan view of FIG. 3. In the figure, 5 is an external lead terminal, 11, 13, 14, 31' is a dense tungsten metallized layer, and 31 is a porous tungsten metallized layer. Multi-figure Multi-figure 2 Multi-figure 3 Fig. 4
Claims (1)
ミツク基体に形成せる導電パターンは多孔質メタライズ
層に低抵抗のろう材を含浸せしめた構造とし、且つ外部
リード端子との接着部分はち密質メタライズ層と多孔質
メタライズ層との二重層構造としたことを特徴とする集
積回路用パツケージ。1 In a flat type ceramic package, the conductive pattern formed on the ceramic substrate has a structure in which a porous metallized layer is impregnated with a low-resistance brazing filler metal, and the bonding area with the external lead terminal is formed between a dense metallized layer and a porous metallized layer. An integrated circuit package characterized by having a double layer structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11825979A JPS605224B2 (en) | 1979-09-14 | 1979-09-14 | Packages for integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11825979A JPS605224B2 (en) | 1979-09-14 | 1979-09-14 | Packages for integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5642362A JPS5642362A (en) | 1981-04-20 |
| JPS605224B2 true JPS605224B2 (en) | 1985-02-08 |
Family
ID=14732186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11825979A Expired JPS605224B2 (en) | 1979-09-14 | 1979-09-14 | Packages for integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS605224B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0424744Y2 (en) * | 1986-07-03 | 1992-06-11 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5820543U (en) * | 1981-08-03 | 1983-02-08 | 三洋電機株式会社 | Electrodes for soldering thick film circuits |
| JPS5931043A (en) * | 1982-08-12 | 1984-02-18 | Mitsubishi Electric Corp | Semiconductor device package |
-
1979
- 1979-09-14 JP JP11825979A patent/JPS605224B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0424744Y2 (en) * | 1986-07-03 | 1992-06-11 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5642362A (en) | 1981-04-20 |
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