JPS6094743A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6094743A JPS6094743A JP20313183A JP20313183A JPS6094743A JP S6094743 A JPS6094743 A JP S6094743A JP 20313183 A JP20313183 A JP 20313183A JP 20313183 A JP20313183 A JP 20313183A JP S6094743 A JPS6094743 A JP S6094743A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- plating
- lead
- pattern
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000010931 gold Substances 0.000 claims description 19
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 17
- 229910052737 gold Inorganic materials 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims 1
- 239000000919 ceramic Substances 0.000 abstract description 16
- 238000007747 plating Methods 0.000 abstract description 15
- 239000000758 substrate Substances 0.000 abstract description 10
- 238000007772 electroless plating Methods 0.000 abstract description 7
- 238000009713 electroplating Methods 0.000 abstract description 6
- 238000007796 conventional method Methods 0.000 abstract description 5
- 238000005245 sintering Methods 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000005219 brazing Methods 0.000 abstract description 2
- 238000005520 cutting process Methods 0.000 abstract description 2
- 238000005498 polishing Methods 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract 2
- 238000001354 calcination Methods 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 229910052759 nickel Inorganic materials 0.000 description 5
- 230000006378 damage Effects 0.000 description 4
- PQTCMBYFWMFIGM-UHFFFAOYSA-N gold silver Chemical compound [Ag].[Au] PQTCMBYFWMFIGM-UHFFFAOYSA-N 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- PNNSTTVHNHPWGV-UHFFFAOYSA-N [Fe].[Au].[Au] Chemical compound [Fe].[Au].[Au] PNNSTTVHNHPWGV-UHFFFAOYSA-N 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置の製造方法に係り、特にセラミック
容器の鍍金方法の改善に−する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to an improvement of a method of plating a ceramic container.
（ｂ） 従来技術と問題点
従来牛導体装置に使用するたとえばセラミックバッグー
ジを製造する場合、第１図に示すごとくセラミックのグ
リーンシート上に所定のＭＯ、Ｍｎ 。(b) Prior Art and Problems When manufacturing, for example, a ceramic baggage used in a conventional conductor device, predetermined MO and Mn are deposited on a ceramic green sheet as shown in FIG.
Ｗなどよりなるメクライズ層の導電パターンタトえば半
導体菓子１を接着する導電ステージ２或は金線細線３を
ワイヤボンデングする内部リードパターン４などが印刷
された複数個のグリーンシートを多胸に重ね合わせて適
当な加圧力と温度により積層後、この積層した板状体を
高温度に焼結し一体的々セラミック基体５とされる。次
いで該セラミック基体５の導電パターンに無電解ニッケ
ルメッキを施した後スルーホール６の端部に複数個のリ
ード端子７をロク付けする。次いで導電ステージ２．内
部リードパターン４などの導電パターン及びリード端子
７に導通しセラミック基体５の倒曲に導出設けられた鍍
金端子用パターン８を用いてセラミック基体面に設けら
れた導電パターン及びリード端子７に電解鍍金法によっ
てニッケル（Ｎ１）鍍金を行々う。A plurality of green sheets printed with a conductive pattern 2 for bonding a semiconductor confectionery 1 or an internal lead pattern 4 for wire bonding a thin gold wire 3 are superimposed on each other in a multi-layered manner. After lamination using appropriate pressure and temperature, the laminated plate bodies are sintered at high temperature to integrally form the ceramic substrate 5. Next, after electroless nickel plating is applied to the conductive pattern of the ceramic substrate 5, a plurality of lead terminals 7 are connected to the ends of the through holes 6. Next, conductive stage 2. Electrolytic plating is applied to the conductive patterns and lead terminals 7 provided on the surface of the ceramic substrate using a plating terminal pattern 8 which is conductive to the conductive patterns such as the internal lead pattern 4 and the lead terminals 7 and is led out from the bent side of the ceramic substrate 5. Nickel (N1) plating is performed using a method.
次いで該Ｎ１鍍金層の密着を強化するため所定温度のシ
ンター処理を行ない引続き前記鍍金端子用パターン８を
用いて電解鍍金法によりセラミック基体５の導電パター
ン及びリード端子に金ＣＡｕ）鍍金を行々う。次いで必
要に応じてリード端子の金鉄金層の引離を行なって金を
回収する。ただしリードに金銀金が必要な場合は上記剥
離工程は行なわない。また部分金鍍金はジェット金鍍金
によってもよい。Next, in order to strengthen the adhesion of the N1 plated layer, a sintering process is performed at a predetermined temperature, and then the conductive pattern and lead terminals of the ceramic substrate 5 are plated with gold (CAu) by electrolytic plating using the plated terminal pattern 8. . Then, if necessary, the gold-iron-gold layer of the lead terminal is separated to recover the gold. However, if gold, silver, or gold is required for the lead, the above peeling step is not performed. Further, partial gold plating may be performed by jet gold plating.
次いで第２図に示すようにセラミック基体５の側面に設
けられた鍍金端子用パターン８を側面新暦で除去し、除
去した部分を更に図示したごとく溝９切りを行なう。該
満９は該セラミック容器を用いて組立てを行なう場合に
人体による接触によって生ずる半導体素子１の静電破壊
を出来るだけ防止するために設けられる。向前回と同等
の部分については同一符号を伺している。Next, as shown in FIG. 2, the plated terminal pattern 8 provided on the side surface of the ceramic substrate 5 is removed using a side surface cutting tool, and the removed portion is further cut into grooves 9 as shown. 9 is provided in order to prevent as much as possible electrostatic discharge damage to the semiconductor element 1 caused by contact with a human body when assembling the semiconductor element 1 using the ceramic container. Parts that are equivalent to the previous front are given the same reference numerals.
しかしながら上記溝９都を設けても導出部は露出してお
り、半導体素子１をセラミック基体５の導電ステージ２
上に接着し、金ｐＡ細線３でワイヤボンデングする組立
工程において半導体装置をハンドリングする時に溝９内
の内部導電パターンに導通した側面の導出部に人体が接
触して半導体素子の静電破壊を生ずる問題があった。However, even if the nine grooves are provided, the lead-out portion is exposed, and the semiconductor element 1 is placed on the conductive stage 2 of the ceramic base 5.
When handling the semiconductor device during the assembly process in which the semiconductor device is bonded to the top and wire-bonded with the gold pA thin wire 3, the human body may come into contact with the lead-out portion on the side surface that is electrically connected to the internal conductive pattern in the groove 9, causing electrostatic damage to the semiconductor device. There was a problem that arose.
（ｃ） 発明の目的
本発明の目的はかかる問題点にらみなされたもので静電
体破壊の発生を防止し更に半導体容器の製造工程を短縮
することが可能な半導体装置の製造方法の提供にある。(c) Purpose of the Invention The purpose of the present invention is to provide a method for manufacturing a semiconductor device that prevents the occurrence of electrostatic breakdown and further shortens the manufacturing process of a semiconductor container. .
（（１） 発明の構成
その目的を達成するため１本発明は高況反に焼成された
半導体容器ｉｆｏの導電パターンにリード端子をロク向
けし１次いで無電解鍍金にて金織膜を前記導体パターン
およびリード端子に被着する工程が含まれてなることを
特徴とする。((1) Structure of the Invention In order to achieve the object, the present invention provides a structure in which a lead terminal is directly oriented to a conductive pattern of a semiconductor container ifo which is fired under high conditions, and then a gold woven film is applied to the conductor by electroless plating. It is characterized in that it includes a step of attaching it to the pattern and lead terminals.
（ｅ） 発明の実施例 以下本発明の実施例について図面を参照して説明する。(e) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.
第３図は本発明の一実施例における半導体装置の製造方
法の工程図であり１１はセラミックシートの焼成、１２
は無電解ニッケル（Ｎｉ−）ａ金１１３はリードロク付
け、 １４は無電解ニッケル（Ｎ１）鍍金、１５けシン
ター、 １６は無電解金（Ａｕ）鍍金、 １７はリード
金剥離の各工程を示す。FIG. 3 is a process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which 11 is a firing of a ceramic sheet, 12
113 shows electroless nickel (Ni-)a gold 113 for lead locking, 14 for electroless nickel (N1) plating, 15 for sintering, 16 for electroless gold (Au) plating, and 17 for lead gold stripping.
第３図の工程図から明らかなように本発明が従来と特に
異なる点は電解鍍金を無電解鍍金に置きかえることによ
って第４図の半導体装置の要部断面図に示すととくセラ
ミック基体２１の側面に。As is clear from the process diagram of FIG. 3, the present invention is particularly different from the conventional method in that electrolytic plating is replaced with electroless plating. To.
半導体素子２２を接着する導電ステージ２３裁は金属細
線２４をワイヤボンデングする内部リードパターン２５
及びスルーホール２６の端部にロク付けされたリード端
子２７に導通ずる銀金端子用パターンを図示したごとく
必要としない点にある。The conductive stage 23 on which the semiconductor element 22 is bonded has an internal lead pattern 25 on which thin metal wires 24 are wire-bonded.
Another advantage is that, as shown in the figure, there is no need for a pattern for a silver-gold terminal that is electrically connected to a lead terminal 27 connected to the end of the through-hole 26.
即ち焼成１１よりリードロク付け１３の工＆までは従来
方法と全く向−であるが次のＮ１鈑金工程１４及びシン
タ一工程１５後のＡｕ鍍金工程１６においてけ従来の電
解銭金方法にかえて無電解鍍金方法によるためセラミッ
ク基体の側面の鍍金端子パターンがなくそのため組立工
程におけるハンドリングの際に人体の側面の接触による
静を破壊を防止することが可能となる。更に側面に鍍金
端子パターンが設けられてないため従来例においてＩＩ
Ｉ述した側面仙磨、及び溝切りの工程を省略することが
でき工程の短縮を因ることができる。上述した無電解二
ングル鍍金１２・１４におけるニッケル鍍金側の厚さは
約５０〜１００μ１ｎｃｈ、無電解金鍍金１６の鈑４１
層の厚さは約５０〜２２５μ１ｎｃｈである。That is, the process from firing 11 to lead locking 13 is completely different from the conventional method, but in the next N1 sheet metal process 14 and the Au plating process 16 after the sintering process 15, it is replaced with the conventional electrolytic method. Since the electrolytic plating method is used, there is no plating terminal pattern on the side surface of the ceramic substrate, which makes it possible to prevent damage caused by contact with the side surface of the human body during handling during the assembly process. Furthermore, since there is no plating terminal pattern on the side surface, the conventional example
The processes of side polishing and grooving described above can be omitted, resulting in a shortened process. The thickness of the nickel plating side in the above-mentioned two electroless platings 12 and 14 is about 50 to 100 μl nch, and the plate 41 of the electroless gold plating 16
The layer thickness is approximately 50-225 μl nch.
何１部分＄１金はジェット金鍍金によってもよく、この
場合には鍍金端子パターンは導電ンテージ都ｅζ対して
のみでｉ＋Ｊであり１本発明の範囲内のものである。タ
１本力法に第５図に示すような平田バンプ３１を廟する
リードレスチークキャリ（Ｌｃｃ）にも適用用能であり
前回と同等部分については同一符号を伺している。Any portion of the gold may be jet gold plated, in which case the plated terminal pattern is i+J only for the conductive stage eζ and is within the scope of the present invention. This method can also be applied to a leadless cheek carry (Lcc) using a Hirata bump 31 as shown in FIG.
（ｆ） 発明の詳細
な説明したことく本発明によれば電解鍍金の代りに無電
解鍍金を用いることによってセラミック基体の側面に銀
金端子パターンを設ける必要がなく、従って人体の接触
による静電破壊の発生を防止１．かつ製造工程の短編を
図ることがｉｉｌ能となり半導体装置の歩積向上、ｙＡ
価低湿１に効果かある。(f) Detailed Description of the Invention According to the present invention, by using electroless plating instead of electrolytic plating, there is no need to provide a silver-gold terminal pattern on the side surface of the ceramic substrate, and therefore electrostatic charge caused by contact with the human body is eliminated. Preventing destruction 1. In addition, it is possible to shorten the manufacturing process, improving the yield of semiconductor devices, and increasing the yield of semiconductor devices.
It is effective for low humidity level 1.
第１図及び第２図は従来方法を説明するための仮押ｗＴ
曲図、第３図は本発明の一実施例の工程図。
第４図は本発明の一実施例を説明するための要部断面図
、第５図は他の実施例を説明するための要部断面図でお
る。
図において１１は焼成、 １２は加電解Ｎｉ鍛金。
１３はリードロウ付け、１４は無電解Ｎ１銀金。
１５はシンター、１６は無電解Ｎ１銀金、１７はリード
Ａｕ刺離、２１はセラミック基餌、２２は半導体素子、
２３は導電ステージ、２４は合一細線、 ２５は内部リ
ードパターン、 ２６はスルーホール、２７はリード端
子、３１は半田バンブを示す。
第１図
第２図Figures 1 and 2 are temporary presses wT to explain the conventional method.
FIG. 3 is a process diagram of an embodiment of the present invention. FIG. 4 is a sectional view of a main part for explaining one embodiment of the present invention, and FIG. 5 is a sectional view of a main part for explaining another embodiment. In the figure, 11 is a fired Ni metal, and 12 is an electrolyzed Ni forged metal. 13 is lead brazing, 14 is electroless N1 silver gold. 15 is a sinter, 16 is an electroless N1 silver gold, 17 is a lead Au puncture, 21 is a ceramic base bait, 22 is a semiconductor element,
23 is a conductive stage, 24 is a combined thin wire, 25 is an internal lead pattern, 26 is a through hole, 27 is a lead terminal, and 31 is a solder bump. Figure 1 Figure 2
Claims (1)
ド端子をロク伺けし１次いで無！ｔ＆、Ｍ金にて金執膜
を前記導電パターンおよびリード端子に、被着する工程
が含まれてなることを特徴とする半導体装置の製造方法
。When the lead terminal is connected to the conductive pattern on the surface of the semiconductor container that has been fired at high temperature, there is no result! 1. A method for manufacturing a semiconductor device, comprising the step of depositing a gold film on the conductive pattern and the lead terminal using T&M gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20313183A JPS6094743A (en) | 1983-10-28 | 1983-10-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20313183A JPS6094743A (en) | 1983-10-28 | 1983-10-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6094743A true JPS6094743A (en) | 1985-05-27 |
| JPH0451051B2 JPH0451051B2 (en) | 1992-08-18 |
Family
ID=16468921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20313183A Granted JPS6094743A (en) | 1983-10-28 | 1983-10-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6094743A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6258047U (en) * | 1985-09-28 | 1987-04-10 |
-
1983
- 1983-10-28 JP JP20313183A patent/JPS6094743A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6258047U (en) * | 1985-09-28 | 1987-04-10 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0451051B2 (en) | 1992-08-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |