JP3273187B2 - Manufacturing method of wiring board - Google Patents

Manufacturing method of wiring board

Info

Publication number
JP3273187B2
JP3273187B2 JP01495799A JP1495799A JP3273187B2 JP 3273187 B2 JP3273187 B2 JP 3273187B2 JP 01495799 A JP01495799 A JP 01495799A JP 1495799 A JP1495799 A JP 1495799A JP 3273187 B2 JP3273187 B2 JP 3273187B2
Authority
JP
Japan
Prior art keywords
common conductor
layer
conductor layer
wiring board
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP01495799A
Other languages
Japanese (ja)
Other versions
JP2000216286A (en
Inventor
孝有 奈須
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Spark Plug Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP01495799A priority Critical patent/JP3273187B2/en
Publication of JP2000216286A publication Critical patent/JP2000216286A/en
Application granted granted Critical
Publication of JP3273187B2 publication Critical patent/JP3273187B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E30/00Energy generation of nuclear origin
    • Y02E30/30Nuclear fission reactors

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、配線基板の製造方
法に係り、特に複数層からなる矩形状の絶縁基板を用い
た配線基板に設けられた多数の外部接続端子の電解メッ
キ法をに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for electrolytically plating a large number of external connection terminals provided on a wiring board using a rectangular insulating substrate having a plurality of layers.

【0002】[0002]

【従来の技術】図1(a)および(b)に示すピングリ
ッドアレイ型セラミックパッケージのような、多数のリ
ードピン(外部接続端子)2を有するセラミックパッケ
ージ1は、その製造工程において、多数のリードピン2
にニッケル(Ni)や金(Au)のような金属をメッキ
する必要がある。このメッキ工程においては、相互に絶
縁されている多数のリードピン2の総てに導通をとる必
要がある。
2. Description of the Related Art A ceramic package 1 having many lead pins (external connection terminals) 2, such as a pin grid array type ceramic package shown in FIGS. 1A and 1B, has a large number of lead pins in a manufacturing process. 2
Need to be plated with a metal such as nickel (Ni) or gold (Au). In this plating step, it is necessary to conduct all the many lead pins 2 which are insulated from each other.

【0003】従来より多数のリードピン2に共通の導通
をとる手段として、リードピン2のそれぞれからセラミ
ック基板3の内部を経て、セラミック基板3の側面5の
表面に至る導出配線層4を形成するとともに、セラミッ
ク基板3の側面5の表面に印刷配線法等を用いて、共通
導体層6を形成し、この共通導体層6により側面5の表
面に表出した導出配線層4を共通に接続する。
Conventionally, as a means for establishing conduction in common with a large number of lead pins 2, a lead-out wiring layer 4 extending from each of the lead pins 2 through the inside of the ceramic substrate 3 to the surface of the side surface 5 of the ceramic substrate 3 is formed. A common conductor layer 6 is formed on the surface of the side surface 5 of the ceramic substrate 3 by using a printed wiring method or the like, and the lead-out wiring layer 4 exposed on the surface of the side surface 5 is commonly connected by the common conductor layer 6.

【0004】このような構成とし、図2に示すように、
共通導体層6を導通アーム7により所定の電位に接続す
ることにより、多数のリードピン2の総てを同一電位に
保つことが可能となり、従ってここに絶縁されたリード
ピン2の表面に容易に電解メッキを施し、メッキ金属層
を形成することができる。さらに、このメッキ工程終了
後に、共通導体層6を除去することにより、多数のリー
ドピン2を再び相互に絶縁することができる。
With such a configuration, as shown in FIG.
By connecting the common conductor layer 6 to a predetermined potential by the conducting arm 7, it is possible to keep all of the many lead pins 2 at the same potential, so that the surface of the insulated lead pin 2 can be easily electroplated. To form a plated metal layer. Further, after the completion of the plating step, by removing the common conductor layer 6, a large number of lead pins 2 can be insulated from each other again.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、共通導
体層6は、導通アームにより接続する必要があるため、
導通アームと共通導体層6との導通を確実にするために
は、共通導体層6の幅をより広くする必要があった(図
3(a)および(b)参照)。しかし、このように共通
導体層6の幅を広くすると、共通導体層6の表面にも多
くのメッキ金属が層着されるため、メッキ金属の無駄が
多くなり、製造コストの増大を招いていた。
However, since the common conductor layer 6 needs to be connected by a conductive arm,
In order to ensure conduction between the conduction arm and the common conductor layer 6, it was necessary to make the width of the common conductor layer 6 wider (see FIGS. 3A and 3B). However, when the width of the common conductor layer 6 is increased in this manner, a large amount of plating metal is deposited on the surface of the common conductor layer 6, so that the waste of the plating metal increases and the manufacturing cost increases. .

【0006】本発明は上記欠点に鑑み、案出されたもの
であり、その目的は、共通導体層6と導通アーム7との
導通を確実にしながらも、メッキ金属の無駄を少なく
し、製造コストを低減できる配線基板の製造方法を提供
することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to reduce the waste of plated metal while ensuring the conduction between the common conductor layer 6 and the conduction arm 7 and to reduce the manufacturing cost. It is an object of the present invention to provide a method of manufacturing a wiring board which can reduce the number of wiring boards.

【0007】[0007]

【課題を解決するための手段】前記目的を達成するため
の請求項1の発明は、矩形状絶縁基板の表面に複数の外
部接続端子が配設されてなる配線基板の製造方法であっ
て、前記複数個の外部接続端子のそれぞれから前記矩形
状絶縁基板の各側面に導出させる導出配線層を形成する
工程と、部分的に幅広部を有する共通導体層を前記矩形
状絶縁基板の各側面に被着し、前記導出配線層を電気的
に接続する工程と、前記共通導体層の幅広部に通電し、
前記複数個の外部接続端子の表面に電解メッキ法により
メッキ金属層を形成する工程と、前記矩形状絶縁基板の
各側面を研磨し、共通導体を除去する工程と、を含む配
線基板の製造方法を要旨とする。
According to a first aspect of the present invention, there is provided a method of manufacturing a wiring board, comprising a plurality of external connection terminals provided on a surface of a rectangular insulating substrate. Forming a lead-out wiring layer leading to each side of the rectangular insulating substrate from each of the plurality of external connection terminals; and forming a common conductor layer having a partially wide portion on each side of the rectangular insulating substrate. Attaching and electrically connecting the lead-out wiring layer, energizing a wide portion of the common conductor layer,
A method of manufacturing a wiring board, comprising: a step of forming a plated metal layer on the surfaces of the plurality of external connection terminals by an electrolytic plating method; and a step of polishing each side surface of the rectangular insulating substrate to remove a common conductor. Is the gist.

【0008】本発明によれば、共通導体層のうち、通電
される部分の近傍を幅広としたので、導電アーム等との
接続を確実にすることができる。さらに、共通導体層の
うち、導電アームと接続されない部分は幅を狭くしたた
め、共通導体層の上に被着するメッキ金属の量を低減で
き、メッキ金属の無駄を最小限に抑えることができる。
According to the present invention, the vicinity of the portion to be energized in the common conductor layer is widened, so that the connection with the conductive arm or the like can be ensured. Furthermore, since the width of the portion of the common conductor layer that is not connected to the conductive arm is reduced, the amount of plating metal deposited on the common conductor layer can be reduced, and the waste of plating metal can be minimized.

【0009】なお、各側面の共通導体層に接続するため
の導通アームが配線基板の保持をより確実にするために
複数あるときは、その複数の導通アームのうちの少なく
とも1つと共通導体層との導通さえ確実になっていれば
よいので、共通導体層のうち複数の導通アームの少なく
とも1つと接続する部分のみ幅広とすればよい。
When there are a plurality of conductive arms for connecting to the common conductor layer on each side surface for more securely holding the wiring board, at least one of the plurality of conductive arms is connected to the common conductor layer. Therefore, it is sufficient that only the portion of the common conductor layer that is connected to at least one of the plurality of conductive arms be widened.

【0010】また、各側面に形成された共通導体層を互
いに導通させるために、前記矩形状絶縁基板の各角部の
内部に隣接する各側面に導出する接続導体層を形成する
と、共通導体層同士の導通をより確実にすることができ
る。
Further, in order to make the common conductor layers formed on the respective side surfaces conductive with each other, a connection conductor layer extending to each adjacent side surface inside each corner of the rectangular insulating substrate is formed. The continuity between them can be further ensured.

【0011】[0011]

【発明の実施の形態】以下、本発明の実施形態を、図面
を参照しつつ説明する。まず、酸化アルミニウム,シリ
カ、カルシア、マグネシア等の原料粉末を適当な有機溶
剤、溶媒を添加混合して泥漿状となすとともにこれをド
クターブレード法やカレンダーロール法等を採用し、シ
ート状に成形することによってセラミックグリーンシー
ト(セラミック生シート)を得る。その後、前記セラミ
ックグリーンシートに適当な打抜き加工法を施し、矩形
状となすことにより、所定枚数の矩形状セラミックグリ
ーンシートを得る。
Embodiments of the present invention will be described below with reference to the drawings. First, a raw material powder of aluminum oxide, silica, calcia, magnesia, or the like is formed into a slurry by adding and mixing an appropriate organic solvent and a solvent, and is formed into a sheet by using a doctor blade method, a calendar roll method, or the like. Thereby, a ceramic green sheet (ceramic green sheet) is obtained. Thereafter, the ceramic green sheets are subjected to a suitable punching process to form a rectangular shape, thereby obtaining a predetermined number of rectangular ceramic green sheets.

【0012】こうして得られた矩形状セラミックグリー
ンシート23には、例えば、図4に示すように焼成後に
所望の信号配線層となる配線メタライズ層28や、焼成
後に異なる絶縁層に形成された信号配線層等を互いに接
続するためのビア導体となるビア29等を形成する他、
焼成後に導出配線層14となる導出メタライズ層24を
形成する。この導出メタライズ層24は、その一部がセ
ラミックグリーンシート23の各側面25に導出されて
いる。さらに、セラミックグリーンシート23の上面各
角部には隣接する側面25に導出される接続メタライズ
層20は、焼成後に接続配線層となり、後述する矩形状
絶縁基板13の各側面15に形成された共通導体層16
を互いに導通させる作用をなす。
The thus obtained rectangular ceramic green sheet 23 includes, for example, a wiring metallization layer 28 which becomes a desired signal wiring layer after firing, and a signal wiring formed on a different insulating layer after firing, as shown in FIG. In addition to forming a via 29 serving as a via conductor for connecting layers and the like to each other,
After the firing, a derived metallized layer 24 to be the derived wiring layer 14 is formed. A part of the derived metallization layer 24 is led to each side surface 25 of the ceramic green sheet 23. Further, the connection metallization layer 20 led out to the side surface 25 adjacent to each corner of the upper surface of the ceramic green sheet 23 becomes a connection wiring layer after firing, and is formed on each side surface 15 of the rectangular insulating substrate 13 described later. Conductive layer 16
Function to conduct each other.

【0013】次に、セラミックグリーンシート23と他
の所定数のセラミックグリーンシートをそれぞれ上下に
積層してセラミックグリーンシート積層体30を形成す
る。セラミックグリーンシート積層体30の各側面35
に側面メタライズ層26を形成する(図5参照)。この
側面メタライズ層26は、その長手方向略中央に他より
も幅が広い幅広部26aを備える。
Next, the ceramic green sheet 23 and a predetermined number of other ceramic green sheets are stacked one above the other to form a ceramic green sheet laminate 30. Each side surface 35 of the ceramic green sheet laminate 30
Then, a side metallization layer 26 is formed (see FIG. 5). The side metallization layer 26 includes a wide portion 26a having a width wider than the others at substantially the center in the longitudinal direction.

【0014】なお、配線メタライズ層28、ビア29、
導出メタライズ層24、および側面メタライズ層26
は、例えば、タングステン(W)、モリブデン(M
o)、マンガン(Mn)等の高融点金属粉末からなり、
該高融点金属粉末に適当な有機溶剤、溶媒等を添加混合
することによって得た金属ペーストを従来周知のスクリ
ーン印刷法を採用して形成される。
The wiring metallization layer 28, the via 29,
Derived metallization layer 24 and side metallization layer 26
Are, for example, tungsten (W), molybdenum (M
o), made of a high melting point metal powder such as manganese (Mn),
A metal paste obtained by adding and mixing an appropriate organic solvent, solvent and the like to the high melting point metal powder is formed by employing a conventionally well-known screen printing method.

【0015】次に、セラミックグリーンシート積層体3
0を、還元雰囲気中、約1600℃で焼成し、各セラミ
ックグリーンシートを焼結一体化して絶縁基板11とな
す。このとき、配線メタライズ層は信号配線層、ビアは
ビア導体、導出メタライズ層は導出配線層14、側面メ
タライズ層26は共通導体層16、接続メタライズ層2
0は接続配線層となる。なお、共通導体層16は、その
長手方向略中央に他の部分よりも幅広の幅広部16aを
有している。さらに、絶縁基板11の表面に形成された
ろう付けパッドにリードピン12を銀ろう等のろう材を
介してろう付けして、配線基板11とする(図6(a)
参照)。
Next, the ceramic green sheet laminate 3
0 is fired at about 1600 ° C. in a reducing atmosphere, and the ceramic green sheets are sintered and integrated to form an insulating substrate 11. At this time, the wiring metallization layer is a signal wiring layer, the via is a via conductor, the derived metallization layer is the derived wiring layer 14, the side metallization layer 26 is the common conductor layer 16, the connection metallization layer 2
0 becomes a connection wiring layer. Note that the common conductor layer 16 has a wide portion 16a wider than other portions at substantially the center in the longitudinal direction. Further, the lead pin 12 is brazed to a brazing pad formed on the surface of the insulating substrate 11 via a brazing material such as silver brazing to form a wiring board 11 (FIG. 6A).
reference).

【0016】次いで、図6(b)に示すように、導通ア
ーム17を幅広部16aに接触させ、リードピン12や
その他所定部分の表面にメッキ金属層を層着させる。こ
のメッキ工程は、具体的には配線基板11をメッキ液中
に浸漬するとともに導通アーム17から共通導体層16
を経由してリードピン12等に一定の電力を印加するこ
とによって行われる。
Next, as shown in FIG. 6B, the conductive arm 17 is brought into contact with the wide portion 16a, and a plating metal layer is deposited on the surfaces of the lead pins 12 and other predetermined portions. In this plating step, specifically, the wiring board 11 is immersed in a plating solution, and the conductive arm 17 is connected to the common conductor layer 16.
This is performed by applying a constant power to the lead pins 12 and the like via the.

【0017】なお、この場合、リードピン12はそれぞ
れが導出配線層14や接続配線層等により共通導体層1
6に電気的に共通に形成されているため、共通導体層1
6に電力を印加すれば総てのリードピン12に電解メッ
キのための電力を印加することが可能となり、多数のリ
ードピン12の露出する外表面に一度にメッキ金属層を
形成することができる。メッキ金属としては、ニッケル
および金が挙げられるが、その他の金属であってもよ
い。
In this case, each of the lead pins 12 is connected to the common conductor layer 1 by the lead-out wiring layer 14 and the connection wiring layer.
6, the common conductor layer 1
When power is applied to the lead 6, power for electrolytic plating can be applied to all the lead pins 12, and a plating metal layer can be formed on the exposed outer surfaces of many lead pins 12 at once. Examples of the plating metal include nickel and gold, but other metals may be used.

【0018】また、上記メッキ工程においては、共通導
体層16の表面にもメッキ金属が層着されるが、共通導
体層16の幅広部16a以外は、幅が狭くなっているの
で、無駄なメッキ金属の層着を最小限に抑えることがで
きる。なお、幅広部16a以外の共通導体層16の幅
は、側面15に表出した導出配線層と確実に導通させる
ために、共通導体層16(側面メタライズ層26)を形
成する際の印刷精度等を考慮して定めればよいが、0.
4mm〜1.0mmの範囲が好ましく、本実施形態で
は、0.7mmとした。
In the above-mentioned plating step, a plating metal is also deposited on the surface of the common conductor layer 16. However, since the width of the common conductor layer 16 other than the wide portion 16 a is narrow, unnecessary plating is performed. Metal layering can be minimized. The width of the common conductor layer 16 other than the wide portion 16a is determined by the printing accuracy or the like when the common conductor layer 16 (side metallization layer 26) is formed in order to ensure conduction with the derived wiring layer exposed on the side surface 15. May be determined in consideration of
The range of 4 mm to 1.0 mm is preferable, and in the present embodiment, it is 0.7 mm.

【0019】また、導通アーム17を共通導体層16の
幅広部16aに接触させるので、両者の導通を確実にす
ることができる。幅広部の幅は、広ければ広いほど導通
アーム17との接触が容易になるが、一定以上広くして
も意味が無く、却ってメッキ金属の無駄を引き起こして
しまうこともあるため、導通アーム17の形状や大きさ
等を考慮して適当な幅に選定するとよい。1.0mm〜
2.0mmの範囲が好ましく、本実施例では、1.6m
mとした。
Further, since the conduction arm 17 is brought into contact with the wide portion 16a of the common conductor layer 16, conduction between the two can be ensured. As the width of the wide portion becomes wider, the contact with the conducting arm 17 becomes easier. However, it does not make sense to make the width wider than a certain value, and the plated metal may be wasted. An appropriate width should be selected in consideration of the shape, size, and the like. 1.0mm ~
A range of 2.0 mm is preferable, and in this embodiment, 1.6 m
m.

【0020】さらに、幅広部とその他の部分の幅は、
0.2mm以上あることが好ましい。それ以下である
と、メッキ金属の無駄を低減する効果がわずかになって
しまうからである。
Further, the width of the wide portion and other portions is
It is preferably at least 0.2 mm. If the amount is less than that, the effect of reducing the waste of the plating metal becomes small.

【0021】そして、次に、矩形状絶縁基板13の側面
15をグラインダー等の機械的研磨装置により研磨し、
共通導体層16を除去することにより、各リードピン2
や導出配線層14を電気的に独立させ、配線基板が完成
する。このような配線基板は、例えば半導体素子等の電
子部品が搭載される。上記実施形態では詳述しなかった
が、半導体素子等を搭載するために必要な従来周知の構
造を備えることができる。
Then, the side surface 15 of the rectangular insulating substrate 13 is polished by a mechanical polishing device such as a grinder.
By removing the common conductor layer 16, each lead pin 2
And the lead-out wiring layer 14 are electrically independent, and the wiring board is completed. An electronic component such as a semiconductor element is mounted on such a wiring board. Although not described in detail in the above embodiment, a conventionally known structure necessary for mounting a semiconductor element or the like can be provided.

【0022】なお、矩形状絶縁基板11は酸化アルミニ
ウム質焼結体、ムライト質焼結体、窒化アルミニウム質
焼結体、炭化珪素質焼結体等の電気絶縁材料からなる。
また、リードピン12は、コバール(Fe−Ni−Co
合金)や42アロイ(Fe−Ni合金)等の金属からな
り、コバール金属等のインゴット(塊)を圧延加工法や
打抜き加工法等、従来周知の金属加工法を採用すること
によって所定のピン状に形成される。
The rectangular insulating substrate 11 is made of an electrically insulating material such as a sintered body of aluminum oxide, a sintered body of mullite, a sintered body of aluminum nitride, and a sintered body of silicon carbide.
The lead pins 12 are made of Kovar (Fe-Ni-Co).
Alloys) and 42 alloys (Fe-Ni alloys). A predetermined pin shape is obtained by employing a conventionally known metal working method such as a rolling method or a punching method for an ingot (lumps) such as Kovar metal. Formed.

【0023】上記実施形態では、図6にしめす形状の共
通導体層16を形成したが、この形状に限定されず、例
えば、図7(a)〜(c)に示すような形状であっても
よい。すなわち、図7(a)に示す矩形状絶縁基板31
は、共通導体層36の両側に突出する幅広部36aを有
している。図7(b)に示す矩形状絶縁基板41は、共
通導体46の両側に突出する幅広部46aを有してお
り、この幅広部46aは略長円形をしている。図7
(c)に示す矩形状絶縁基板51は、共通導体層56の
片側に突出する2つの幅広部56aを備える。これによ
り、2つの導電アームとの接触が確実となる。なお、図
7(a)〜(c)では、要部のみ示したため、リードピ
ン等は省略した。
In the above embodiment, the common conductor layer 16 having the shape shown in FIG. 6 is formed. However, the present invention is not limited to this shape. For example, the shape shown in FIGS. Good. That is, the rectangular insulating substrate 31 shown in FIG.
Have wide portions 36 a protruding on both sides of the common conductor layer 36. The rectangular insulating substrate 41 shown in FIG. 7B has wide portions 46a protruding on both sides of the common conductor 46, and the wide portions 46a are substantially oval. FIG.
The rectangular insulating substrate 51 shown in (c) includes two wide portions 56 a protruding on one side of the common conductor layer 56. This ensures contact with the two conductive arms. 7 (a) to 7 (c), only the main parts are shown, and the lead pins and the like are omitted.

【0024】導通アームは、各側面毎に複数配設されて
いてもよい。導通アームが多ければその分配線基板の保
持が容易且つ確実になる。この場合、複数の導通アーム
のうち、少なくとも一つが幅広部に対応していればよ
い。すなわち、総ての導通アームに対応する部分に幅広
部を設ける必要はない。
A plurality of conductive arms may be provided for each side surface. The more conductive arms, the easier and more reliable the holding of the wiring board. In this case, at least one of the plurality of conductive arms may correspond to the wide portion. That is, it is not necessary to provide a wide portion in a portion corresponding to all the conductive arms.

【0025】配線基板の保持を容易にするためには、矩
形状絶縁基板の4つの側辺のうち、1組の対向する2辺
の側面の共通導体層に導通アームを接触させ、導通アー
ムにより配線基板を挟持するとよい。この場合、導通ア
ームに接触させる2辺の側面の共通導体層にのみ幅広部
を設けてもよいが、そうすると、導通アームで挟持する
際に、幅広部が設けられた辺(側面)を確認して、配線
基板を導通アームに取り付ける必要がある。したがっ
て、矩形状絶縁基板の4つの側辺のうち、1組の対向す
る2辺の側面の共通導体層に導通アームを接触させ、導
通アームにより配線基板を挟持する場合であっても、4
辺,すなわち、すべての側面の共通導体層に幅広部を設
けるとよい。このような構成によれば、導通アームに取
り付ける際に、配線基板の方向を確認する必要がないの
で、配線基板の導通アームへの取付け作業が容易にな
る。
In order to facilitate the holding of the wiring board, a conductive arm is brought into contact with a common conductor layer on one set of two sides of the four sides of the rectangular insulating substrate, and the conductive arm is It is good to hold a wiring board. In this case, the wide portion may be provided only on the common conductor layer on the two sides that are in contact with the conductive arm. However, when sandwiched by the conductive arm, the side (side) provided with the wide portion is confirmed. Therefore, it is necessary to attach the wiring board to the conduction arm. Therefore, even when the conductive arm is brought into contact with the common conductor layer on the side surface of one set of two opposing sides of the four sides of the rectangular insulating substrate, and the wiring substrate is sandwiched between the conductive arms, even if
A wide portion may be provided on the side, that is, on the common conductor layer on all side surfaces. According to such a configuration, it is not necessary to check the direction of the wiring board when attaching the wiring board to the conductive arm, so that the work of attaching the wiring board to the conductive arm becomes easy.

【0026】なお、本発明は、上述した実施形態に限定
されるものではなく、本発明の要旨を逸脱しない範囲で
あれば種々の変更が可能である。特に、共通導体層の幅
広部の形状は様々な形態が考えられる。さらに、各側面
毎で幅広部の形態を適宜異なる形態とすることも可能で
ある。
It should be noted that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention. In particular, various shapes can be considered for the shape of the wide portion of the common conductor layer. Further, the form of the wide portion may be appropriately changed for each side surface.

【0027】[0027]

【発明の効果】本発明の配線基板の製造方法によれば、
共通導体層と導通アームとの導通を確実にしながらも、
共通導体層に層着されるメッキ金属を最小限にし、製造
コストを低減することができる。
According to the method of manufacturing a wiring board of the present invention,
While ensuring conduction between the common conductor layer and the conduction arm,
The plating metal deposited on the common conductor layer can be minimized, and the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来の配線基板の製造方法を示す図であり、
(a)は要部斜視図、(b)は要部断面である。
FIG. 1 is a diagram showing a conventional method for manufacturing a wiring board;
(A) is a perspective view of a main part, and (b) is a cross section of the main part.

【図2】従来の配線基板の製造方法を示す要部断面図で
あり、共通導体層6と導通アーム7を接続した状態を示
す図である。
FIG. 2 is a cross-sectional view of a main part showing a conventional method of manufacturing a wiring board, showing a state where a common conductor layer 6 and a conductive arm 7 are connected.

【図3】従来の配線基板の製造方法を示す図であり、
(a)は要部斜視図、(b)は要部断面である。
FIG. 3 is a diagram showing a conventional method for manufacturing a wiring board;
(A) is a perspective view of a main part, and (b) is a cross section of the main part.

【図4】本発明の実施形態に係る配線基板の製造方法に
示す図であり、セラミックグリーンシートの平面図であ
る。
FIG. 4 is a diagram illustrating a method for manufacturing a wiring board according to an embodiment of the present invention, and is a plan view of a ceramic green sheet.

【図5】本発明の実施形態に係る配線基板の製造方法に
示す図であり、セラミックグリーンシート積層体30を
示す図である。
FIG. 5 is a diagram illustrating a method for manufacturing a wiring board according to an embodiment of the present invention, and is a diagram illustrating a ceramic green sheet laminate 30.

【図6】本発明の実施形態に係る配線基板の製造方法に
示す図であり、(a)は要部斜視図、(b)は要部断面
である。
6A and 6B are diagrams illustrating a method for manufacturing a wiring board according to an embodiment of the present invention, wherein FIG. 6A is a perspective view of a main part, and FIG.

【図7】本発明の実施形態に係る配線基板の製造方法の
変形例を示す図であり、(a)〜(c)はそれぞれ異な
る形態の共通導体層を示す。
FIG. 7 is a view showing a modification of the method of manufacturing a wiring board according to the embodiment of the present invention, wherein (a) to (c) show different forms of the common conductor layer.

【符号の説明】[Explanation of symbols]

1、11:配線基板 2、12:リードピン 3、13:矩形状絶縁基板 4、14:導出配線層 5、15:側面 6、16、:共通導体層 16a:幅広部 7、17:導通アーム 1, 11: Wiring board 2, 12: Lead pin 3, 13: Rectangular insulating substrate 4, 14: Derived wiring layer 5, 15: Side surface 6, 16 ,: Common conductor layer 16a: Wide portion 7, 17: Conductive arm

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 矩形状絶縁基板の表面に複数の外部接続
端子が配設されてなる配線基板の製造方法であって、 前記複数個の外部接続端子のそれぞれから前記矩形状絶
縁基板の各側面に導出させる導出配線層を形成する工程
と、部分的に幅広部を有する共通導体層を前記矩形状絶
縁基板の各側面に被着し、前記導出配線層を電気的に接
続する工程と、 前記共通導体層の幅広部に通電し、前記複数個の外部接
続端子の表面に電解メッキ法によりメッキ金属層を形成
する工程と、 前記矩形状絶縁基板の各側面を研磨し、共通導体を除去
する工程と、を含む配線基板の製造方法。
1. A method for manufacturing a wiring board, comprising a plurality of external connection terminals provided on a surface of a rectangular insulating substrate, wherein each side surface of the rectangular insulating substrate is formed from each of the plurality of external connection terminals. Forming a lead-out wiring layer to be led out, and applying a common conductor layer having a partially wide portion to each side surface of the rectangular insulating substrate, and electrically connecting the lead-out wiring layer; Energizing a wide portion of the common conductor layer to form a plated metal layer on the surfaces of the plurality of external connection terminals by electrolytic plating, and polishing each side surface of the rectangular insulating substrate to remove the common conductor. And a method for manufacturing a wiring board.
JP01495799A 1999-01-22 1999-01-22 Manufacturing method of wiring board Expired - Fee Related JP3273187B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP01495799A JP3273187B2 (en) 1999-01-22 1999-01-22 Manufacturing method of wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01495799A JP3273187B2 (en) 1999-01-22 1999-01-22 Manufacturing method of wiring board

Publications (2)

Publication Number Publication Date
JP2000216286A JP2000216286A (en) 2000-08-04
JP3273187B2 true JP3273187B2 (en) 2002-04-08

Family

ID=11875469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01495799A Expired - Fee Related JP3273187B2 (en) 1999-01-22 1999-01-22 Manufacturing method of wiring board

Country Status (1)

Country Link
JP (1) JP3273187B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6298363B2 (en) * 2014-06-03 2018-03-20 日本特殊陶業株式会社 Wiring board

Also Published As

Publication number Publication date
JP2000216286A (en) 2000-08-04

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