JP4355097B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

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Publication number
JP4355097B2
JP4355097B2 JP2000330132A JP2000330132A JP4355097B2 JP 4355097 B2 JP4355097 B2 JP 4355097B2 JP 2000330132 A JP2000330132 A JP 2000330132A JP 2000330132 A JP2000330132 A JP 2000330132A JP 4355097 B2 JP4355097 B2 JP 4355097B2
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green sheet
ceramic green
metal layer
wiring board
wiring
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JP2002134646A (en
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秀憲 田中
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Description

【０００１】
【発明の属する技術分野】
本発明は半導体素子や表面弾性波素子等の電子部品が搭載される配線基板の製造方法に関するものである。
【０００２】
【従来の技術】
従来、半導体素子や表面弾性波素子等の電子部品を搭載するための配線基板は、例えばその上面の中央部に電子部品が塔載される搭載部を有する四角形状のセラミックスより成る絶縁基体と、この絶縁基体の搭載部から外部に導出する配線導体と、絶縁基体の上面外周部に搭載部を取り囲むように枠状に形成されたシール金属層とを具備している。
【０００３】
そして、絶縁基体の搭載部に電子部品を塔載するとともに、この電子部品の各電極を配線導体に電気的に接続し、しかる後、シール金属層に例えば封止用シールリングを介して金属からなる蓋体を接合させ、絶縁基体と蓋体とからなる容器の内部に電子部品を気密に封止することによって製品としての電子装置となる。
【０００４】
ところでこのような配線基板は、近時における電子装置の小型化の要求に伴い、その大きさが数ｍｍ角程度と極めて小さく、薄いものとなってきているとともに、封止用シールリングを用いずシール金属層に蓋体を直接溶接する方法がとられるようになってきている。
【０００５】
なお、前記シール金属層に蓋体を直接、溶接接合する場合、シール金属層の絶縁基体に対する接合強度を強いものとしておく必要があり、そのためシール金属層は絶縁基体の上面外周縁まで施し、絶縁基体との接合面積を広いものとしてある。
【０００６】
またこのような小型化した配線基板は、その取り扱いを容易とするため、さらにまたセラミック配線基板および電子装置の製作効率をよくするために、多数個の配線基板を１枚の広面積のセラミック基板から同時集約的に得るようになした、いわゆる多数個取り配線基板の形態で、通常、以下の工程により製作される。
【０００７】
即ち、
（１）セラミックグリーンシートを縦方向及び横方向の仮想線によって四角形状をなす複数の領域に区画するとともに各領域に金属ペースト所定パターンに印刷塗布し配線用導体を形成する工程と
（２）前記セラミックグリーンシートの各領域の外周縁に沿って金属ペーストを０．３ｍｍ〜０．６ｍｍの幅で枠状に印刷塗布し、シール用金属層を形成する工程と
（３）前記セラミックグリーンシートの上面で横方向の仮想線上に第１の分割溝を、縦方向の仮想線上に第２の分割溝を、例えば、金属製の刃をセラミックグリーンシート上に各仮想線に沿って押圧することにより、順次形成する工程と
（４）前記セラミックグリーンシートを焼成し、セラミック焼結体から成る絶縁基体に配線導体及びシール金属層を被着させた複数個の配線基板を有するセラミック基板を形成する工程と
（５）前記セラミック基板を第１及び第２の分割溝に沿って曲げ応力を加えることにより切断し、多数の配線基板を個々に分割する工程
とにより製作されている。
【０００８】
なお、前記セラミックグリーンシートに形成された第１の分割溝はセラミックグリーンシートに第２の分割溝を形成するために金属製の刃を押圧した際、閉じるような変形を受け、これによって第１の分割溝の幅は、第２の分割溝の幅に対して約７０％〜９０％と狭いものとなっている。
【０００９】
【発明が解決しようとする課題】
しかしながら、上記従来の配線基板では、シール用金属層がセラミックグリーンシートの各四角形状の領域の外周縁まで形成されていること、第１の分割溝の幅が狭くなっていること等からセラミックグリーンシートを焼成し、絶縁基体と成す際に、セラミックグリーンシートの焼成収縮によって第１の分割溝の幅がより一層狭いものとなり、第１の分割溝を挟んで隣合った同士のシール金属層が、癒着してしまうという欠点を有していた。
【００１０】
特にこのようなシール金属層同士の癒着は各四角形状の領域のそれぞれの辺の中央部で起こり易く、シール金属層同士が癒着すると分割溝に沿って各絶縁基体に分割する時、大きな力が必要となり分割が困難となるとともに、本来分割される箇所以外の所で割れを発生し、所定形状の絶縁基体を得ることができないという欠点が誘発されてしまう。
【００１１】
本発明は上記欠点に鑑み案出されたものであり、その目的は、配線基板を多数個取りのセラミック基板の形態で製作する方法において、シール金属層が分割溝を挟んで隣合った同士で癒着することを防止し、セラミック基板を容易かつ正確に分割溝に沿って分割することが可能な配線基板の製造方法を提供することにある。
【００１２】
【課題を解決するための手段】
本発明の配線基板の製造方法は、
（１）セラミックグリーンシートを縦方向及び横方向の仮想線によって四角形状をなす複数の領域に区画するとともに各領域に配線用導体を形成する工程と、
（２）前記セラミックグリーンシートの各領域の外周縁に、金属ペーストを０．３〜０．６ｍｍの幅で枠状に印刷塗布し、シール用金属層を形成する工程と、
（３）前記セラミックグリーンシートの横方向の仮想線上で各領域の中央部に直径０．１ｍｍ〜０．２５ｍｍの貫通孔を形成する工程と、
（４）前記セラミックグリーンシートの上面で横方向の仮想線上に第１の分割溝を形成する工程と、
（５）前記セラミックグリーンシートの上面で縦方向の仮想線上に第２の分割溝を形成する工程と、
（６）前記セラミックグリーンシートを焼成し、セラミック焼結体から成る絶縁基体に配線導体及びシール金属層被着させた複数個の配線基板を有するセラミック基板を形成する工程と、
（７）前記セラミック基板を第１及び第２の分割溝に沿って切断し、多数の配線基板を個々に分割する工程
とから成ることを特徴とするものである。
【００１３】
本発明の配線基板の製造方法によれば、セラミックグリーンシートの横方向の仮想線上で四角形状の各領域の中央部に直径０．１ｍｍ〜０．２５ｍｍの貫通孔を形成した後、セラミックグリーンシートの上面で横方向の仮想線上に第１の分割溝を、セラミックグリーンシートの上面で縦方向の仮想線上に第２の分割溝を順次形成するようになしたことから、第２の分割溝を形成する際に第１の分割溝の幅が狭くなること及びセラミックグリーンシートの焼成収縮等に起因して各四角形状の領域のそれぞれの辺の中央部でシール金属層同士が癒着しようとしてもその癒着は第１の分割溝の各領域の中央部に貫通孔が形成されていることによって効果的に阻止され、その結果、分割溝に沿って各絶縁基体に分割する時、小さな力で分割が可能となるとともに所定箇所で正確に分割が可能となり、所定形状の絶縁基体を正確に得ることができる。
【００１４】
【発明の実施の形態】
次に本発明を添付図面に基づき詳細に説明する。
図１は本発明の製造方法で形成された配線基板を半導体素子収納用パッケージに適用した場合の一実施例を示し、図中、Ａは絶縁基体１と配線導体２とシール金属層３とから成る配線基板、４は蓋体である。この配線基板Ａの絶縁基体１と蓋体４とで半導体素子５を収容するための容器６が構成される。
【００１５】
前記絶縁基体１は半導体素子５を支持する支持部材として作用し、上面の略中央部に半導体素子搭載部１ａを有し、この搭載部１ａ上に半導体素子５がガラス、ロウ材、樹脂等の接着材を介して取着固定される。
【００１６】
また前記配線導体２は半導体素子５の各電極を外部電気回路に接続するための導電路として作用し、半導体素子５の各電極をボンディングワイヤ７を介し配線導体２に接続することによって半導体素子５の各電極は配線導体２を介して外部電気回路に接続されることとなる。
【００１７】
更に前記シール金属層３は蓋体４をロウ材を介して接合するための下地金属層として作用し、シール金属層３上に蓋体４を金−錫等のロウ材を介して位置決め載置するとともに所定温度で熱処理することによりシール金属層３上に蓋体４が接合され、絶縁基体１と蓋体４とから成る容器６内部に半導体素子５が気密に収容される。
【００１８】
前記配線基板Ａは、分割溝で区画された配線基板Ａとなる領域を多数個有するセラミック基板を、前記分割溝に沿って切断することにより製作される。
【００１９】
この配線基板Ａの製造方法について、次に、図２乃至図７に基づいて説明する。なお、図中、図１と同一箇所には同一符号が付してある。
【００２０】
まず、図２に示す如く、セラミックグリーンシート１１を横方向の仮想線１２ａ及び縦方向の仮想線１２ｂによって四角形状をなし中央部に半導体素子搭載部１ａを有する複数の領域１３に区画するとともに各四角形状の領域１３の搭載部１ａ周辺に配線用導体１４を形成する。
【００２１】
前記セラミックグリーンシート１１は、例えば、絶縁基体１が酸化アルミニウム質焼結体で形成されている場合であれば、酸化アルミニウム、酸化ケイ素、酸化カルシウム、酸化マグネシウム等の原料粉末に適当な有機バインダおよび溶剤を添加混合して泥漿状となすとともに、従来周知のドクターブレード法やカレンダーロール法等を用いてシート状に成形することによって形成される。
【００２２】
また前記配線用導体１４は、タングステン、モリブデン、マンガン、銅、銀等の金属粉末から成り、タングステン等の金属粉末に適当な有機バインダーや溶剤を添加混合して得た金属ペーストをセラミックグリーンシート１１の仮想線によって区画された各四角形状の領域１３に従来周知のスクリーン印刷法により所定パターンに印刷塗布することによって形成される。
【００２３】
次に、図３に示す如く、前記セラミックグリーンシート１１の各四角形状の領域１３の外周縁に金属ペーストを０．３〜０．６ｍｍの幅で枠状に印刷塗布し、シール用金属層１５を形成する。
【００２４】
前記シール用金属層１５を形成する金属ペーストは、配線用導体１４を形成する金属ペーストと同様に、タングステン、モリブデン、マンガン、銅、銀等の金属粉末に適当な有機バインダーや溶剤を添加混合することにより作製される。
【００２５】
次に、図４に示す如く、前記セラミックグリーンシート１１の横方向の仮想線１２ａ上で各領域１３の中央部に貫通孔１６を形成する。
【００２６】
前記貫通孔１６は、横方向の仮想線１２ａを挟んで隣接するシール用金属層１５の各領域１３の中央部に一定の隙間を形成する作用をなし、この隙間により、セラミックグリーンシート１１に印刷、形成したシール用金属層１５が、後の工程の焼成時、分割溝を挟んで隣合った同士で癒着することが阻止される。
【００２７】
前記貫通孔１６は、例えば、金属製の打ち抜きピンを、セラミックグリーンシート１１の仮想線上の所定位置に押圧するとともに厚み方向に貫通させることにより形成される。
【００２８】
次に、図５に示す如く、前記セラミックグリーンシート１１の上面で横方向の仮想線１２ａ上に第１の分割溝１７ａを形成し、その後、縦方向の仮想線１２ｂ上に第２の分割溝１７ｂを形成する。
【００２９】
前記第１の分割溝１７ａおよび第２の分割溝１７ｂは、例えば、Ｖ字状等、前記各分割溝の所定の断面形状と同じ縦断面形を有する金属製の刃をセラミックグリーンシート１１の上面に押圧することにより形成される。
【００３０】
なお、この場合、前記第１の分割溝１７ａは、セラミックグリーンシート１１に第２の分割溝１７ｂを形成するために金属製の刃を押圧した際、閉じるような変形を受け、これによって第１の分割溝１７ａの幅は、第２の分割溝１７ｂの幅に対して約７０％〜９０％と狭いものとなっている。
【００３１】
次に、前記セラミックグリーンシート１１を、還元雰囲気中、約１６００℃の温度で焼成し、図６に示す如く、セラミック焼結体から成る絶縁基体１に配線導体２及びシール金属層３を被着させた複数個の配線基板Ａを有するセラミック基板１８を形成する。この焼成の際、セラミックグリーンシート１１の各分割溝１７ａ、１７ｂは、セラミックグリーンシート１１の四角形状の各領域１３の中央部の焼結開始が端部に比べて遅く、収縮量も小さいことから、各領域１３の中央部で閉じるようにして収縮する。このため分割溝の幅は、上記セラミックグリーンシートへの形成時の変形と相俟って、特に第１の分割溝１７ａの中央部で非常に狭いものとなっている。しかしながら、第１の分割溝１７ａの中央部には貫通孔１６が形成されており、該貫通孔１６によって四角形状をなす各配線基板Ａのそれぞれの辺の中央部でシール金属層３同士が癒着しようとするのが効果的に阻止され、隣接するシール金属層３同士が癒着することはない。
【００３２】
次に、前記セラミック基板１８を第１及び第２の分割溝１７ａ、１７ｂに沿って切断し、図７に示す如く、中央部に搭載部１ａを有する絶縁基体１に配線導体２及びシール金属層３を形成した多数の配線基板Ａを個々に分割する。
【００３３】
前記セラミック基板１８の切断は、順次、第１、第２の各分割溝１７ａ、１７ｂに沿ってセラミック基板１８に曲げ応力を加えて撓折することにより行われる。
【００３４】
また前記セラミック基板１８を縦横の分割溝１７ａ、１７ｂに沿って分割する際、隣接するシール金属層３同士は貫通孔１６により癒着が阻止されているため分割を小さな力で行なうことが可能となり、同時に分割を分割溝１７ａ、１７ｂに沿って正確に行なうことができ、所定形状の配線基板Ａを正確に得ることができる。
【００３５】
なお、前記貫通孔１６は、その直径が０．１ｍｍよりも小さくなると、第１の分割溝１７ａの、各領域１３の中央部を挟んで隣接するシール金属層３同士が癒着するのを効果的に阻止することができず、また０．２５ｍｍよりも大きくなると、貫通孔１６の形成部位におけるシール金属層３の幅が狭くなり過ぎ、蓋体４とシール金属層３との接合面積が不十分となり、蓋体４の接合強度や気密封止の長期信頼性を劣化させてしまう。従って、前記貫通孔１６は、その直径が０．１ｍｍ〜０．２５ｍｍの範囲に特定される。
【００３６】
かくして得られた配線基板Ａは、絶縁基体１の上面に半導体素子５を搭載するとともに半導体素子５の電極を配線導体２に電気的に接続し、シール金属層３に蓋体４をロウ材等の封止材を介して接合することにより、半導体素子５が絶縁基体１と蓋体４とで構成される容器６内部に気密に封止されて半導体装置となり、外部電気回路に実装することにより半導体素子５の電極が外部電気回路と電気的に接続されることとなる。
【００３７】
なお、前記蓋体４のシール金属層３への接合は、例えば、金−錫ロウ材を介してシール金属層３上に蓋体４を位置決め当接するとともに、ロウ材を加熱溶融させてシール金属層３と蓋体４との接合する面に濡れ広がらせることにより行われる。
【００３８】
また前記シール金属層３は、その幅が０．３ｍｍ未満となると、貫通孔１６形成部位におけるシール金属層３の幅が狭くなり過ぎ、蓋体４とシール金属層３とを強固に接合させることができず、蓋体の接合強度や気密封止の長期信頼性を劣化させてしまい、０．６ｍｍを超えると配線基板Ａを小型化することができなくなるとともに、封止材がシール金属層３と蓋体４との接合面積に比べて広く流れ過ぎ蓋体４の接合強度が弱くなり、また蓋体４の接合位置がずれ易くなってしまう。従って、前記シール金属層３は、その幅が０．３ｍｍ〜０．６ｍｍの範囲に特定される。
【００３９】
更に前記各配線基板Ａのシール金属層３および配線導体２はその表面にニッケル、銅、パラジウム、金、錫等の金属またはその合金から成るメッキ層（非図示）を２μｍ〜２０μｍの厚みに被着させておくとシール金属層３および配線導体２の酸化腐食が有効に防止されるとともに、ボンディングワイヤ７のボンディング性や蓋体４の溶接接合の強度等が良好となる。従って、前記各配線基板Ａのシール金属層３および配線導体２はその表面にニッケル、銅、パラジウム、金、錫等の金属またはその合金から成るメッキ層（非図示）を２μｍ〜２０μｍの厚みに被着させておくことが好ましい。
本発明はまた上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば、上述の実施例では本発明の配線基板を半導体素子収納用パッケージに適用した例で説明したが、これを、表面弾性波素子等の電子部品を搭載する配線基板に適用してもよい。
【００４０】
【発明の効果】
本発明の配線基板の製造方法によれば、セラミックグリーンシートの横方向の仮想線上で四角形状の各領域の中央部に直径０．１ｍｍ〜０．２５ｍｍの貫通孔を形成した後、セラミックグリーンシートの上面で横方向の仮想線上に第１の分割溝を、セラミックグリーンシートの上面で縦方向の仮想線上に第２の分割溝を順次形成するようになしたことから、第２の分割溝を形成する際に第１の分割溝の幅が狭くなること及びセラミックグリーンシートの焼成収縮等に起因して各四角形状の領域のそれぞれの辺の中央部でシール金属層同士が癒着しようとしてもその癒着は第１の分割溝の各領域の中央部に貫通孔が形成されていることによって効果的に阻止され、その結果、分割溝に沿って各絶縁基体に分割する時、小さな力で分割が可能となるとともに所定箇所で正確に分割が可能となり、所定形状の絶縁基体を正確に得ることができる。
【図面の簡単な説明】
【図１】本発明の配線基板を半導体素子収納用パッケージに適用した場合の一実施例を示す断面図である。
【図２】図１に示す半導体素子収納用パッケージに使用される配線基板の製造方法を説明するための各工程毎の平面図である。
【図３】図１に示す半導体素子収納用パッケージに使用される配線基板の製造方法を説明するための各工程毎の平面図である。
【図４】図１に示す半導体素子収納用パッケージに使用される配線基板の製造方法を説明するための各工程毎の平面図である。
【図５】図１に示す半導体素子収納用パッケージに使用される配線基板の製造方法を説明するための各工程毎の平面図である。
【図６】図１に示す半導体素子収納用パッケージに使用される配線基板の製造方法を説明するための各工程毎の平面図である。
【図７】図１に示す半導体素子収納用パッケージに使用される配線基板の製造方法を説明するための各工程毎の平面図である。
【符号の説明】
１・・・・絶縁基体
１ａ・・・搭載部
２・・・・配線導体
３・・・・シール金属層
Ａ・・・・配線基板
４・・・・蓋体
５・・・・半導体素子
６・・・・容器
７・・・・ボンディングワイヤ
１１・・・セラミックグリーンシート
１２ａ・・横方向の仮想線
１２ｂ・・縦方向の仮想線
１３・・・領域
１４・・・配線用導体
１５・・・シール用金属層
１６・・・貫通孔
１７ａ・・第１の分割溝
１７ｂ・・第２の分割溝
１８・・・セラミック基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a wiring board on which electronic components such as semiconductor elements and surface acoustic wave elements are mounted.
[0002]
[Prior art]
Conventionally, a wiring board for mounting an electronic component such as a semiconductor element or a surface acoustic wave element includes, for example, an insulating base made of a rectangular ceramic having a mounting portion on which an electronic component is mounted at the center of its upper surface, A wiring conductor led out from the mounting portion of the insulating base and a seal metal layer formed in a frame shape so as to surround the mounting portion on the outer peripheral portion of the upper surface of the insulating base.
[0003]
And while mounting an electronic component on the mounting part of an insulating base | substrate, each electrode of this electronic component is electrically connected to a wiring conductor, and after that, from a metal via a sealing ring for sealing, for example. An electronic device as a product is obtained by bonding a lid body and sealing an electronic component inside a container composed of an insulating base and a lid body.
[0004]
By the way, with the recent demand for miniaturization of electronic devices, such wiring boards have become extremely small and have a thickness of about several millimeters square, and do not use a sealing ring for sealing. A method of directly welding the lid to the seal metal layer has been adopted.
[0005]
When the lid is directly welded to the seal metal layer, the seal metal layer needs to have a strong bonding strength to the insulating base, and therefore, the seal metal layer is applied to the outer periphery of the upper surface of the insulating base and insulated. The bonding area with the substrate is wide.
[0006]
In addition, in order to facilitate the handling of such a miniaturized wiring board, and to improve the manufacturing efficiency of the ceramic wiring board and the electronic device, a large number of wiring boards are combined into a single large-area ceramic board. In the form of a so-called multi-piece wiring board that is obtained collectively from the above, it is usually manufactured by the following steps.
[0007]
That is,
(1) a step of partitioning the ceramic green sheet into a plurality of rectangular regions by vertical and horizontal imaginary lines and printing and applying a predetermined pattern of metal paste to each region to form a wiring conductor; Forming a metal layer for sealing by applying a metal paste in a frame shape with a width of 0.3 mm to 0.6 mm along the outer peripheral edge of each region of the ceramic green sheet; and (3) an upper surface of the ceramic green sheet. By pressing the first dividing groove on the horizontal imaginary line, the second dividing groove on the imaginary line in the vertical direction, for example, by pressing a metal blade on the ceramic green sheet along each imaginary line, And (4) a plurality of wiring boards in which the ceramic green sheet is fired and a wiring conductor and a sealing metal layer are deposited on an insulating base made of a ceramic sintered body. And (5) cutting the ceramic substrate by applying a bending stress along the first and second dividing grooves, and dividing the plurality of wiring substrates individually. Yes.
[0008]
The first dividing groove formed in the ceramic green sheet is deformed so as to close when a metal blade is pressed to form the second dividing groove in the ceramic green sheet. The width of the divided grooves is as narrow as about 70% to 90% with respect to the width of the second divided grooves.
[0009]
[Problems to be solved by the invention]
However, in the above-described conventional wiring board, the sealing metal layer is formed up to the outer peripheral edge of each square-shaped region of the ceramic green sheet, and the width of the first dividing groove is reduced. When the sheet is fired to form an insulating substrate, the width of the first dividing groove becomes narrower due to the firing shrinkage of the ceramic green sheet, and the seal metal layers adjacent to each other across the first dividing groove are formed. , Had the disadvantage of adhering.
[0010]
In particular, such adhesion between the seal metal layers is likely to occur at the center of each side of each quadrangular region, and when the seal metal layers adhere to each other, a large force is generated when the seal metal layers are divided into the respective insulating bases along the dividing grooves. It becomes necessary and difficult to divide, and cracks are generated in places other than the part that is originally divided, leading to a disadvantage that an insulating substrate having a predetermined shape cannot be obtained.
[0011]
The present invention has been devised in view of the above-described drawbacks, and the object of the present invention is to manufacture a wiring board in the form of a multi-piece ceramic substrate, in which a sealing metal layer is adjacent to each other with a dividing groove interposed therebetween. An object of the present invention is to provide a method of manufacturing a wiring board that prevents adhesion and can divide a ceramic substrate along a dividing groove easily and accurately.
[0012]
[Means for Solving the Problems]
The manufacturing method of the wiring board of the present invention includes:
(1) a step of partitioning the ceramic green sheet into a plurality of rectangular regions by vertical and horizontal virtual lines and forming a wiring conductor in each region;
(2) A step of printing and applying a metal paste in a frame shape with a width of 0.3 to 0.6 mm on the outer peripheral edge of each region of the ceramic green sheet to form a metal layer for sealing;
(3) forming a through hole having a diameter of 0.1 mm to 0.25 mm in the center of each region on the horizontal imaginary line of the ceramic green sheet;
(4) forming a first divided groove on a horizontal imaginary line on the upper surface of the ceramic green sheet;
(5) forming a second divided groove on the imaginary line in the vertical direction on the upper surface of the ceramic green sheet;
(6) firing the ceramic green sheet, and forming a ceramic substrate having a plurality of wiring substrates in which a wiring conductor and a seal metal layer are deposited on an insulating base made of a ceramic sintered body;
(7) The method includes a step of cutting the ceramic substrate along the first and second dividing grooves and dividing a plurality of wiring substrates individually.
[0013]
According to the method for manufacturing a wiring board of the present invention, after forming a through hole having a diameter of 0.1 mm to 0.25 mm in the center of each quadrangular region on the horizontal virtual line of the ceramic green sheet, the ceramic green sheet Since the first divided grooves are sequentially formed on the horizontal imaginary line on the upper surface of the ceramic green sheet and the second divided grooves are formed on the imaginary vertical line on the upper surface of the ceramic green sheet, the second divided grooves are formed. Even when the seal metal layers try to adhere to each other at the center of each side of each quadrangular region due to the narrowing of the width of the first dividing groove during the formation and firing shrinkage of the ceramic green sheet Adhesion is effectively prevented by the formation of a through hole in the center of each region of the first dividing groove. As a result, when dividing into each insulating substrate along the dividing groove, the adhesion can be performed with a small force. Made possible Together enables accurately divided at a predetermined position can be obtained accurately insulation substrate having a predetermined shape.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 shows an embodiment in which a wiring board formed by the manufacturing method of the present invention is applied to a package for housing a semiconductor element. In the figure, A is composed of an insulating substrate 1, a wiring conductor 2, and a seal metal layer 3. The wiring board 4 is a lid. The insulating substrate 1 and the lid 4 of the wiring board A constitute a container 6 for housing the semiconductor element 5.
[0015]
The insulating substrate 1 functions as a support member for supporting the semiconductor element 5 and has a semiconductor element mounting portion 1a at a substantially central portion on the upper surface. The semiconductor element 5 is made of glass, brazing material, resin, etc. It is attached and fixed via an adhesive.
[0016]
The wiring conductor 2 acts as a conductive path for connecting each electrode of the semiconductor element 5 to an external electric circuit. By connecting each electrode of the semiconductor element 5 to the wiring conductor 2 via the bonding wire 7, the semiconductor element 5 is connected. These electrodes are connected to an external electric circuit through the wiring conductor 2.
[0017]
Further, the seal metal layer 3 acts as a base metal layer for joining the lid body 4 via the brazing material, and the lid body 4 is positioned on the seal metal layer 3 via the brazing material such as gold-tin. At the same time, the cover 4 is bonded onto the seal metal layer 3 by heat treatment at a predetermined temperature, and the semiconductor element 5 is hermetically accommodated inside the container 6 composed of the insulating base 1 and the cover 4.
[0018]
The wiring board A is manufactured by cutting a ceramic substrate having a plurality of regions to be the wiring board A divided by the dividing grooves along the dividing grooves.
[0019]
Next, a method for manufacturing the wiring board A will be described with reference to FIGS. In the figure, the same parts as those in FIG.
[0020]
First, as shown in FIG. 2, the ceramic green sheet 11 is formed into a quadrangular shape by a horizontal imaginary line 12a and a vertical imaginary line 12b, and is partitioned into a plurality of regions 13 having a semiconductor element mounting portion 1a at the center. A wiring conductor 14 is formed around the mounting portion 1a of the rectangular region 13.
[0021]
For example, when the insulating base 1 is formed of an aluminum oxide sintered body, the ceramic green sheet 11 includes an organic binder suitable for raw material powders such as aluminum oxide, silicon oxide, calcium oxide, and magnesium oxide, and It is formed by adding a solvent to form a slurry, and forming it into a sheet using a conventionally known doctor blade method, calendar roll method, or the like.
[0022]
The wiring conductor 14 is made of a metal powder such as tungsten, molybdenum, manganese, copper, or silver. A metal paste obtained by adding an appropriate organic binder or solvent to the metal powder such as tungsten is mixed with the ceramic green sheet 11. Each of the rectangular regions 13 defined by the virtual lines is formed by printing and applying a predetermined pattern by a conventionally known screen printing method.
[0023]
Next, as shown in FIG. 3, a metal paste is printed and applied in a frame shape with a width of 0.3 to 0.6 mm on the outer peripheral edge of each square-shaped region 13 of the ceramic green sheet 11, and the sealing metal layer 15. Form.
[0024]
As with the metal paste forming the wiring conductor 14, the metal paste forming the metal layer 15 for sealing is mixed by adding an appropriate organic binder or solvent to metal powder such as tungsten, molybdenum, manganese, copper, or silver. It is produced by this.
[0025]
Next, as shown in FIG. 4, a through hole 16 is formed in the center of each region 13 on the horizontal virtual line 12 a of the ceramic green sheet 11.
[0026]
The through hole 16 has a function of forming a fixed gap at the center of each region 13 of the sealing metal layer 15 adjacent to the horizontal imaginary line 12a, and the gap is printed on the ceramic green sheet 11. The formed sealing metal layer 15 is prevented from adhering to each other adjacent to each other across the dividing groove when firing in a later step.
[0027]
The through hole 16 is formed, for example, by pressing a metal punching pin to a predetermined position on the imaginary line of the ceramic green sheet 11 and penetrating it in the thickness direction.
[0028]
Next, as shown in FIG. 5, the first divided grooves 17a are formed on the horizontal virtual lines 12a on the upper surface of the ceramic green sheet 11, and then the second divided grooves are formed on the vertical virtual lines 12b. 17b is formed.
[0029]
The first dividing groove 17a and the second dividing groove 17b are made of, for example, a metal blade having the same vertical cross-sectional shape as the predetermined cross-sectional shape of each of the dividing grooves, such as a V shape. It is formed by pressing.
[0030]
In this case, the first dividing groove 17a is deformed so as to be closed when a metal blade is pressed to form the second dividing groove 17b in the ceramic green sheet 11, and thereby the first dividing groove 17a is deformed. The width of the divided groove 17a is as narrow as about 70% to 90% with respect to the width of the second divided groove 17b.
[0031]
Next, the ceramic green sheet 11 is fired at a temperature of about 1600 ° C. in a reducing atmosphere, and as shown in FIG. 6, the wiring conductor 2 and the seal metal layer 3 are deposited on the insulating base 1 made of a ceramic sintered body. A ceramic substrate 18 having the plurality of wiring substrates A thus formed is formed. At the time of firing, each of the divided grooves 17a and 17b of the ceramic green sheet 11 has a slower start of sintering at the center of each square-shaped region 13 of the ceramic green sheet 11 than the end, and the shrinkage amount is small. Then, it shrinks so as to close at the center of each region 13. For this reason, the width of the dividing groove is very narrow, especially in the central portion of the first dividing groove 17a, coupled with the deformation at the time of forming the ceramic green sheet. However, a through hole 16 is formed in the central portion of the first dividing groove 17a, and the seal metal layers 3 adhere to each other at the central portion of each side of each of the wiring boards A having a quadrangular shape. The attempt is effectively prevented, and the adjacent seal metal layers 3 do not adhere to each other.
[0032]
Next, the ceramic substrate 18 is cut along the first and second dividing grooves 17a and 17b, and as shown in FIG. 7, the wiring conductor 2 and the seal metal layer are formed on the insulating base 1 having the mounting portion 1a at the center. A large number of wiring boards A formed with 3 are individually divided.
[0033]
The ceramic substrate 18 is cut by bending the ceramic substrate 18 by applying bending stress along the first and second divided grooves 17a and 17b sequentially.
[0034]
Further, when the ceramic substrate 18 is divided along the vertical and horizontal dividing grooves 17a, 17b, the adjacent seal metal layers 3 are prevented from adhering to each other by the through holes 16, so that the division can be performed with a small force. At the same time, the division can be accurately performed along the division grooves 17a and 17b, and the wiring board A having a predetermined shape can be obtained accurately.
[0035]
When the diameter of the through hole 16 is smaller than 0.1 mm, it is effective that the seal metal layers 3 adjacent to each other across the central portion of each region 13 of the first dividing groove 17a are adhered to each other. If the thickness is larger than 0.25 mm, the width of the seal metal layer 3 at the portion where the through hole 16 is formed becomes too narrow, and the bonding area between the lid 4 and the seal metal layer 3 is insufficient. Thus, the bonding strength of the lid 4 and the long-term reliability of the hermetic sealing are deteriorated. Therefore, the diameter of the through hole 16 is specified in the range of 0.1 mm to 0.25 mm.
[0036]
In the wiring board A thus obtained, the semiconductor element 5 is mounted on the upper surface of the insulating base 1, the electrodes of the semiconductor element 5 are electrically connected to the wiring conductor 2, and the lid 4 is placed on the sealing metal layer 3 with a brazing material or the like. The semiconductor element 5 is hermetically sealed inside the container 6 composed of the insulating base 1 and the lid body 4 to form a semiconductor device, and is mounted on an external electric circuit. The electrode of the semiconductor element 5 is electrically connected to an external electric circuit.
[0037]
The lid 4 is bonded to the seal metal layer 3 by, for example, positioning and abutting the lid 4 on the seal metal layer 3 via a gold-tin brazing material and heating and melting the brazing material to seal metal. It is carried out by wetting and spreading the surface where the layer 3 and the lid 4 are joined.
[0038]
Further, when the width of the seal metal layer 3 is less than 0.3 mm, the width of the seal metal layer 3 in the through hole 16 formation region becomes too narrow, and the lid 4 and the seal metal layer 3 are firmly bonded. In this case, the bonding strength of the lid and the long-term reliability of the hermetic sealing are deteriorated. If the thickness exceeds 0.6 mm, the wiring board A cannot be reduced in size and the sealing material is the sealing metal layer 3. Compared to the bonding area between the lid body 4 and the lid body 4, the lid body 4 flows too much and the joint strength of the lid body 4 becomes weak, and the joining position of the lid body 4 is likely to shift. Therefore, the width of the seal metal layer 3 is specified in the range of 0.3 mm to 0.6 mm.
[0039]
Further, the sealing metal layer 3 and the wiring conductor 2 of each wiring board A are covered with a plating layer (not shown) made of a metal such as nickel, copper, palladium, gold, tin or an alloy thereof (not shown) to a thickness of 2 μm to 20 μm. If attached, the oxidative corrosion of the seal metal layer 3 and the wiring conductor 2 is effectively prevented, and the bonding property of the bonding wire 7 and the strength of the welded joint of the lid 4 are improved. Therefore, the sealing metal layer 3 and the wiring conductor 2 of each wiring board A have a plating layer (not shown) made of a metal such as nickel, copper, palladium, gold, tin, or an alloy thereof on the surface thereof to a thickness of 2 μm to 20 μm. It is preferable to make it adhere.
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiments, the wiring board of the present invention is replaced with a semiconductor element. Although the example applied to the storage package has been described, this may be applied to a wiring board on which an electronic component such as a surface acoustic wave element is mounted.
[0040]
【The invention's effect】
According to the method for manufacturing a wiring board of the present invention, after forming a through hole having a diameter of 0.1 mm to 0.25 mm in the center of each quadrangular region on the horizontal virtual line of the ceramic green sheet, the ceramic green sheet Since the first divided grooves are sequentially formed on the horizontal imaginary line on the upper surface of the ceramic green sheet and the second divided grooves are formed on the imaginary vertical line on the upper surface of the ceramic green sheet, the second divided grooves are formed. Even when the seal metal layers try to adhere to each other at the center of each side of each quadrangular region due to the narrowing of the width of the first dividing groove during the formation and firing shrinkage of the ceramic green sheet Adhesion is effectively prevented by the formation of a through hole in the center of each region of the first dividing groove. As a result, when dividing into each insulating substrate along the dividing groove, the adhesion can be performed with a small force. Made possible Together enables accurately divided at a predetermined position can be obtained accurately insulation substrate having a predetermined shape.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment when a wiring board of the present invention is applied to a package for housing a semiconductor element.
2 is a plan view for each step for explaining a method of manufacturing a wiring board used in the package for housing a semiconductor element shown in FIG. 1; FIG.
3 is a plan view for each step for explaining a method of manufacturing a wiring board used in the package for housing a semiconductor element shown in FIG. 1. FIG.
4 is a plan view for each step for explaining a method of manufacturing a wiring board used in the package for housing a semiconductor element shown in FIG. 1; FIG.
5 is a plan view for each step for explaining a method of manufacturing a wiring board used in the package for housing a semiconductor element shown in FIG. 1; FIG.
6 is a plan view for each step for explaining a method of manufacturing a wiring board used in the package for housing a semiconductor element shown in FIG. 1. FIG.
7 is a plan view for each step for explaining a method of manufacturing a wiring board used in the package for housing a semiconductor element shown in FIG. 1; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Insulating base | substrate 1a ... Mounting part 2 ... Wiring conductor 3 ... Seal metal layer A ... Wiring board 4 ... Lid 5 ... Semiconductor element 6 ··· Container 7 ··· Bonding wire 11 · · · Ceramic green sheet 12a · · · horizontal virtual line 12b · · · vertical virtual line 13 · · · region 14 · · · conductor 15 for wiring · · · · Metal layer 16 for sealing ··· Through hole 17a · · First divided groove 17b · · Second divided groove 18 · · · Ceramic substrate

Claims (1)

（１）セラミックグリーンシートを縦方向及び横方向の仮想線によって四角形状をなす複数の領域に区画するとともに各領域に配線用導体を形成する工程と、
（２）前記セラミックグリーンシートの各領域の外周縁に、金属ペーストを０．３〜０．６ｍｍの幅で枠状に印刷塗布し、シール用金属層を形成する工程と、
（３）前記セラミックグリーンシートの横方向の仮想線上で各領域の中央部に直径０．１ｍｍ〜０．２５ｍｍの貫通孔を形成する工程と、
（４）前記セラミックグリーンシートの上面で横方向の仮想線上に第１の分割溝を形成する工程と、
（５）前記セラミックグリーンシートの上面で縦方向の仮想線上に第２の分割溝を形成する工程と、
（６）前記セラミックグリーンシートを焼成し、セラミック焼結体から成る絶縁基体に配線導体及びシール金属層を被着させた複数個の配線基板を有するセラミック基板を形成する工程と、
（７）前記セラミック基板を第１及び第２の分割溝に沿って切断し、多数の配線基板を個々に分割する工程
とから成る配線基板の製造方法。(1) a step of partitioning the ceramic green sheet into a plurality of rectangular regions by vertical and horizontal virtual lines and forming a wiring conductor in each region;
(2) A step of printing and applying a metal paste in a frame shape with a width of 0.3 to 0.6 mm on the outer peripheral edge of each region of the ceramic green sheet to form a metal layer for sealing;
(3) forming a through hole having a diameter of 0.1 mm to 0.25 mm in the center of each region on the horizontal imaginary line of the ceramic green sheet;
(4) forming a first divided groove on a horizontal imaginary line on the upper surface of the ceramic green sheet;
(5) forming a second divided groove on the imaginary line in the vertical direction on the upper surface of the ceramic green sheet;
(6) firing the ceramic green sheet and forming a ceramic substrate having a plurality of wiring substrates in which a wiring conductor and a seal metal layer are attached to an insulating base made of a ceramic sintered body;
(7) A method of manufacturing a wiring board, comprising: cutting the ceramic substrate along first and second dividing grooves, and dividing a large number of wiring boards individually.
JP2000330132A 2000-10-30 2000-10-30 Wiring board manufacturing method Expired - Fee Related JP4355097B2 (en)

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JP2009010103A (en) * 2007-06-27 2009-01-15 Ngk Spark Plug Co Ltd Multiple patterning ceramic substrate
US9045332B2 (en) * 2011-11-29 2015-06-02 Qualcomm Mems Technologies, Inc. Thin back glass interconnect

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