JPS5871644A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5871644A JPS5871644A JP16975781A JP16975781A JPS5871644A JP S5871644 A JPS5871644 A JP S5871644A JP 16975781 A JP16975781 A JP 16975781A JP 16975781 A JP16975781 A JP 16975781A JP S5871644 A JPS5871644 A JP S5871644A
- Authority
- JP
- Japan
- Prior art keywords
- package
- conductive
- conductive frame
- internal wiring
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の構造に係り0%にプラグ・イ/・
タイプのパッケージに封入されてなる半導体装置の外部
構造に関する。[Detailed Description of the Invention] The present invention relates to the structure of a semiconductor device and has a plug-in/
This invention relates to the external structure of a semiconductor device enclosed in a type of package.
高集積度の半導体集積回路(IC)に於ては。In highly integrated semiconductor integrated circuits (ICs).
内部配線が多層に形成され、且つ底面に多数の接続ビン
が単数又は複数列にわたって配設されてなるプラグ・イ
ン・タイプのセラミック・パッケージが用いられる。皺
パッケージの内部配線のボンディング拳パッド部、内部
配線と電気的に導通している電極ピン、チップ・ステー
ジ等に金(Au)等の電気メッキを施す際、た・・とえ
ばデュアル・イン・ライン・タイプのセラミック・パッ
ケージであれば複数の外部リードを連結させたリードフ
レームが各内部配線と電気的に導通されているため。A plug-in type ceramic package is used in which internal wiring is formed in multiple layers and a number of connection vias are arranged in one or more rows on the bottom surface. When electroplating gold (Au) etc. on the bonding pad of the internal wiring of the wrinkled package, the electrode pins electrically connected to the internal wiring, the chip stage, etc., for example, dual in. In the case of a line-type ceramic package, the lead frame that connects multiple external leads is electrically connected to each internal wiring.
該リードフレームをめっき用電極として電位を付与する
ことにより容易にメッキを施すことができるのに対し1
本プラグ・インeタイプのパッケージの場合はそれぞれ
の内部配線が独立しているため、全ての内部配線をメッ
キ用電極として電位を付与しなければならず被メツキ部
に電気メッキを施すことは極めて困難である。そこでプ
ラグ・イン・タイプのパッケージに於ては多層に形成さ
れている内部配−〇端面をパッケージの側面に表出させ
て置き、該側面上に各内部配線の端面と電気的に導通さ
れた一連のメッキ用電極を形成しておいて、該電極から
パッケージ上に露出している被メツキ部に電位を付与し
てメッキがなされる。そしてメッキが終った後にパッケ
ージの側面から前記メッキ用電極を削り落として、内部
配線を個々に分離するという手段が用いられる。従って
このようなプラグ・イン・タイプのパッケージに於ては
、その側面に内部配線の端面が表出した構造にならざる
を得ない。そのため該構造のパッケージを用いて形成し
た半導体装置に於ては、該半導体装置を取シ扱う際にパ
ッケージ側面に触れる指先等から内部配線に電位が負荷
されて、半導体素子が静電気破壊を起こすことがままあ
る。Plating can be easily performed by applying a potential to the lead frame as a plating electrode.
In the case of this plug-in e type package, each internal wiring is independent, so it is necessary to apply a potential to all internal wiring as plating electrodes, and it is extremely difficult to apply electroplating to the part to be plated. Have difficulty. Therefore, in a plug-in type package, the end face of the internal wiring formed in multiple layers is exposed on the side of the package, and electrically connected to the end face of each internal wiring is placed on the side face. A series of plating electrodes are formed, and a potential is applied from the electrodes to the part to be plated exposed on the package to perform plating. After plating is completed, the plating electrode is scraped off from the side surface of the package to separate the internal wirings individually. Therefore, in such a plug-in type package, the end face of the internal wiring is exposed on the side surface. Therefore, in a semiconductor device formed using a package with this structure, when handling the semiconductor device, a potential is applied to the internal wiring from a fingertip or the like that touches the side of the package, causing electrostatic damage to the semiconductor element. There is still time.
本発明は上記プラグ・インeタイプのパッケージによっ
て形成された半導体装置に於ける。半導体素子の静電気
破壊を防止する構造を提供するものである。The present invention relates to a semiconductor device formed by the above-mentioned plug-in e type package. The present invention provides a structure that prevents electrostatic damage to semiconductor elements.
即ち本発明は、11面に内部配線の端面が表出したセラ
ミック・パッケージに半導体素子が搭載されてなる半導
体装置に於て、前記セラミック;パッケージの側面を覆
う導電枠を着脱自在に嵌着して表ることを特徴とする。That is, the present invention provides a semiconductor device in which a semiconductor element is mounted on a ceramic package in which the end face of internal wiring is exposed on the 11th side. It is characterized by being expressed as follows.
以下本発明の実施例について9図を用いて評細に説明す
る。第1図はセラミック・パッケージの側面模式図、第
2図、第3図、第4図はそれぞれ異なる一実施例に於け
る斜視図(a)及び要部断面図(b)である。Embodiments of the present invention will be described in detail below using FIG. 9. FIG. 1 is a schematic side view of a ceramic package, and FIGS. 2, 3, and 4 are a perspective view (a) and a sectional view (b) of a main part of different embodiments, respectively.
本発明の半導体装置を構成するプラグ・イン・タイプの
セラミック・パッケージの構造を概念的に示したのが第
1図の側面模式図で1図に於て。The structure of the plug-in type ceramic package constituting the semiconductor device of the present invention is conceptually shown in FIG. 1, which is a schematic side view.
1は積層セラミック基板(パッケージ基体)、2は内部
配線、3はスルーホール、4は電極ピンを表わしている
。即ち該パッケージに於ては1図に示すように各層の内
部配線2の端面はパッケージの基体である積層セラミッ
ク基板1の側面に表出している。そして積層セラミック
基板1の下面に配設されている電極ビン4は9それぞれ
スルーホール3を介して内部配m2に電気的に接続され
ている。又図示されていないが、内部配線の一部で6
b ホ:y ティング・パッド領域及び特定の内部配線
に接続するチップ・ステージは、積層セラミック基板1
上に表出している。そして積層セラミック基板1面に施
される内部配線、スルーホール内の導電膜等は1通常タ
ングステン(W)、モリブデン(Mo)等のメタ2イズ
層で形成されておシ、基板から表出した領域即ち、ボン
ディング・パッド部(図示せず)、チップ・ステージ(
図示せず)及び前記電極ピン4上にはAuメッキが施さ
れている。 ゛
本発明を適用しようとする半導体装置は、上記のような
セラミック・パッケージのチップ・ステージ上に半導体
IC等のチップをろう付けし、該半導体チップの配線パ
ッドと前記内部配線のボンディング・パッドとの間をワ
イヤ・ボンディングで接続して形成する。従って前述し
たような素子の静電気破壊が生ずるわけである。1 represents a laminated ceramic substrate (package base), 2 represents internal wiring, 3 represents a through hole, and 4 represents an electrode pin. That is, in this package, as shown in FIG. 1, the end faces of the internal wiring 2 of each layer are exposed on the side surface of the laminated ceramic substrate 1, which is the base of the package. Nine electrode bins 4 disposed on the lower surface of the laminated ceramic substrate 1 are electrically connected to the internal wiring m2 via through holes 3, respectively. Also, although not shown, some of the internal wiring
b E: y The chip stage connected to the contact pad area and specific internal wiring is the multilayer ceramic substrate 1
It is exposed above. Internal wiring, conductive films in through holes, etc. applied to one side of the laminated ceramic substrate are usually formed of a metal layer such as tungsten (W) or molybdenum (Mo), and are exposed from the substrate. bonding pad area (not shown), chip stage (
(not shown) and the electrode pin 4 are plated with Au.゛In a semiconductor device to which the present invention is applied, a chip such as a semiconductor IC is brazed on a chip stage of a ceramic package as described above, and wiring pads of the semiconductor chip and bonding pads of the internal wiring are connected to each other. These are formed by connecting them with wire bonding. Therefore, the electrostatic breakdown of the device as described above occurs.
第2図(&)及び(b)は上記プラグ・イン・タイプの
セラミック・パッケージによって構成される半導体装置
に本発明を適用した一実施例に於ける斜視図及び要部断
面図である。即ち該実施例に於てはセラミック・パッケ
ージ11上に、その縁部上面及び側面を覆う箱形の導電
枠12が着脱自在に嵌着されている。そして該導電枠は
銀(Al)、銅(Cu)。FIGS. 2(&) and 2(b) are a perspective view and a sectional view of a main part of an embodiment in which the present invention is applied to a semiconductor device constituted by the above-mentioned plug-in type ceramic package. That is, in this embodiment, a box-shaped conductive frame 12 is removably fitted onto the ceramic package 11 to cover the top and side surfaces of the edges. The conductive frame is made of silver (Al) and copper (Cu).
炭素Cなどの金属粒子あるいは導電性物質粒子を例えば
シリコン樹脂に混入させて得られる導電性ゴム等の導電
性を有し、かつ伸縮性を有する。弾性材料によって形成
され、圧入等の方法によりセラミック・パッケージII
K着脱自在に嵌着される。又その厚さは0.5〜1〔■
〕程度あれば充分である、〕こうすることにより内部配
線は短絡され全て同電位に保たれる。なお図に於て13
はキャップ、14はシール用メタライズ会パターン、1
5は電極ビン、16は内部配線、17はICチップ。It has conductivity and elasticity, such as a conductive rubber obtained by mixing metal particles such as carbon C or conductive substance particles into silicone resin, for example. Ceramic package II is formed of an elastic material and is formed by a method such as press-fitting.
K is removably fitted. Also, its thickness is 0.5 to 1 [■
] is sufficient. By doing this, the internal wiring is short-circuited and all are kept at the same potential. In addition, in the figure 13
is the cap, 14 is the metallized pattern for the seal, 1
5 is an electrode bin, 16 is an internal wiring, and 17 is an IC chip.
18はボンディング・ワイヤ、19はスルーホールを示
す。18 is a bonding wire, and 19 is a through hole.
第3図(a)及び(b)は9本発明の他の一実施例に於
ける斜視図及び要部断面図である。即ち該実施例に於て
はセラミックーパッケージ11の側面のみが、該側面上
に着脱自在に嵌着された導電性を有しかつ伸縮性を有す
るゴム材料等からなる0、5〜1(in)程度の厚さの
導電枠22によって覆われてなっている。なお図に於て
他の記号は第2図<a)及び(b)と同一部位を示して
いる。FIGS. 3(a) and 3(b) are a perspective view and a sectional view of essential parts in another embodiment of the present invention. That is, in this embodiment, only the side surface of the ceramic package 11 is made of conductive and stretchable rubber material, etc., which is removably fitted onto the side surface. ) and is covered with a conductive frame 22 having a thickness of about 100 mm. In addition, other symbols in the figures indicate the same parts as in FIGS. 2<a) and (b).
第4図(a)及び(b)は9本発明の上記以外の一実施
例に於ける斜視図及び要部断面図である。即ち該実施例
に於ては、セラミック拳パッケージ11の側面に、導電
性を有し、且つ伸縮性を有する0、5〔菖鳳〕程度の厚
さのゴム材料で形成され、内側に向って屈折したつばを
持つ導電枠32が着脱自在に嵌着されてなっている。な
お同図に於て、他の記号は第2図(a)及び(b)と同
一部位を示している。FIGS. 4(a) and 4(b) are a perspective view and a sectional view of a main part of an embodiment of the present invention other than the above. That is, in this embodiment, the side surface of the ceramic fist package 11 is made of a conductive and stretchable rubber material with a thickness of about 0.5 [Iris], and the side surface of the ceramic fist package 11 is made of a rubber material having a thickness of about 0.5 [Iris]. A conductive frame 32 with a bent brim is detachably fitted. In this figure, other symbols indicate the same parts as in FIGS. 2(a) and 2(b).
以上実施例によって説明したように1本発明のプラグ・
イン−タイプのセラミック・パッケージを用いた半導体
装置に於ては、前記パッケージの側面に表出している内
部配線16の端面が導電性を有しかつ伸縮性を有する0
、5〜1(龍〕程度の厚さの導電枠12.22..32
%によって着脱自在に覆われており半導体装置を実装す
る前は半導体装置に嵌着して静電気破壊を防止し、半導
体装置の性能試験時、実装時等には容易に取りはずすこ
とができる。なお実施例に於ては導電性および伸縮性を
有する弾性材料を用いた場合について説明したが銅(C
u)、はんだなどの導電性の良好な金属を用いて第2図
に示す導電枠22の如き導電枠を形成しても本発明の目
的を達成することができる。なお絶縁枠を用いて内面に
導電膜などの導電体物質を被着してもよい。As explained above with reference to the embodiments, one plug of the present invention
In a semiconductor device using an in-type ceramic package, the end surface of the internal wiring 16 exposed on the side surface of the package is conductive and elastic.
, conductive frame 12.22..32 with a thickness of about 5 to 1 (dragon)
%, and is fitted onto the semiconductor device to prevent electrostatic damage before the semiconductor device is mounted, and can be easily removed during performance testing or mounting of the semiconductor device. In the examples, the case where an elastic material having conductivity and stretchability was used was explained, but copper (C
u) The object of the present invention can also be achieved by forming a conductive frame such as the conductive frame 22 shown in FIG. 2 using a metal with good conductivity such as solder. Note that a conductive material such as a conductive film may be applied to the inner surface of the insulating frame.
このように本発明によれば該半導体装置を取扱う際に指
示等の電位を有する物体がパッケージの側面に触れても
導電枠が嵌着され全ての配線を短絡しているため、全て
の配線が同時チャージアップされる。従って半導体素子
の例えばゲート電極とドレイ/電極間等局部的に電位が
負荷されることがなくなるのでパッケージに封入した半
導体素子の静電気破壊を完全に防止することができる。As described above, according to the present invention, even if an object having a potential such as an instruction touches the side of the package when handling the semiconductor device, the conductive frame is fitted and all the wiring is short-circuited, so that all the wiring is Charged up at the same time. Therefore, since no potential is applied locally, such as between the gate electrode and the drain/electrode of the semiconductor element, electrostatic damage to the semiconductor element sealed in the package can be completely prevented.
第1図1プラグ・イン・タイプのセラミック・パッケー
ジの側面模式図で、第2図及至第4図は本発明の異なる
一実施例における斜視図(a)及び要部断面図(b)で
ある。
図に於て、1は積層セランツク基板(パッケージ基体)
、2.16は内部配線、3.19はスルーホール、4.
15はtWピ/、11はセラミック・パッケージ、12
,22.32は導電枠、13はキャップ、14はシール
用メタライズ・パターン、17はICチップ、18はボ
ンディング拳ワイヤを示ζ
第1図
(
第2図
199
砧3図
3FIG. 1 is a schematic side view of a plug-in type ceramic package, and FIGS. 2 to 4 are a perspective view (a) and a sectional view (b) of a main part of a different embodiment of the present invention. . In the figure, 1 is a laminated ceramic board (package base)
, 2.16 is internal wiring, 3.19 is through hole, 4.
15 is tW pi/, 11 is ceramic package, 12
, 22. 32 is a conductive frame, 13 is a cap, 14 is a metallized pattern for sealing, 17 is an IC chip, and 18 is a bonding wire.
Claims (1)
ジに半導体素子が搭載されてなる半導体装置に於て、前
記セラミック・パッケージの側面を覆う導電枠を着脱自
在に嵌着してなることを特徴とする半導体装置。A semiconductor device in which a semiconductor element is mounted on a ceramic package with an end face of internal wiring exposed on the side surface, characterized in that a conductive frame covering the side surface of the ceramic package is removably fitted. semiconductor devices.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16975781A JPS5871644A (en) | 1981-10-23 | 1981-10-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16975781A JPS5871644A (en) | 1981-10-23 | 1981-10-23 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5871644A true JPS5871644A (en) | 1983-04-28 |
JPS6237888B2 JPS6237888B2 (en) | 1987-08-14 |
Family
ID=15892279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16975781A Granted JPS5871644A (en) | 1981-10-23 | 1981-10-23 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5871644A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4696526A (en) * | 1985-07-26 | 1987-09-29 | Intel Corporation | Carrier for tape automated bonded semiconductor device |
EP2149901A1 (en) * | 2008-08-01 | 2010-02-03 | STMicroelectronics Ltd (Malta) | Method for manufacturing an electronic device protected against electro static discharge |
-
1981
- 1981-10-23 JP JP16975781A patent/JPS5871644A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4696526A (en) * | 1985-07-26 | 1987-09-29 | Intel Corporation | Carrier for tape automated bonded semiconductor device |
EP2149901A1 (en) * | 2008-08-01 | 2010-02-03 | STMicroelectronics Ltd (Malta) | Method for manufacturing an electronic device protected against electro static discharge |
US8742562B2 (en) | 2008-08-01 | 2014-06-03 | Stmicroelectronics (Malta) Ltd | Electronic device protected against electro static discharge |
Also Published As
Publication number | Publication date |
---|---|
JPS6237888B2 (en) | 1987-08-14 |
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