JPS634710B2 - - Google Patents
Info
- Publication number
- JPS634710B2 JPS634710B2 JP15016781A JP15016781A JPS634710B2 JP S634710 B2 JPS634710 B2 JP S634710B2 JP 15016781 A JP15016781 A JP 15016781A JP 15016781 A JP15016781 A JP 15016781A JP S634710 B2 JPS634710 B2 JP S634710B2
- Authority
- JP
- Japan
- Prior art keywords
- package
- conductor layer
- pattern
- plating
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 27
- 238000007747 plating Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000919 ceramic Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 10
- 238000009713 electroplating Methods 0.000 claims description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 230000007794 irritation Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置のパツケージの改良に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in packages for semiconductor devices.
半導体チツプを搭載するパツケージとして所定
パターンの金属の導体層をメタライズしたセラミ
ツク基板を積層して形成したパツケージは周知で
ある。 2. Description of the Related Art As a package for mounting a semiconductor chip, a package formed by laminating ceramic substrates each having a metalized conductor layer in a predetermined pattern is well known.
このようなパツケージの従来の構造の平面図を
第１図にその断面図を第２図に示す。 A plan view of a conventional structure of such a package is shown in FIG. 1, and a sectional view thereof is shown in FIG.
図示するようにセラミツクパツケージのステー
ジ１上において金―シリコン（Au―Si）層を介
して半導体チツプ２が融着されている。一方該チ
ツプとタングステン（Ｗ）のような導体層に金
（Au）またはニツケル（Ni）がメツキされたイ
ンナーリード線３とが金線等のワイヤー４によつ
てボンデイングされており、またインナーリード
線３と外部リード線５とはセラミツク基板にタン
グステン（Ｗ）、またはモリブデン（Mo）をメ
タライズして形成されている導体層６によつて接
続されている。一方該セラミツク基板上にはタン
グステン（Ｗ）またはモリブデン（Mo）等によ
りシールパターン７がメタライズされており後の
工程で該パツケージ上にセラミツク等のキヤツプ
８をかぶせてパツケージをシールする際に用いら
れる。 As shown in the figure, a semiconductor chip 2 is fused onto a stage 1 of a ceramic package via a gold-silicon (Au--Si) layer. On the other hand, the chip and an inner lead wire 3 in which a conductor layer such as tungsten (W) is plated with gold (Au) or nickel (Ni) are bonded by a wire 4 such as a gold wire. The wire 3 and the external lead wire 5 are connected by a conductor layer 6 formed by metallizing tungsten (W) or molybdenum (Mo) on a ceramic substrate. On the other hand, a seal pattern 7 is metalized with tungsten (W) or molybdenum (Mo) on the ceramic substrate, and is used in a later process when a cap 8 of ceramic or the like is placed over the package to seal the package. .
ところで前述したメタライズにより作る外部リ
ード線はコバール等の鉄―ニツケル合金で形成さ
れており、これらは錆びやすく電気抵抗が大きい
のであらかじめ、AuまたはNi等の金属メツキを
施しておくことが必要でありまたインナーリード
およびシールパターンもこの必要がありこのよう
な金属メツキを電気メツキで実施するために前記
メツキを実施しようとしているインナーリード
線、外部リード線等に接続している導体層に電気
メツキを施すための電圧を印加する必要がある。 By the way, the external lead wires made by metallization mentioned above are made of iron-nickel alloys such as Kovar, and as these are prone to rust and have high electrical resistance, it is necessary to plate them with metals such as Au or Ni in advance. This is also necessary for the inner lead and seal pattern, and in order to perform such metal plating by electroplating, it is necessary to electroplat the conductor layer connected to the inner lead wire, external lead wire, etc. to which the plating is to be performed. It is necessary to apply a voltage for this purpose.
そこで一般にこのような電気メツキを施すため
の電圧を印加する手段として前記導体層６をセラ
ミツクパツケージの４側面に導出させ、該各側面
にメツキ用パターン９を形成していた。 Therefore, as a means for applying a voltage for performing such electroplating, the conductor layer 6 is generally led out to four sides of the ceramic package, and a plating pattern 9 is formed on each side.
ところで電気メツキを終了した後には前記側面
のメツキ用パターンの金属層は研磨して除去する
がパツケージの四方の側面から導体層の端部が露
出しており、そのためこのようなパツケージに収
められた半導体装置を他の電子機械に実装する際
該パツケージの側面を治具で挾んで実装すること
が多く、この治具で挾む際に静電気が発生し該静
電気が導体層６を介して半導体チツプ中に流れ込
み、半導体装置を劣化させるといつた不都合を生
じていた。また導体層６の端部は側面に導出さ
れ、メツキ用パターン９は側面に形成されていた
ため、信号用のパターン形成とは、全く別の工程
が必要であり、形成工程は複雑なものであつた。 By the way, after electroplating is completed, the metal layer of the plating pattern on the side surface is removed by polishing, but the ends of the conductor layer are exposed from all four sides of the package. When a semiconductor device is mounted on another electronic machine, the sides of the package are often clamped with a jig. Static electricity is generated when the package is clamped with a jig, and the static electricity is transferred to the semiconductor chip via the conductor layer 6. This caused inconveniences such as flowing into the semiconductor device and deteriorating the semiconductor device. In addition, since the end of the conductor layer 6 was led out to the side surface and the plating pattern 9 was formed on the side surface, a completely different process was required from the signal pattern formation, and the formation process was complicated. Ta.
本発明は上述した欠点を除去するような半導体
装置のパツケージを提供することを目的とするも
のである。 The object of the present invention is to provide a package for a semiconductor device which eliminates the above-mentioned drawbacks.
かかる目的を達成するための半導体装置のパツ
ケージはセラミツク基板上に所定パターンの導体
層を形成し、該導体層を形成するセラミツク基板
を積層して形成してなる半導体装置のパツケージ
において、前記導体層の端部をパツケージの底部
背面に集め該導体層を電気メツキする際に用いる
メツキ用金属パターンを該パツケージの底部背面
に設け前記導体層と接続したことを特徴とするも
のである。 A semiconductor device package for achieving this purpose is formed by forming a conductor layer in a predetermined pattern on a ceramic substrate, and laminating the ceramic substrates forming the conductor layer. The present invention is characterized in that a plating metal pattern is provided on the bottom back surface of the package and is connected to the conductive layer.
以下図面を用いて本発明の一実施例につき詳細
に説明する。 An embodiment of the present invention will be described in detail below with reference to the drawings.
第３図は本発明に関る半導体装置のパツケージ
の背面側より見た平面図で第４図はそのＡ―
A′線に沿つた断面図である。 FIG. 3 is a plan view of the package of the semiconductor device according to the present invention, seen from the back side, and FIG.
FIG. 3 is a sectional view taken along line A'.
図はプラグインライン型パツケージに例を用い
たもので、第３図および第４図に示すようにセラ
ミツクパツケージの底部背面側に導体層およびリ
ード線等に電気メツキをするための電圧を印加す
るためのＷ又はMo金属をメタライズして形成し
たメツキ用金属パターン１１が設けられている。 The figure uses an example of a plug-in line type package, and as shown in Figures 3 and 4, the voltage for electroplating the conductor layer and lead wires, etc. is applied to the bottom rear side of the ceramic package. A plating metal pattern 11 formed by metallizing W or Mo metal is provided.
このような金属パターンを形成する方法は他の
導体層と同様の手法でよい。 The method for forming such a metal pattern may be the same as that for other conductor layers.
一方セラミツク基板にはインナーリード線３よ
り延びる導体層１２および、外部リード線５より
延びる導体層１３、およびシールパターン７より
延びる導体層１４、およびステージ１上の金属層
より延びる導体層１５がそれぞれセラミツク基板
上にMoまたはＷをメタライズすることで形成さ
れそれらの導体層の端部がすべてメツキ用金属パ
ターンに接続されている。 On the other hand, the ceramic substrate has a conductor layer 12 extending from the inner lead wire 3, a conductor layer 13 extending from the outer lead wire 5, a conductor layer 14 extending from the seal pattern 7, and a conductor layer 15 extending from the metal layer on the stage 1, respectively. It is formed by metallizing Mo or W on a ceramic substrate, and the ends of these conductor layers are all connected to a metal pattern for plating.
このようにして形成されたメツキ用金属パター
ンから導線を取り出した後、この導線を電気メツ
キ用の電極に接続し、該メツキ用金属パターンが
形成されたセラミツクパツケージをAuまたはNi
の電気メツキ用液中に浸積させ該金属パターンを
介してそれぞれの導体層に電圧を印加してリード
線、シール用パターン等をAuまたはNiメツキす
る。 After taking out the conductive wire from the metal pattern for plating formed in this way, this conductor is connected to an electrode for electroplating, and the ceramic package on which the metal pattern for plating is formed is made of Au or Ni.
The lead wires, sealing patterns, etc. are plated with Au or Ni by immersing them in an electroplating liquid and applying a voltage to each conductor layer through the metal pattern.
その後メツキ用金属パターン１１をアルミナ
（Al2O3）等の研磨剤で除去する。 Thereafter, the plating metal pattern 11 is removed using an abrasive such as alumina (Al 2 O 3 ).
このようにすればシール用パターン、リード線
等から延び、セラミツク基板上にメタライズして
形成されている導体層の端部がすべてセラミツク
パツケージの底部の背面に延びてそこでメツキ用
金属パターン１１と接続されているので、該パツ
ケージに塔載されている半導体装置を電子機械に
実装する際、パツケージの側面を治具で挾んで生
じた静電気が導体層を通じて半導体チツプに流れ
る現象がなくなり半導体装置が劣化するといつた
現象が除去できる利点を生じる。 In this way, the ends of the conductor layer extending from the sealing pattern, lead wires, etc. and formed by metallization on the ceramic substrate will all extend to the back side of the bottom of the ceramic package, and will be connected there to the metal pattern 11 for plating. Therefore, when the semiconductor device mounted on the package is mounted on an electronic machine, the static electricity generated when the sides of the package are clamped with a jig does not flow to the semiconductor chip through the conductor layer, and the semiconductor device deteriorates. This gives rise to the advantage that the phenomenon of irritation can be eliminated.
またメツキ用パターンはリード線に接続される
信号用パターンと同一面に１箇所形成すれば良
く、信号用パターンと同時に形成可能である。更
にメツキ用パターンの除去も１回で終了すること
ができ、４側面のメツキ用パターンをそれぞれ除
去していた従来に比べその工程はきわめて容易な
ものとなる。 Further, the plating pattern may be formed at one location on the same surface as the signal pattern connected to the lead wire, and can be formed at the same time as the signal pattern. Furthermore, the removal of the plating pattern can be completed in one step, making the process much easier than in the past, in which the plating patterns on each of the four sides were removed.
以上はプラグイン型のパツケージに例を用いて
述べたが、その他デユアルインライン型のセラミ
ツクパツケージにも適用できることは勿論であ
る。またメツキ用金属パターンの形状は方形でも
勿論差し支えない。 Although the above has been described using an example of a plug-in type package, it is of course applicable to other dual-in-line type ceramic packages as well. Moreover, the shape of the metal pattern for plating may of course be rectangular.
第１図および第２図は従来の半導体装置のパツ
ケージを示す平面図およびその断面図で第３図お
よび第４図は本発明の半導体装置のパツケージの
一実施例を示す平面図およびその断面図である。
図において１はステージ、２は半導体チツプ、
３はインナーリード線、４はワイヤー、５は外部
リード線、６，１２，１３，１４，１５は導体
層、７はシールパターン、８はキヤツプ、９，１
１はメツキ用金属パターンを示す。
1 and 2 are a plan view and a sectional view of a conventional semiconductor device package, and FIGS. 3 and 4 are a plan view and a sectional view of an embodiment of the semiconductor device package of the present invention. It is. In the figure, 1 is a stage, 2 is a semiconductor chip,
3 is an inner lead wire, 4 is a wire, 5 is an external lead wire, 6, 12, 13, 14, 15 is a conductor layer, 7 is a seal pattern, 8 is a cap, 9, 1
1 shows a metal pattern for plating.
Claims (1)
形成し、該導体層を形成したセラミツク基板を積
層して形成してなる半導体装置のパツケージにお
いて、前記導体層の端部をパツケージの底部背面
に集め該導体層を電気メツキする際に用いるメツ
キ用金属パターンを該パツケージの底部背面に設
け前記導体層と接続したことを特徴とする半導体
装置のパツケージ。1. In a semiconductor device package formed by forming a conductor layer in a predetermined pattern on a ceramic substrate and stacking the ceramic substrates on which the conductor layer is formed, the ends of the conductor layer are gathered at the bottom rear surface of the package. 1. A package for a semiconductor device, characterized in that a metal pattern for plating used when electroplating a conductor layer is provided on the bottom rear surface of the package and connected to the conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15016781A JPS5851544A (en) | 1981-09-22 | 1981-09-22 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15016781A JPS5851544A (en) | 1981-09-22 | 1981-09-22 | Package for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5851544A JPS5851544A (en) | 1983-03-26 |
| JPS634710B2 true JPS634710B2 (en) | 1988-01-30 |
Family
ID=15490963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15016781A Granted JPS5851544A (en) | 1981-09-22 | 1981-09-22 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5851544A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6112921A (en) * | 1984-06-26 | 1986-01-21 | Toyobo Co Ltd | Method of water repellent processing of synthetic yarn |
| JPS6177345A (en) * | 1984-09-21 | 1986-04-19 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS62214648A (en) * | 1986-03-15 | 1987-09-21 | Ngk Insulators Ltd | Manufacture of package for semiconductor element |
| US5507989A (en) * | 1992-04-01 | 1996-04-16 | Teijin Limited | High speed process for producing polyester filaments |
-
1981
- 1981-09-22 JP JP15016781A patent/JPS5851544A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5851544A (en) | 1983-03-26 |
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