JPH0394431A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0394431A
JPH0394431A JP1231134A JP23113489A JPH0394431A JP H0394431 A JPH0394431 A JP H0394431A JP 1231134 A JP1231134 A JP 1231134A JP 23113489 A JP23113489 A JP 23113489A JP H0394431 A JPH0394431 A JP H0394431A
Authority
JP
Japan
Prior art keywords
semiconductor chip
circuit patterns
metal base
gold
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1231134A
Other languages
Japanese (ja)
Other versions
JP2781018B2 (en
Inventor
Katsuya Fukase
Masato Tanaka
Original Assignee
Shinko Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co Ltd filed Critical Shinko Electric Ind Co Ltd
Priority to JP1231134A priority Critical patent/JP2781018B2/en
Publication of JPH0394431A publication Critical patent/JPH0394431A/en
Application granted granted Critical
Publication of JP2781018B2 publication Critical patent/JP2781018B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PURPOSE: To easily manufacture products corresponding to uses of various products and to reduce the number of production processes by a method wherein a face on one side, on which a semiconductor chip has been mounted, of a metal base is resin-sealed collectively inclusive of the semiconductor chip, bonding wires and circuit patterns and only the metal base is etched and removed.
CONSTITUTION: A metal base 10 is plated with gold; required circuit patterns are formed of a gold-plated layer. A semiconductor chip 14 is bonded to a die bonding part 12; circuit patterns 13 and the semiconductor chip 14 are wire- bonded; the semiconductor chip 14, a circuit component 16, the circuit patterns 13 and the like are resin-sealed. Then, the metal base 10 is etched and removed as a whole. Consequently, the semiconductor chip 14, the circuit component 16 and the like are resin-sealed; parts of the gold-plated layer such as the die bonding part 12, the circuit patterns 13 and the like are exposed. Thereby, a production operation can be made easy and the number of production processes can be reduced.
COPYRIGHT: (C)1991,JPO&Japio
JP1231134A 1989-09-06 1989-09-06 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2781018B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1231134A JP2781018B2 (en) 1989-09-06 1989-09-06 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1231134A JP2781018B2 (en) 1989-09-06 1989-09-06 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0394431A true JPH0394431A (en) 1991-04-19
JP2781018B2 JP2781018B2 (en) 1998-07-30

Family

ID=16918815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1231134A Expired - Fee Related JP2781018B2 (en) 1989-09-06 1989-09-06 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2781018B2 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0974149A (en) * 1995-09-04 1997-03-18 Oki Electric Ind Co Ltd Small package and manufacture
WO1997039482A1 (en) * 1996-04-18 1997-10-23 Tessera, Inc. Methods for manufacturing a semiconductor package
JPH11121646A (en) * 1997-10-14 1999-04-30 Hitachi Cable Ltd Semiconductor package and manufacture thereof
JPH11195733A (en) * 1997-10-28 1999-07-21 Seiko Epson Corp Semiconductor device and manufacture thereof, and conductive board thereof
US6033933A (en) * 1997-02-14 2000-03-07 Lg Semicon Co., Ltd Method for attaching a removable tape to encapsulate a semiconductor package
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
US6528879B2 (en) 2000-09-20 2003-03-04 Sanyo Electric Co., Ltd. Semiconductor device and semiconductor module
US6583444B2 (en) 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
US7165316B2 (en) 1996-04-18 2007-01-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US7173336B2 (en) 2000-01-31 2007-02-06 Sanyo Electric Co., Ltd. Hybrid integrated circuit device
JP2008215498A (en) * 2007-03-05 2008-09-18 Nsk Warner Kk Wet multi-disc frictional engaging device
JP2014533892A (en) * 2011-11-30 2014-12-15 ジアンスー チャンジアン エレクトロニクス テクノロジー カンパニーリミテッド Non-exposed pad ball grid array package structure and manufacturing method thereof
JP2015503233A (en) * 2011-11-30 2015-01-29 ジアンスー チャンジアン エレクトロニクス テクノロジー カンパニーリミテッド Barrel plating quad flat no lead (QFN) package structure and manufacturing method thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091606B2 (en) 2000-01-31 2006-08-15 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device and semiconductor module
EP1122778A3 (en) 2000-01-31 2004-04-07 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device
JP3679687B2 (en) 2000-06-08 2005-08-03 三洋電機株式会社 Hybrid integrated circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0974149A (en) * 1995-09-04 1997-03-18 Oki Electric Ind Co Ltd Small package and manufacture
WO1997039482A1 (en) * 1996-04-18 1997-10-23 Tessera, Inc. Methods for manufacturing a semiconductor package
US7165316B2 (en) 1996-04-18 2007-01-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US6033933A (en) * 1997-02-14 2000-03-07 Lg Semicon Co., Ltd Method for attaching a removable tape to encapsulate a semiconductor package
US7095054B2 (en) 1997-02-18 2006-08-22 Tessera, Inc. Semiconductor package having light sensitive chips
US6888168B2 (en) 1997-02-18 2005-05-03 Tessera, Inc. Semiconductor package having light sensitive chips
US6583444B2 (en) 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
JPH11121646A (en) * 1997-10-14 1999-04-30 Hitachi Cable Ltd Semiconductor package and manufacture thereof
JPH11195733A (en) * 1997-10-28 1999-07-21 Seiko Epson Corp Semiconductor device and manufacture thereof, and conductive board thereof
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
US7173336B2 (en) 2000-01-31 2007-02-06 Sanyo Electric Co., Ltd. Hybrid integrated circuit device
US7276793B2 (en) 2000-01-31 2007-10-02 Sanyo Electric Co., Ltd. Semiconductor device and semiconductor module
US6528879B2 (en) 2000-09-20 2003-03-04 Sanyo Electric Co., Ltd. Semiconductor device and semiconductor module
JP2008215498A (en) * 2007-03-05 2008-09-18 Nsk Warner Kk Wet multi-disc frictional engaging device
JP2014533892A (en) * 2011-11-30 2014-12-15 ジアンスー チャンジアン エレクトロニクス テクノロジー カンパニーリミテッド Non-exposed pad ball grid array package structure and manufacturing method thereof
JP2015503233A (en) * 2011-11-30 2015-01-29 ジアンスー チャンジアン エレクトロニクス テクノロジー カンパニーリミテッド Barrel plating quad flat no lead (QFN) package structure and manufacturing method thereof

Also Published As

Publication number Publication date
JP2781018B2 (en) 1998-07-30

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees