JPH0394431A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0394431A JPH0394431A JP1231134A JP23113489A JPH0394431A JP H0394431 A JPH0394431 A JP H0394431A JP 1231134 A JP1231134 A JP 1231134A JP 23113489 A JP23113489 A JP 23113489A JP H0394431 A JPH0394431 A JP H0394431A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- metal base
- circuit pattern
- resin
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010931 gold Substances 0.000 claims abstract description 14
- 229910052737 gold Inorganic materials 0.000 claims abstract description 14
- 239000011347 resin Substances 0.000 claims description 16
- 229920005989 resin Polymers 0.000 claims description 16
- 238000007747 plating Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 238000007789 sealing Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 24
- 239000011253 protective coating Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910000676 Si alloy Inorganic materials 0.000 description 3
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体チップ及び所要の回路部品等が一体的に
樹脂封止されて提供される半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor chip and necessary circuit components are integrally sealed with resin.
（従来技術）
半導体装置は電子装置をはじめきわめて多種類の製品に
ひろく用いられており、ＩＣカードといった小形商品に
も利用されるようになっている。(Prior Art) Semiconductor devices are widely used in a wide variety of products including electronic devices, and are also being used in small products such as IC cards.
これら製品で用いられる半導体装置の実装方式としては
、パッケージに半導体チップを搭載してパッケージごと
回路基板に実装するパッケージ方式と，回路基板に半導
体チップをじかに接続するペアチップ方式とがある．
前記のバッケージ方式の場合は，パッケージ内に半導体
チップが封止されて保護されているので、取り扱いがき
わめて容易であり、実装が容易にでき、また耐環境性に
優れている等の特徴がある。The mounting methods for semiconductor devices used in these products include the package method, in which a semiconductor chip is mounted in a package and the entire package is mounted on a circuit board, and the pair chip method, in which the semiconductor chip is directly connected to the circuit board. In the case of the package method described above, the semiconductor chip is sealed and protected within the package, so it is extremely easy to handle, easy to mount, and has excellent environmental resistance. .
これに対して、ペアチップ方式は回路基板にじかに半導
体チップを接続するから．小面積で実装でき、高密度実
装が可能になるという特徴がある。In contrast, the paired chip method connects semiconductor chips directly to the circuit board. It has the characteristics of being able to be mounted in a small area and enabling high-density mounting.
（発明が解決しようとする課題）
上記のように，回路基板等に半導体チップを搭載する方
法には、パッケージ方式あるいはペアチップ方式がある
が、いずれもそれぞれ別体に形成した半導体チップ等の
回路部品を別々に実装しているため、製造工数が複雑に
なって装置の信頼性が劣ること、装置の小形化が制限さ
れること等の問題点があった．
また、半導体チップは通常回路基板等の接続用基板に実
装されるから，ＩＣカードのようなきわめて薄形に形成
される装置においては基板の厚さが薄形化を制限すると
いう問題点があった．そこで、本発明は上記問題点を解
消すべくなされたものであり、その目的とするところは
、半導体チップと回路部品等を容易に一体的に搭載する
ことができ，製造工数を減少させることができて、製造
コストを下げることができると共に，製造プロセスを簡
略化することによて不良品の発生率を低下させ、装置の
信頼性を高めることができ、また，装置の小形化、薄形
化が達成でき，高密度実装を可能とする半導体装置の製
造方法を提供しようとするものである．
（Ｍｌ題を解決するための手段）
本発明は上記目的を達成するため次の構成をそなえる。(Problem to be Solved by the Invention) As mentioned above, there are two methods for mounting semiconductor chips on circuit boards, etc.: the package method and the pair chip method. Since these components were implemented separately, there were problems such as complicated manufacturing steps, poor device reliability, and restrictions on device miniaturization. Furthermore, since semiconductor chips are usually mounted on connection substrates such as circuit boards, there is a problem in that the thickness of the substrate limits how thin the device can be made to be, such as an IC card. Ta. Therefore, the present invention has been made to solve the above-mentioned problems, and its purpose is to easily mount a semiconductor chip, circuit components, etc. in an integrated manner, and to reduce manufacturing man-hours. It is possible to reduce manufacturing costs, reduce the incidence of defective products by simplifying the manufacturing process, and increase the reliability of the equipment. The aim is to provide a method for manufacturing semiconductor devices that enables high-density packaging and high-density packaging. (Means for solving the Ml problem) In order to achieve the above object, the present invention has the following configuration.
すなわち，金属ベース上に金めつき層等の非エッチング
金属層により回路パターンを形威し、金属ベース上に半
導体チップを接合して半導体チップと回路パターンとを
ワイヤボンディングによって接続し、金属ペースの半導
体チップが搭載された一方の面側を、半導体チップ、ボ
ンディングワイヤ，回路パターンを含めて一体的に樹脂
封止し、前記金属ベースのみをエッチング除去すること
を特徴とする。また、金属ベース上に半導体チップを接
合し，該半導体チップと前記金属ベースとをワイヤボン
ディングによって接続し、前記金属べ−スの半導体チッ
プを搭載した一方の面側を、半導体チップ、ボンディン
グワイヤを含めて一体的に樹脂封止し、金属ベースの露
出面に，レジストパターンを設けて金属ベースをエッチ
ングすることによって回路パターンを形成することを特
徴とする．
（作用）
金属ベース上に半導体チップを搭載した後，金属ベース
の半導体チップは搭載された一方の而側のみを樹脂封止
する．金属ベースをエッチングすることによって所要の
回路パターンを形成する．（実施例）
以下本発明の好適な実施例を添付図面に基づいて詳細に
説明する．
〔第１実施例〕
第１図（ａ）〜（ｅ）は本発明に係る半導体装置の製造
方法を示す説明図である．
第１図（ａ）は金属ベース１０に金めつきを施し、金め
つき層によって所要の回路パターンを形戊する工程を示
す．なお、金属ベース１０は薄平板状に形成した金属板
であるが、後工程においてエッチング除去する。したが
って、金属ベース１０にはエッチングによって溶解除去
しやすい金属、たとえば銅等を用いる．
１１は金属ベース１０上に所定の回路パターンにしたが
って設けたレジスｊ・パターンである。１２は金めつき
によって形成されたダイボンディング部、１３は回路パ
ターンである．
レジストパターンｌ１を除去した後、第１図（ｂ）に示
すようにダイボンディングペーストあるいは金一シリコ
ン共品合金等により、ダイボンディング部１２に半導体
チップ１４を接合し、回路パターン１３と半導体チップ
１４とをワイヤボンディングする．１５はボンディング
ワイヤである．また、所要の回路部品１６を回路パター
ン１３の所定位置に接続する．
次に，半導体チップ１４および回路部品１６、回路パタ
ーン１３等を樹脂封止する（第１図（Ｃ））。That is, a circuit pattern is formed on a metal base using a non-etched metal layer such as a gold plating layer, a semiconductor chip is bonded onto the metal base, and the semiconductor chip and the circuit pattern are connected by wire bonding. The method is characterized in that one side on which a semiconductor chip is mounted is integrally sealed with resin, including the semiconductor chip, bonding wires, and circuit pattern, and only the metal base is removed by etching. Further, a semiconductor chip is bonded onto a metal base, the semiconductor chip and the metal base are connected by wire bonding, and one side on which the metal-based semiconductor chip is mounted is connected to the semiconductor chip and the bonding wire. The circuit pattern is formed by forming a resist pattern on the exposed surface of the metal base and etching the metal base. (Function) After mounting a semiconductor chip on a metal base, only one side of the metal-based semiconductor chip on which it is mounted is sealed with resin. The desired circuit pattern is formed by etching the metal base. (Embodiments) Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. [First Embodiment] FIGS. 1(a) to 1(e) are explanatory diagrams showing a method for manufacturing a semiconductor device according to the present invention. FIG. 1(a) shows the process of applying gold plating to the metal base 10 and forming a desired circuit pattern using the gold plating layer. Note that the metal base 10 is a metal plate formed into a thin flat plate shape, and will be removed by etching in a later process. Therefore, the metal base 10 is made of a metal that is easily dissolved and removed by etching, such as copper. 11 is a resist j pattern provided on the metal base 10 according to a predetermined circuit pattern. 12 is a die bonding part formed by gold plating, and 13 is a circuit pattern. After removing the resist pattern l1, as shown in FIG. 1(b), the semiconductor chip 14 is bonded to the die bonding part 12 using a die bonding paste or a gold-silicon alloy, etc., and the circuit pattern 13 and the semiconductor chip 14 are bonded together. and wire bonding. 15 is a bonding wire. Further, required circuit components 16 are connected to predetermined positions of the circuit pattern 13. Next, the semiconductor chip 14, circuit components 16, circuit pattern 13, etc. are sealed with resin (FIG. 1(C)).
ｌ７は封止樹脂である．なお、この樹脂封止の際には図
のように金属ベースエ０の片面側のみを封止する．
次に、金属ベース１０全体をエッチングして除去する。l7 is a sealing resin. Note that during this resin sealing, only one side of the metal base E0 is sealed as shown in the figure. Next, the entire metal base 10 is etched and removed.
金属ベース１０上にあらかじめ設けておいた金めっき層
はこのエッチング処理によっては除去されないから、金
めつき層、すなわちダイボンディング部１２、回路パタ
ーン１３はそのまま封止樹脂１７に接合されて残る．こ
うして、第１図（ｄ）に示す半導体装置が得られる．な
お，回路パターン１３等は金めつき層に限らず、上記製
造方法からわかるように、金属ベース１０をエッチング
除去する際に侵されない金属、すなわち非エッチング金
属層によって形戒すればよい．
上記方法によって得られた半導体装置は半導体チップ１
４および回路部品１６等が樹脂封止され、ダイボンディ
ング部１２および回路パターン１３等の金めつき層部分
が露出している。この半導体装置は半導体チップモジュ
ールとしてそのまま電子装置に実装することができるが
，単体として用いる場合は、第１図（ｅ）のように外部
接続用の端子部１８等を除いて保護コーティング１９に
よって回路パターン１３等を被覆して保護するようにす
るとよい。Since the gold plating layer previously provided on the metal base 10 is not removed by this etching process, the gold plating layer, that is, the die bonding portion 12 and the circuit pattern 13 remain bonded to the sealing resin 17 as they are. In this way, the semiconductor device shown in FIG. 1(d) is obtained. Note that the circuit pattern 13 and the like are not limited to the gold-plated layer, but may be formed of a metal that will not be attacked when the metal base 10 is removed by etching, that is, a non-etched metal layer, as can be seen from the above manufacturing method. The semiconductor device obtained by the above method is semiconductor chip 1.
4 and circuit components 16 are sealed with resin, and the gold-plated layer portions such as the die bonding portion 12 and the circuit pattern 13 are exposed. This semiconductor device can be mounted in an electronic device as is as a semiconductor chip module, but when used as a single unit, the circuit is covered with a protective coating 19 except for the terminal portion 18 for external connection, etc., as shown in FIG. 1(e). It is preferable to cover and protect the pattern 13 and the like.
〔第２実施例〕
第２図（ａ）〜（ｅ）は半導体装置の他の製造方法を示
す説明図である。[Second Embodiment] FIGS. 2(a) to 2(e) are explanatory diagrams showing another method of manufacturing a semiconductor device.
図で１０は金属ベースで、上記例と同様に銅の薄平板を
用いる。第２図（ａ）は金属ベース１０の所定位置に半
導体チップ１４を接合した状態である。In the figure, reference numeral 10 denotes a metal base, which is a thin flat plate of copper as in the above example. FIG. 2(a) shows a state in which the semiconductor chip 14 is bonded to a predetermined position of the metal base 10.
半導体チップ１４はダイボンディングペーストを用いる
方法、あるいは金一シリコン共品合金による方法等によ
って接合できる．金−シリコン共品合金による場合はあ
らかじめ金属ベース１０に金めつきを施す．
次に，第２図（ｂ）に示すように、半導体チップ１４と
金属ベース１０とをワイヤボンディングする。The semiconductor chip 14 can be bonded by a method using die bonding paste, a method using a gold-silicon alloy, or the like. If a gold-silicon alloy is used, the metal base 10 is gold plated in advance. Next, as shown in FIG. 2(b), the semiconductor chip 14 and the metal base 10 are wire-bonded.
１５はボンディングワイヤである。ボンディングワイヤ
１５が接合される金属ベースＩＯのボンディング部２０
には、金めつき等を施して確実なボンディング性が得ら
れるようにする。15 is a bonding wire. Bonding portion 20 of metal base IO to which bonding wire 15 is bonded
Apply gold plating or the like to ensure reliable bonding.
なお、回路部品１６も金属ベース１０の所定位置に接合
する。Note that the circuit component 16 is also bonded to a predetermined position on the metal base 10.
次に，前記半導体チップ１２および回路部品２０等を樹
脂封止する．この樹脂封止の際には、半導体チップ１４
が搭載されている金属ベース１０の片面側のみ樹脂封止
し、前記ボンディングワイヤ１゜５等もすべて封止する
（第２図（Ｃ）） ．この状態で、封止体の下面に金属
ベース１０が露出する。Next, the semiconductor chip 12, circuit components 20, etc. are sealed with resin. During this resin sealing, the semiconductor chip 14
Only one side of the metal base 10 on which the metal base 10 is mounted is sealed with a resin, and the bonding wire 1.5 and the like are also all sealed (Fig. 2 (C)). In this state, the metal base 10 is exposed on the lower surface of the sealing body.
次に、金属ベース１０の下面にレジストを塗布し、露光
してレジストパターン２ｌを形戊する．（第１図（ｄ）
） ．このレジストパターン２１は金属ベース１０をエ
ッチングすることによって、ダイボンディング部２２、
回路パターン２３を形成するためのものである．
したがって、レジストパターン２ｌは前記ボンディング
部２０および回路部品１６等の配置位置に合わせて形成
する必要がある，
金属ベース１０をエッチングしてダイボンディング部２
２および回路パターン２３を形成した後、回路パターン
２３を保護するための保護コーティング１９を施す．保
護コーティング１９は外部接続用の端子部１８を露出さ
せてコーティングするものとし、この後，端子部１８に
金めつきを施して端子部１８を被覆する（第２図（ｅ）
）。Next, a resist is applied to the lower surface of the metal base 10 and exposed to form a resist pattern 2l. (Figure 1(d)
)． This resist pattern 21 is formed by etching the metal base 10 to form the die bonding portion 22,
This is for forming the circuit pattern 23. Therefore, the resist pattern 2l needs to be formed in accordance with the placement position of the bonding part 20 and the circuit components 16.The metal base 10 is etched and the die bonding part 2
2 and the circuit pattern 23 are formed, a protective coating 19 is applied to protect the circuit pattern 23. The protective coating 19 is applied to expose the terminal part 18 for external connection, and then gold plating is applied to the terminal part 18 to cover the terminal part 18 (Fig. 2(e)).
).
なお，ダイボンディング部２２および回路パターン２３
の耐環境性を得るため、上記方法とは逆に、ダイボンデ
ィング部２２および回路パターン２３に金めつきを施し
てから保護コーティング１９を施すようにしてもよい。Note that the die bonding part 22 and the circuit pattern 23
In order to obtain environmental resistance, the protective coating 19 may be applied after gold plating is applied to the die bonding portion 22 and the circuit pattern 23, contrary to the above method.
また、上記方法で用いる金属ベース１０としては電解銅
箔が有効に使用できる．この電解鋼箔はその表面が複雑
な凹凸形状を有する粗面として形成されるもので，粗面
を封止樹脂との接合側とすることにより、アンカー効果
によって回路パターン２３と強固に接合させることがで
きる。この場合、金属ベース１０のワイヤボンディング
部２０にはあらかじめ平滑処理および金めつき等を施し
ておくとよい。Furthermore, electrolytic copper foil can be effectively used as the metal base 10 used in the above method. This electrolytic steel foil is formed as a rough surface with a complicated uneven shape, and by using the rough surface as the side to be bonded to the sealing resin, it is possible to firmly bond to the circuit pattern 23 by an anchor effect. I can do it. In this case, it is preferable that the wire bonding portion 20 of the metal base 10 is subjected to smoothing treatment, gold plating, etc. in advance.
こうして、半導体チップおよび所要の回路部品等が一体
的に封止された半導体装置が得られる。In this way, a semiconductor device is obtained in which the semiconductor chip, necessary circuit components, etc. are integrally sealed.
上記実施例で得られた半導体装置は、各挿製品，用途に
応じて所要の回路パターンを形戊し、所要の回路部品を
搭載することにより、必要な機能を有するモジュールと
して設計して製造でき、各種機器に搭載して効果的に利
用することができる。The semiconductor device obtained in the above example can be designed and manufactured as a module with the necessary functions by shaping the required circuit pattern according to each insert product and application and mounting the required circuit components. It can be installed in various devices and used effectively.
また、第１図、第２図に示したように半導体チップは回
路パターンに接続されているだけで，回路基板を要しな
いから、装置の小形化、薄形化にきわめて効果的である
．これによって、ＩＣカードのような小形商品にも容易
に応用利用することが可能となる。Furthermore, as shown in Figures 1 and 2, the semiconductor chip is simply connected to the circuit pattern and does not require a circuit board, which is extremely effective in making the device smaller and thinner. This makes it possible to easily apply the method to small products such as IC cards.
また、上記製造方法ではワイヤボンディング法によって
いるから、製造上の信頼性が高いと共に、製造も容易で
あるという利点がある。さらに、リードフレームを用い
る場合等とくらべて、回路パターンを高密度に形成する
ことができ、高集積化された半導体チップを容易に搭載
することが可能となる。Further, since the above manufacturing method uses a wire bonding method, it has the advantage of high manufacturing reliability and easy manufacturing. Furthermore, compared to the case where a lead frame is used, circuit patterns can be formed with higher density, and highly integrated semiconductor chips can be easily mounted.
以上、本発明について好適な実施例を挙げて種々説明し
たが、本発明はこの実施例に限定されるものではなく、
発明の精神を逸脱しない範囲内で多くの改変を施し得る
のはもちろんのことである。The present invention has been variously explained above using preferred embodiments, but the present invention is not limited to these embodiments.
Of course, many modifications can be made without departing from the spirit of the invention.
（発明の効果）
上述したように，本発明に係る半導体装置の製造方法に
よれば、各種製品の用途に応じた製品を製造することが
容易にでき、また一体的に樹脂封止することによって製
造工数を減らすことができ、製品の信頼性を向上させる
ことができる．また、これによって製造コストを下げる
ことが可能となる．また、半導体装置の小形化、薄形化
を達成することができて高密度実装を可能にする等の著
効を奏する．(Effects of the Invention) As described above, according to the method for manufacturing a semiconductor device according to the present invention, it is possible to easily manufacture products according to the intended use of various products, and by integrally encapsulating with resin, Manufacturing man-hours can be reduced and product reliability can be improved. This also makes it possible to reduce manufacturing costs. In addition, it has great effects such as making semiconductor devices smaller and thinner, making high-density packaging possible.
第１図は本発明に係る半導体装置の製造方法を示す説明
図、第２図は他の製造方法を示す説明図である．
１０・・・金属ベース、 ｌ１・・・レジストパター
ン， １２・・・ダイボンディング部、１３・・・回路
パターン、 １４・・・半導体チップ， １５・・・
ボンディングワイヤ、 ｌ６・・・回路部品， １７
・・・封止樹脂、 １８・・・端子部、 １９・・・保
護コーティング、２０・・・ボンディング部、 ２１
・・・レジストパターン、 ２２・・・ダイボンディ
ング部、２３・・・回路パターン、 ２４・・・金め
つき。
第
１図FIG. 1 is an explanatory diagram showing a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is an explanatory diagram showing another manufacturing method. DESCRIPTION OF SYMBOLS 10... Metal base, l1... Resist pattern, 12... Die bonding part, 13... Circuit pattern, 14... Semiconductor chip, 15...
Bonding wire, l6... circuit component, 17
... Sealing resin, 18... Terminal part, 19... Protective coating, 20... Bonding part, 21
...Resist pattern, 22...Die bonding part, 23...Circuit pattern, 24...Gold plating. Figure 1
Claims (1)
により回路パターンを形成し、 金属ベース上に半導体チップを接合して半 導体チップと回路パターンとをワイヤボンディングによ
って接続し、 金属ベースの半導体チップが搭載された一 方の面側を、半導体チップ、ボンディングワイヤ、回路
パターンを含めて一体的に樹脂封止し、 前記金属ベースのみをエッチング除去する ことを特徴とする半導体装置の製造方法。 ２、金属ベース上に半導体チップを接合し、該半導体チ
ップと前記金属ベースとをワイ ヤボンディングによって接続し、 前記金属ベースの半導体チップを搭載した 一方の面側を、半導体チップ、ボンディングワイヤを含
めて一体的に樹脂封止し、 金属ベースの露出面に、レジストパターン を設けて金属ベースをエッチングすることによって回路
パターンを形成することを特徴とする半導体装置の製造
方法。[Claims] 1. A circuit pattern is formed on a metal base using a non-etched metal layer such as a gold plating layer, a semiconductor chip is bonded on the metal base, and the semiconductor chip and the circuit pattern are connected by wire bonding. , a semiconductor device characterized in that one side on which a metal-based semiconductor chip is mounted is integrally sealed with a resin, including the semiconductor chip, bonding wires, and circuit pattern, and only the metal base is removed by etching. manufacturing method. 2. Bonding a semiconductor chip onto a metal base, connecting the semiconductor chip and the metal base by wire bonding, and bonding one side of the metal base on which the semiconductor chip is mounted, including the semiconductor chip and the bonding wire. 1. A method of manufacturing a semiconductor device, comprising integrally sealing the semiconductor device with a resin, forming a resist pattern on the exposed surface of the metal base, and etching the metal base to form a circuit pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1231134A JP2781018B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1231134A JP2781018B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0394431A true JPH0394431A (en) | 1991-04-19 |
| JP2781018B2 JP2781018B2 (en) | 1998-07-30 |
Family
ID=16918815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1231134A Expired - Fee Related JP2781018B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2781018B2 (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0974149A (en) * | 1995-09-04 | 1997-03-18 | Oki Electric Ind Co Ltd | Small package and manufacture |
| WO1997039482A1 (en) * | 1996-04-18 | 1997-10-23 | Tessera, Inc. | Methods for manufacturing a semiconductor package |
| JPH11121646A (en) * | 1997-10-14 | 1999-04-30 | Hitachi Cable Ltd | Semiconductor package and manufacture thereof |
| JPH11195733A (en) * | 1997-10-28 | 1999-07-21 | Seiko Epson Corp | Semiconductor device and manufacture thereof, and conductive board thereof |
| US6033933A (en) * | 1997-02-14 | 2000-03-07 | Lg Semicon Co., Ltd | Method for attaching a removable tape to encapsulate a semiconductor package |
| US6451627B1 (en) * | 1999-09-07 | 2002-09-17 | Motorola, Inc. | Semiconductor device and process for manufacturing and packaging a semiconductor device |
| US6528879B2 (en) | 2000-09-20 | 2003-03-04 | Sanyo Electric Co., Ltd. | Semiconductor device and semiconductor module |
| US6583444B2 (en) | 1997-02-18 | 2003-06-24 | Tessera, Inc. | Semiconductor packages having light-sensitive chips |
| US7165316B2 (en) | 1996-04-18 | 2007-01-23 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
| US7173336B2 (en) | 2000-01-31 | 2007-02-06 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
| JP2008215498A (en) * | 2007-03-05 | 2008-09-18 | Nsk Warner Kk | Wet multi-disc frictional engaging device |
| JP2014533892A (en) * | 2011-11-30 | 2014-12-15 | ジアンスー チャンジアン エレクトロニクス テクノロジー カンパニーリミテッド | Non-exposed pad ball grid array package structure and manufacturing method thereof |
| JP2015503233A (en) * | 2011-11-30 | 2015-01-29 | ジアンスー チャンジアン エレクトロニクス テクノロジー カンパニーリミテッド | Barrel plating quad flat no lead (QFN) package structure and manufacturing method thereof |
| JP2022016475A (en) * | 2017-04-20 | 2022-01-21 | 旭化成エレクトロニクス株式会社 | Magnetic detector, current detector, manufacturing method for magnetic detector, and manufacturing method for current detector |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6548328B1 (en) | 2000-01-31 | 2003-04-15 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device |
| US7091606B2 (en) | 2000-01-31 | 2006-08-15 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device and semiconductor module |
| JP3679687B2 (en) | 2000-06-08 | 2005-08-03 | 三洋電機株式会社 | Hybrid integrated circuit device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59208756A (en) * | 1983-05-12 | 1984-11-27 | Sony Corp | Manufacture of semiconductor device package |
-
1989
- 1989-09-06 JP JP1231134A patent/JP2781018B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59208756A (en) * | 1983-05-12 | 1984-11-27 | Sony Corp | Manufacture of semiconductor device package |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0974149A (en) * | 1995-09-04 | 1997-03-18 | Oki Electric Ind Co Ltd | Small package and manufacture |
| WO1997039482A1 (en) * | 1996-04-18 | 1997-10-23 | Tessera, Inc. | Methods for manufacturing a semiconductor package |
| US7165316B2 (en) | 1996-04-18 | 2007-01-23 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
| US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
| US6033933A (en) * | 1997-02-14 | 2000-03-07 | Lg Semicon Co., Ltd | Method for attaching a removable tape to encapsulate a semiconductor package |
| US6583444B2 (en) | 1997-02-18 | 2003-06-24 | Tessera, Inc. | Semiconductor packages having light-sensitive chips |
| US6888168B2 (en) | 1997-02-18 | 2005-05-03 | Tessera, Inc. | Semiconductor package having light sensitive chips |
| US7095054B2 (en) | 1997-02-18 | 2006-08-22 | Tessera, Inc. | Semiconductor package having light sensitive chips |
| JPH11121646A (en) * | 1997-10-14 | 1999-04-30 | Hitachi Cable Ltd | Semiconductor package and manufacture thereof |
| JPH11195733A (en) * | 1997-10-28 | 1999-07-21 | Seiko Epson Corp | Semiconductor device and manufacture thereof, and conductive board thereof |
| US6451627B1 (en) * | 1999-09-07 | 2002-09-17 | Motorola, Inc. | Semiconductor device and process for manufacturing and packaging a semiconductor device |
| US7173336B2 (en) | 2000-01-31 | 2007-02-06 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
| US7276793B2 (en) | 2000-01-31 | 2007-10-02 | Sanyo Electric Co., Ltd. | Semiconductor device and semiconductor module |
| US6528879B2 (en) | 2000-09-20 | 2003-03-04 | Sanyo Electric Co., Ltd. | Semiconductor device and semiconductor module |
| JP2008215498A (en) * | 2007-03-05 | 2008-09-18 | Nsk Warner Kk | Wet multi-disc frictional engaging device |
| JP2014533892A (en) * | 2011-11-30 | 2014-12-15 | ジアンスー チャンジアン エレクトロニクス テクノロジー カンパニーリミテッド | Non-exposed pad ball grid array package structure and manufacturing method thereof |
| JP2015503233A (en) * | 2011-11-30 | 2015-01-29 | ジアンスー チャンジアン エレクトロニクス テクノロジー カンパニーリミテッド | Barrel plating quad flat no lead (QFN) package structure and manufacturing method thereof |
| JP2022016475A (en) * | 2017-04-20 | 2022-01-21 | 旭化成エレクトロニクス株式会社 | Magnetic detector, current detector, manufacturing method for magnetic detector, and manufacturing method for current detector |
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| Publication number | Publication date |
|---|---|
| JP2781018B2 (en) | 1998-07-30 |
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