JPS62214648A - Manufacture of package for semiconductor element - Google Patents
Manufacture of package for semiconductor elementInfo
- Publication number
- JPS62214648A JPS62214648A JP5769886A JP5769886A JPS62214648A JP S62214648 A JPS62214648 A JP S62214648A JP 5769886 A JP5769886 A JP 5769886A JP 5769886 A JP5769886 A JP 5769886A JP S62214648 A JPS62214648 A JP S62214648A
- Authority
- JP
- Japan
- Prior art keywords
- conductive paste
- ceramic green
- green sheet
- semiconductor element
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000919 ceramic Substances 0.000 claims abstract description 36
- 238000007747 plating Methods 0.000 claims abstract description 20
- 238000007639 printing Methods 0.000 claims abstract description 6
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 5
- 238000007789 sealing Methods 0.000 claims abstract description 5
- 229910052709 silver Inorganic materials 0.000 claims abstract description 3
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 10
- 230000002093 peripheral effect Effects 0.000 abstract description 7
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 239000002356 single layer Substances 0.000 abstract description 4
- 239000002365 multiple layer Substances 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000002075 main ingredient Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はＬＳＩのような半導体素子を装着させるための
、複層のセラミックシートからなる半真体素子用パッケ
ージの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a package for a semi-solid device made of a multilayer ceramic sheet, on which a semiconductor device such as an LSI is mounted.
（従来の技術）
セラミックス類の半導体素子用パッケージにはピングリ
ッドアレイ、パッドグリフドアレイ、チップキャリア等
の種々の種類があるが、いずれもセラミックシート上に
半導体素子を載せるためのメタライズ部と、半導体素子
の各端子と接続されるためのフィンガパターンと呼ばれ
る電極パターン部とスルーホール部を介した端子用パッ
ド部を備えたものである。このような半導体素子用パッ
ケージの製造工程においては上記のような各部分にＮｉ
メッキや金メッキが施されるが、比較的面積の広いメタ
ライズ部はともかく、極めて細い個々独立したフィンガ
パターンが印刷されている電掻パターン部に十分な厚さ
にメッキ層を形成するには個々のフィンガパターンを共
通電極に４通さセたうえでメッキを行う必要がある。こ
のため従来は、第５図に示すようにセラミックシート（
２０）上に外縁部分がつながった電極パターン部（２１
）を印刷しメッキを施したうえ、セラミックシート（２
０）に形成されたスナップライン（２２）からセラミッ
クシート（２０）の外縁部分を折って不要な部分を取除
くという製造方法が取られていた。しかしこのような従
来方法においては最終製品よりもかなり大きいセラミッ
クシートを製造しなければならないうえ、折り取られた
側面部分が平滑面とならず、また精度の高い外形寸法が
出ないうえ折り取りの際に本体部分にまでクラックが入
るおそれがある等の欠点があった。(Prior Art) There are various types of ceramic packages for semiconductor devices, such as pin grid arrays, pad grid arrays, and chip carriers. It is provided with an electrode pattern section called a finger pattern for connection to each terminal of a semiconductor element and a terminal pad section via a through-hole section. In the manufacturing process of such semiconductor device packages, Ni is added to each of the above parts.
Plating or gold plating is applied, but apart from the relatively wide metallized area, it is necessary to form a plating layer with a sufficient thickness on the electric scraping pattern area where extremely thin individual finger patterns are printed. It is necessary to set four finger patterns on the common electrode before plating. For this reason, conventionally, ceramic sheets (
20) Electrode pattern part (21) on which the outer edge part is connected
) is printed and plated, and a ceramic sheet (2
The manufacturing method used was to fold the outer edge portion of the ceramic sheet (20) from the snap line (22) formed at 0) and remove the unnecessary portion. However, in this conventional method, it is necessary to manufacture a ceramic sheet that is considerably larger than the final product, the broken side portions do not have a smooth surface, the external dimensions cannot be obtained with high precision, and the break-off process is difficult. There were drawbacks such as the risk of cracks entering the main body.
（発明が解決しようとする問題点）
本発明は上記のような従来の問題点を解決して、必要以
上に大きいセラミックシートを製造する必要がなく、シ
かも全フィンガパターンに対して容易かつ確実に十分な
厚さのメッキを施すことができる半Ｗ体素子用パッケー
ジの製造方法を目的として完成されたものである。(Problems to be Solved by the Invention) The present invention solves the above-mentioned conventional problems, eliminates the need to manufacture ceramic sheets that are larger than necessary, and allows easy and reliable production of all finger patterns. This was completed with the aim of creating a method for manufacturing a package for half-W solid elements, which can be plated to a sufficient thickness.
（問題点を解決するための手段）
本発明は半導体素子が装着されるメタライズ部と、半う
５体素子と接続される電極パターン部と、外部端子と、
それへの接続用のスルーホール部のメタライズとが形成
された単層又は複層の第１のセラミックグリーンシート
上に更に半導体素子を気密封着するための第２のセラミ
ックグリーンシートを積層し所要外形寸法にナイフカッ
トして焼成したうえ第１のセラミックシートの外周側面
に露出させたメタライズ部の表面にＮｉ、へｇ、Ｃｕ等
を主成分とする導電ペーストを印刷してこれを焼付け、
その後メッキを施したうえこの導電ペーストを除去する
ことを特徴とするものである。(Means for Solving the Problems) The present invention includes a metallized portion to which a semiconductor element is mounted, an electrode pattern portion connected to the half-pentagram element, an external terminal,
A second ceramic green sheet for hermetically sealing a semiconductor element is further laminated on the single-layer or multi-layer first ceramic green sheet on which a metallized through-hole part for connection thereto is formed. After cutting with a knife to the external dimensions and firing, a conductive paste containing Ni, Heg, Cu, etc. as the main ingredients is printed on the surface of the metallized portion exposed on the outer peripheral side of the first ceramic sheet and baked.
The feature is that after plating is applied, the conductive paste is removed.
次に本発明をチップキャリアを示す図面に暴いて更に詳
細に説明すると、第１図において（１１は（ｌＡ）及び
くＩＢ）の２枚のシートからなる第１のセラミックグリ
ーンシート、（２）はその上面に積層された第２のセラ
ミックグリーンシートである。第１のセラミックグリー
ンシート＋１１には半導体素子が載置されるメタライズ
部（３）と、半導体素子の各端子とワイヤボンディング
等によって接続される電極パターン部（４）と、端子接
続用のスルーホール部（５）とが形成されており、この
スルーホール部（５）の内周面には各電極パターンと接
続されたメタライズ部が形°成されている。なお図示の
プラグインタイブのものでは後述するようにスルーホー
ル部（５）の下面に端子用のピン（６）がろう付けされ
るが、リードレスタイプではピン（６）はなく、またフ
リップチップタイプのものでは電極パターン部（４）と
メタライズ部（３）とが一体化しており、半導体素子を
メタライズ部（３）の上面に載せると半導体素子の下面
とメタライズ部（３）とが導通してワイヤボンディング
を省くことができるうえ、第１のセラミックグリーンシ
ート（１１を単層とすることができる等の種々のバリエ
ーションが存在することは当業者には明らかなことであ
る。Next, the present invention will be explained in more detail with reference to a drawing showing a chip carrier. In FIG. is a second ceramic green sheet laminated on the upper surface thereof. The first ceramic green sheet +11 includes a metallized part (3) on which a semiconductor element is placed, an electrode pattern part (4) connected to each terminal of the semiconductor element by wire bonding, etc., and a through hole for terminal connection. A portion (5) is formed, and a metallized portion connected to each electrode pattern is formed on the inner peripheral surface of this through hole portion (5). In addition, in the plug-in type shown in the figure, a terminal pin (6) is brazed to the bottom surface of the through-hole part (5) as described later, but in the leadless type, there is no pin (6), and the flip-chip type does not have a pin (6). In this type, the electrode pattern part (4) and the metallized part (3) are integrated, and when the semiconductor element is placed on the upper surface of the metallized part (3), the lower surface of the semiconductor element and the metallized part (3) are electrically connected. It is obvious to those skilled in the art that there are various variations, such as eliminating wire bonding and making the first ceramic green sheet (11) a single layer.
上記のような単層又は複層の第１のセラミックグリーン
シート（【）上に、半導体素子を気密封着するための第
２のセラミックグリーンシート（２）を積層したうえ外
形寸法に合わせてナイフカットし、その後常法によって
焼成すれば、第１及び第２のセラミックグリーンシート
（１）、（２）は積層一体化された第１及び第２のセラ
ミックシート（１）、（２）となる、このとき第１図に
示すように第１のセラミックシートｆｉｌの外周側面に
は電極パターン部（４）の端部が平滑な側面に点状に露
出することとなる。そこで本発明においては、このよう
に点状に露出した電極パターン部（４）を利用してその
表面上にＮｉ、へｇ、Ｃｕ等を主成分とする導電ペース
ト（７）を印刷して独立した各電極パターン部（４）を
相互に導通させる。ここで導電ペーストとは焼成して感
電体となるペーストを意味する。導電ペーストの主成分
としてＮｉ、 Ａｇ、 Ｃｕ等を選択したのは、アルミ
ナその他の焼成されたセラミック譬との間に接合力が得
られるうえ、大きい導電性を有するためである。A second ceramic green sheet (2) for hermetically sealing a semiconductor element is laminated on the first ceramic green sheet (2), which is a single layer or a multilayer as described above, and then cut with a knife according to the external dimensions. When cut and then fired by a conventional method, the first and second ceramic green sheets (1) and (2) become an integrated laminated first and second ceramic sheet (1) and (2). At this time, as shown in FIG. 1, the ends of the electrode pattern portions (4) are exposed in dots on the smooth side surface of the outer peripheral side surface of the first ceramic sheet fil. Therefore, in the present invention, a conductive paste (7) mainly composed of Ni, Heg, Cu, etc. is printed on the surface of the electrode pattern part (4) exposed in the form of dots, so that it becomes independent. The electrode pattern portions (4) thus formed are electrically connected to each other. Here, the conductive paste means a paste that becomes an electric shock body when fired. The reason why Ni, Ag, Cu, etc. were selected as the main components of the conductive paste is that they can provide bonding strength with alumina or other fired ceramics and have high conductivity.
このようなＲ’ｒｌペースト（７）を印刷後にその表面
に更に電気絶縁層（８）を印刷しておくことが好ましく
、かくして第２図の状態とされた第１及び第２のセラミ
ンクシート＋１１、（２）は次に再び焼成されて４電ペ
ースト（７）と電気絶縁層（８）とが焼付けられる。After printing such R'rl paste (7), it is preferable to further print an electrical insulating layer (8) on the surface thereof, and thus the first and second ceramic sheets are in the state shown in FIG. +11, (2) is then fired again to bake the quaternary paste (7) and the electrically insulating layer (8).
その後第３図に示すように焼成品の全面又は片面にＮｉ
メッキ層（９）が形成され、スルーホール部（５）の下
面にビン（６）がろう付けされたうえで第４図のように
Ｎｉ、 Ａｕによる仕上げメッキが施され、仕上げメッ
キ７１ Ｑ［１１が形成される。本発明においては各電
極パターン部（４）は相互に導通されているので、この
ようなＮｉメッキあるいは仕上げメッキの際には、各電
極パターン部（４）を個別にメッキ用電極に接続させる
必要はなく、全電掻パターン部（４）に容易かつ確実に
十分な厚さのＮｉメッキ層（９）及び仕上げメッキＩ？
！Ｑｌを形成することができる。また前述のように電気
絶縁層（８）により導電ペースト（７）の表面を覆って
おけば、導電ペースト（７）の表面にメッキ層が形成さ
れることを防止でき、高価な金メッキ液等の浪費を防止
することができる。このようにして仕上げメッキを完了
した後にセラミックシートｆｉ＋、（２）の外周側面を
研磨して導電ペースト（７）を電気絶縁層（８）ととも
に除去し、各電極パターン部（４）は電気的に独立した
最初の状態に戻されることとなる。After that, as shown in Figure 3, Ni is applied to the entire surface or one side of the fired product.
A plating layer (9) is formed, a bottle (6) is brazed to the bottom surface of the through-hole part (5), and finish plating with Ni and Au is applied as shown in Fig. 4, resulting in finish plating 71 Q[ 11 is formed. In the present invention, each electrode pattern part (4) is electrically connected to each other, so during such Ni plating or finish plating, it is necessary to individually connect each electrode pattern part (4) to the plating electrode. However, the Ni plating layer (9) and the final plating layer (9) with a sufficient thickness can be easily and reliably coated on the entire electric scratching pattern part (4).
! Ql can be formed. In addition, if the surface of the conductive paste (7) is covered with the electrically insulating layer (8) as described above, it is possible to prevent the formation of a plating layer on the surface of the conductive paste (7), and it is possible to prevent the formation of a plating layer on the surface of the conductive paste (7). Waste can be prevented. After completing the final plating in this way, the outer peripheral side of the ceramic sheet fi+ (2) is polished to remove the conductive paste (7) together with the electrically insulating layer (8), and each electrode pattern part (4) is It will be returned to its initial state of independence.
（発明の効果）
本発明は以上の説明からも明らかなように、第１のセラ
ミックグリーンシートと第２のセラミックグリーンシー
トとを積層し焼成したときに第１のセラミックシートの
外周側面に点状に露出する電極パターン部を有効に利用
し、その表面にＮｉ、＾１．Ｃｕ等のような焼成された
セラミック質との親和性及び導電性に優れた金属を主成
分とする導電ペーストを印刷することにより個々独立し
た電極パターン部を相互に電気的に導通させたものであ
るから、従来のようにセラミックシートを太き目に製造
する等の方法を取らなくても各電極パターン部の表面に
十分な厚さのめっき層を容易に形成することができる。(Effects of the Invention) As is clear from the above description, when the first ceramic green sheet and the second ceramic green sheet are laminated and fired, dots appear on the outer peripheral side of the first ceramic green sheet. By effectively utilizing the electrode pattern portion exposed to the surface, Ni, ^1. Individual electrode pattern parts are electrically connected to each other by printing a conductive paste whose main component is a metal with excellent conductivity and affinity with fired ceramic materials such as Cu. Therefore, a sufficiently thick plating layer can be easily formed on the surface of each electrode pattern portion without using a conventional method such as manufacturing thick ceramic sheets.
従って本発明の方法によればセラミックシートの端部を
折り取る必要がなく、これに伴なうクラックの発生等の
おそれもないうえ、メソキ工程後に導電厚膜ペーストは
側面研磨により容易に除去されるのでパッケージの外周
側面は平滑面となる利点もある。なお前述のように導電
ペーストの表面に電気絶縁層を印刷しておけば高価な金
のようなメッキ金属の無駄を省くことも可能となる。よ
って本発明は従来の問題点を解消した半導体素子用パフ
ケージの製造方法として、産業の発展に寄与するところ
は極めて大きいものである。Therefore, according to the method of the present invention, there is no need to break off the edges of the ceramic sheet, and there is no risk of cracks occurring due to this, and the conductive thick film paste can be easily removed by side polishing after the mesoki process. This also has the advantage that the outer peripheral side of the package is a smooth surface. Note that if an electrically insulating layer is printed on the surface of the conductive paste as described above, it is also possible to eliminate waste of expensive plated metals such as gold. Therefore, the present invention greatly contributes to the development of industry as a method for manufacturing puff cages for semiconductor devices that eliminates the problems of the conventional methods.
【図面の簡単な説明】
第１図、第２図、第３図、第４図は本発明の工程を示す
断面図、第５図は従来工程を説明するための平面図であ
る。
（１）：第１のセラミックグリーンシート、（２）：第
２のセラミックグリーンシート、（３）：メクライズ部
、（４）：電極パターン部、（５）ニスルーホール部、
（７）：導電ペースト。
ｊＩ ３ 図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1, FIG. 2, FIG. 3, and FIG. 4 are cross-sectional views showing the process of the present invention, and FIG. 5 is a plan view for explaining the conventional process. (1): first ceramic green sheet, (2): second ceramic green sheet, (3): mekrise section, (4): electrode pattern section, (5) varnish through hole section,
(7): Conductive paste. jI 3 diagram
Claims (1)
子と接続される電極パターン部と、外部端子と、それへ
の接続用のスルーホール部のメタライズとが形成された
単層又は複層の第１のセラミックグリーンシート上に更
に半導体素子を気密封着するための第２のセラミックグ
リーンシートを積層し所要外形寸法にナイフカットして
焼成したうえ第１のセラミックシートの外周側面に露出
させたメタライズ部の表面にＮｉ、Ａｇ、Ｃｕ等を主成
分とする導電ペーストを印刷してこれを焼付け、その後
メッキを施したうえこの導電ペーストを除去することを
特徴とする半導体素子用パッケージの製造方法。 ２、導電ペーストの印刷後にその表面に電気絶縁層を印
刷したうえ焼付け、その後メッキを施す特許請求の範囲
第１項記載の半導体素子用パッケージの製造方法。[Claims] 1. A unit in which a metallized part to which a semiconductor element is attached, an electrode pattern part to be connected to the semiconductor element, an external terminal, and a metallized through-hole part for connection to the external terminal are formed. A second ceramic green sheet for hermetically sealing a semiconductor element is laminated on top of the layer or multilayer first ceramic green sheet, cut with a knife to the required external dimensions, fired, and then the outer periphery of the first ceramic sheet is laminated. A semiconductor device characterized by printing a conductive paste mainly composed of Ni, Ag, Cu, etc. on the surface of the metallized part exposed on the side surface, baking it, plating it, and removing the conductive paste. manufacturing method for packaging. 2. The method of manufacturing a package for a semiconductor device according to claim 1, wherein after printing the conductive paste, an electrically insulating layer is printed on the surface of the conductive paste, baked, and then plated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5769886A JPS62214648A (en) | 1986-03-15 | 1986-03-15 | Manufacture of package for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5769886A JPS62214648A (en) | 1986-03-15 | 1986-03-15 | Manufacture of package for semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62214648A true JPS62214648A (en) | 1987-09-21 |
| JPH0459778B2 JPH0459778B2 (en) | 1992-09-24 |
Family
ID=13063155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5769886A Granted JPS62214648A (en) | 1986-03-15 | 1986-03-15 | Manufacture of package for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62214648A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5067007A (en) * | 1988-06-13 | 1991-11-19 | Hitachi, Ltd. | Semiconductor device having leads for mounting to a surface of a printed circuit board |
| US5094969A (en) * | 1989-09-14 | 1992-03-10 | Litton Systems, Inc. | Method for making a stackable multilayer substrate for mounting integrated circuits |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5816552A (en) * | 1981-07-22 | 1983-01-31 | Fujitsu Ltd | Package for semiconductor element |
| JPS5851544A (en) * | 1981-09-22 | 1983-03-26 | Fujitsu Ltd | Package for semiconductor device |
-
1986
- 1986-03-15 JP JP5769886A patent/JPS62214648A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5816552A (en) * | 1981-07-22 | 1983-01-31 | Fujitsu Ltd | Package for semiconductor element |
| JPS5851544A (en) * | 1981-09-22 | 1983-03-26 | Fujitsu Ltd | Package for semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5067007A (en) * | 1988-06-13 | 1991-11-19 | Hitachi, Ltd. | Semiconductor device having leads for mounting to a surface of a printed circuit board |
| US5094969A (en) * | 1989-09-14 | 1992-03-10 | Litton Systems, Inc. | Method for making a stackable multilayer substrate for mounting integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0459778B2 (en) | 1992-09-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |