JPS5917255A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5917255A JPS5917255A JP57126161A JP12616182A JPS5917255A JP S5917255 A JPS5917255 A JP S5917255A JP 57126161 A JP57126161 A JP 57126161A JP 12616182 A JP12616182 A JP 12616182A JP S5917255 A JPS5917255 A JP S5917255A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- tungsten thin
- film
- bonding pad
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に係シ、特にセラミック積層型の半
導体装置におけるポンディングパッド部の構造に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to the structure of a bonding pad portion in a ceramic laminated semiconductor device.
従来のこの種の半導体装置について図面を用いて説明す
る。第１図は平面図、第２図は第１図のＡ−Ａ部分拡大
断面図、第３図はＢ−Ｂ部分拡大断面図である。これら
の図において、１，２．３はそれぞれセラミック積層体
を形成するところの下段、中段、上段のセラミック片、
４はシールリンク、５は半導体素子、６は外部取り出し
のため中段セラミック片２に印刷され、焼成されたタン
グステンの薄膜、７はタングステン薄膜６のポンディン
グバット部の上部にメッキ処理して形成されたＮｉ膜、
８はＮｉ膜の上にメッキで形成されたＡμ膜、９は半導
体素子５上に形成された電極（図示せず）とポンディン
グパッドとを電気的に接続するだめの金属細線である。A conventional semiconductor device of this type will be explained with reference to the drawings. 1 is a plan view, FIG. 2 is an enlarged cross-sectional view of a portion taken along line AA in FIG. 1, and FIG. 3 is an enlarged cross-sectional view taken along line B-B of FIG. In these figures, 1, 2.3 are the lower, middle, and upper ceramic pieces forming the ceramic laminate, respectively;
4 is a seal link, 5 is a semiconductor element, 6 is a tungsten thin film printed and fired on the middle ceramic piece 2 for external extraction, and 7 is formed by plating the upper part of the pounding butt part of the tungsten thin film 6. Ni film,
8 is an Aμ film formed by plating on the Ni film, and 9 is a thin metal wire for electrically connecting the electrode (not shown) formed on the semiconductor element 5 and the bonding pad.
このようにタングステン薄膜６を印刷し、焼成後、Ｎｌ
メッキ７を１〜２μ施し、次にＡμメッキ８を０．５〜
２μ施す場合の印刷法は、例えばタングステンの粉末を
有機物のバインダの中にしみこませ、これを中段セラミ
ック片２に印刷を施す。After printing the tungsten thin film 6 in this way and baking it, the Nl
Plating 7 is applied to 1 to 2μ, then Aμ plating 8 is applied to 0.5 to 2μ.
In the printing method for applying 2μ, for example, tungsten powder is impregnated into an organic binder, and this is printed on the middle ceramic piece 2.
しかし、寸法通り正確には印刷できず、左右両端部が中
段セラミック片２へ流れ丸みが生じてしまう。一般に、
タングステン薄膜６の幅が十分有る場合、前記丸みが生
じても全体としてはほとんど平面状伸であり、ボンディ
ング作業にも問題にはならない。しかし、タングステン
薄膜６０幅が、例えば、２００μ以下のように狭くなれ
ば、印刷後第４図に示すような丸みを帯びた状態となり
、はとんど平面状態が得られなくなる。この状態で焼成
し、Ｎｉメッキ７、次にＡμメッキ８を施すと、平面が
得られない為、金属細線９な用いてのボンディング作業
は極めて困難となる欠点があった。However, it is not possible to print accurately to the dimensions, and both left and right ends flow toward the middle ceramic piece 2 and become rounded. in general,
If the tungsten thin film 6 has a sufficient width, even if the rounding occurs, the entire film is almost a flat elongation and does not pose a problem in bonding work. However, if the width of the tungsten thin film 60 is reduced to, for example, 200 μm or less, the tungsten thin film 60 becomes rounded as shown in FIG. 4 after printing, and it is almost impossible to obtain a flat state. If it is fired in this state and Ni plating 7 and then Aμ plating 8 are applied, a flat surface cannot be obtained, which has the disadvantage that bonding work using thin metal wire 9 is extremely difficult.
本発明の目的は、タングステン薄膜が印刷されるセラミ
ック片に溝を設けることによって、タングステン薄膜の
幅が狭い場合でも、丸みを減少させ、平面領域を多く得
、ボンディング作業が容易に実施できるようにした半導
体装置を提供するにある。The purpose of the present invention is to provide grooves in the ceramic piece on which the tungsten thin film is printed, thereby reducing the roundness and obtaining a large planar area even when the width of the tungsten thin film is narrow, so that the bonding operation can be carried out easily. The purpose of the present invention is to provide a semiconductor device with improved performance.
本発明の半導体装置は、セラミック積層体からなる容器
に半導体素子を収容し気密に封止したものにおいて、前
記容器のポンディングパッド部には予じめ溝が設けられ
、この溝を含む領域上にポンディングパッドのメタライ
ズ層が形成されている構成を有する。In the semiconductor device of the present invention, a semiconductor element is housed in a container made of a ceramic laminate and hermetically sealed, wherein a groove is provided in advance in a bonding pad portion of the container, and a region including the groove is It has a structure in which a metallized layer of a bonding pad is formed on the top.
つぎに本発明を実施例により説明する。Next, the present invention will be explained by examples.
第５図は本発明の一実施例に係る、第２図の従来例に対
応する部分断面図、第６図は第５図の八−Ａ部分拡大断
面図である。これらの図において、セラミック積層体容
器のポンディングパッド形成部のセラミック片には、予
じめ、ポンディングパッドの長さ方向に沿う溝１ｏが設
けられ、この溝１０を含む領域上にタングステン薄膜６
が印刷されている。このように溝１０があることにより
、タングステン薄膜６の幅が狭い場合でも印刷後の丸み
が減少し、平面領域を多く得ることが可能となる。FIG. 5 is a partial sectional view corresponding to the conventional example shown in FIG. 2, according to an embodiment of the present invention, and FIG. 6 is an enlarged partial sectional view taken along line 8-A in FIG. In these figures, a groove 1o along the length direction of the bonding pad is previously provided in the ceramic piece of the bonding pad forming part of the ceramic laminate container, and a tungsten thin film is formed on the area including this groove 10. 6
is printed. Due to the presence of the grooves 10 in this manner, even if the width of the tungsten thin film 6 is narrow, the roundness after printing is reduced and a large planar area can be obtained.
この溝形成の効果を示す具体例として下表の成績が得ら
れた。As a specific example showing the effect of this groove formation, the results shown in the table below were obtained.
第１表
なお、溝ｌＯの形成方法としては、プレスまたは削シ取
りなどで形成できる。また、溝１０は、１個のポンディ
ングパッド当シ１本のみに限らず複数本形成してもよい
。Table 1 Note that the groove IO can be formed by pressing, scraping, or the like. Further, the number of grooves 10 is not limited to one per one bonding pad, but may be formed in plural numbers.
このように、ポンディングパッド形成部に予じめ溝を設
けて置いて、この部分にタングステン薄膜を印刷すれば
、タングステン薄膜の幅が狭い場合でも印刷後の丸みが
減少゛し、平面領域が多くなシ、金属細線のボンディン
グが極めて容易となる。In this way, if a groove is prepared in advance in the bonding pad forming area and a tungsten thin film is printed on this part, even if the width of the tungsten thin film is narrow, the roundness after printing will be reduced and the flat area will be Bonding of many thin metal wires becomes extremely easy.
第１図は従来のセラミック積層型半導体装置の平面図、
第２図は第１図のＡ−Ａ部分拡大断面図、第３図は第１
図のＢ−Ｂ部分拡大断面図、第４図は幅の狭いポンディ
ングパッドの断面図、第５図は第３図の従来例に対応す
る本発明の一実施例の部分拡大断面図、第６図は第５図
のＡ−Ａ拡大部分断面図である。
１．２．３・・・・・・セラミック片、４・・・・・・
シールリンク、５・・・・・・半導体素子、６・・・・
・・タングステン薄膜、７・・・・・・Ｎ１メッキ層、
８・・・・・・Ａμメッキ層、９・・・・・・金属細線
、１０・・・・・・溝。
箭 ４ 図
ス ５ 図
萬 ６ 図Figure 1 is a plan view of a conventional ceramic laminated semiconductor device.
Figure 2 is an enlarged cross-sectional view of part A-A in Figure 1, and Figure 3 is an enlarged cross-sectional view of Figure 1.
4 is a sectional view of a narrow bonding pad; FIG. 5 is a partially enlarged sectional view of an embodiment of the present invention corresponding to the conventional example shown in FIG. 3; FIG. 6 is an enlarged partial sectional view taken along the line AA in FIG. 5. 1.2.3...Ceramic piece, 4...
Seal link, 5... Semiconductor element, 6...
...Tungsten thin film, 7...N1 plating layer,
8...Aμ plating layer, 9...Metal thin wire, 10...Groove. Bamboo 4 Figures 5 Figures 6 Figures
Claims (1)
密封止した半導体装置において、前記容器のポンディン
グパッド部には溝が設けられ、この溝を含む領域上にポ
ンディングパッドのメタ２イズ層が形成されていること
を特徴とする半導体装置。In a semiconductor device in which a semiconductor element is housed in a container made of a ceramic laminate and hermetically sealed, a groove is provided in a bonding pad portion of the container, and a meta2ized layer of the bonding pad is formed on a region including the groove. A semiconductor device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57126161A JPS5917255A (en) | 1982-07-20 | 1982-07-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57126161A JPS5917255A (en) | 1982-07-20 | 1982-07-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5917255A true JPS5917255A (en) | 1984-01-28 |
Family
ID=14928182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57126161A Pending JPS5917255A (en) | 1982-07-20 | 1982-07-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5917255A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04213647A (en) * | 1990-08-15 | 1992-08-04 | Kajima Corp | Method for constructing wall body by using special solid ware-netting panel |
-
1982
- 1982-07-20 JP JP57126161A patent/JPS5917255A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04213647A (en) * | 1990-08-15 | 1992-08-04 | Kajima Corp | Method for constructing wall body by using special solid ware-netting panel |
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