JPH09199301A - Connected chip resistors and substrate for mounting connected chip resistors - Google Patents

Connected chip resistors and substrate for mounting connected chip resistors

Info

Publication number
JPH09199301A
JPH09199301A JP8006344A JP634496A JPH09199301A JP H09199301 A JPH09199301 A JP H09199301A JP 8006344 A JP8006344 A JP 8006344A JP 634496 A JP634496 A JP 634496A JP H09199301 A JPH09199301 A JP H09199301A
Authority
JP
Japan
Prior art keywords
insulating substrate
multiple chip
chip resistor
width
surface side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8006344A
Other languages
Japanese (ja)
Other versions
JP3557762B2 (en
Inventor
Hideo Kobayashi
英雄 小林
Hiroyuki Yamada
博之 山田
Seiji Tsuda
清二 津田
Tsuneo Kawabata
統夫 川端
Akio Fukuoka
章夫 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP00634496A priority Critical patent/JP3557762B2/en
Publication of JPH09199301A publication Critical patent/JPH09199301A/en
Application granted granted Critical
Publication of JP3557762B2 publication Critical patent/JP3557762B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To strengthen a surface tension and to thereby increase self-alignment effect by increasing the overlap portion of the width or end face electrodes on a back surface and the width of lands of a substrate mounted with the electrodes. SOLUTION: Connected chip resistors have four resistors 16 provided on the upper surface of a rectangular insulating substrate 1 and end face electrodes leading from and electrically connected with the respective resistors 16 and provided from the upper surface to back surface of the insulating substrate 11. The upper surface-side end face electrodes 13a to 13d have an equal pitch to one another. The outermost end face electrodes 15a and 15d on the back surface have pitches 1.3 to 1.6 times as large as those of the end face electrodes 15b and 15c at the center of the back surface.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、各種電子回路に用
いられる多連チップ抵抗器およびそれを実装する実装基
板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple chip resistor used in various electronic circuits and a mounting board for mounting the same.

【0002】[0002]

【従来の技術】従来、多連チップ抵抗器は実願平4−6
1226号(実開平6−26210号)のマイクロフィ
ルムに記載されたものが知られている。
2. Description of the Related Art Conventionally, a multiple chip resistor is disclosed in Japanese Patent Application No.
The thing described in the microfilm of No. 1226 (Jitsukaihei 6-26210) is known.

【0003】図8は従来の多連チップ抵抗器の上面図で
ある。図において、絶縁基板1の上面に形成された4つ
の抵抗体2a〜2dと、抵抗体2a〜2dの両端から、
絶縁基板1の端面および裏面に導出する端子電極3a〜
3d、4a〜4dを有する多連チップ抵抗器において、
絶縁基板1の最外部に形成された端子電極3a,3d,
4a,4dの幅を、最外部の端子に挟まれて配置された
中央部の端子電極3b,3c,4b,4cの幅に対し
て、1.1〜1.3倍としたものが開示されている。
FIG. 8 is a top view of a conventional multiple chip resistor. In the figure, four resistors 2a to 2d formed on the upper surface of the insulating substrate 1 and both ends of the resistors 2a to 2d are
Terminal electrodes 3a led to the end surface and the back surface of the insulating substrate 1 to
In a multiple chip resistor having 3d, 4a-4d,
Terminal electrodes 3a, 3d formed on the outermost part of the insulating substrate 1,
Disclosed is that the width of 4a, 4d is 1.1 to 1.3 times the width of the central terminal electrodes 3b, 3c, 4b, 4c sandwiched between the outermost terminals. ing.

【0004】[0004]

【発明が解決しようとする課題】上記従来の多連チップ
抵抗器は、凹部の形状が真円状であった上、4隅部分に
も凹部を形成していたために、最外部の裏面側端面電極
を中央部の裏面側端面電極の1.3倍以上で形成する
と、当然のことながら凹部間が狭くなり、そこで分断が
多発していた。従って、最外部の裏面側端面電極は中央
部の裏面側端面電極の1.3倍以下としなくてはなら
ず、セルフアライメント効果を重要視される小形の多連
チップ抵抗器においては十分ではなく、従来以上のセル
フアライメント効果を持つ多連チップ抵抗器が要求され
ている。
In the above-mentioned conventional multiple chip resistor, the shape of the concave portion is a perfect circle and the concave portions are formed at the four corners as well. If the electrode is formed 1.3 times or more as large as the electrode on the rear surface side of the central portion, the space between the concave portions is naturally narrowed, and the division frequently occurs there. Therefore, the outermost back-side end surface electrode must be 1.3 times or less than the central back-side end surface electrode, which is not sufficient for a small-sized multiple chip resistor where the self-alignment effect is important. There is a demand for a multiple chip resistor having a self-alignment effect higher than conventional ones.

【0005】一般に、セルフアライメント効果は多連チ
ップ抵抗器の端子電極の幅と、それを実装する実装基板
のランドの幅の重なりが大きいほど表面張力が働き、大
きくなることが知られている。
It is generally known that the self-alignment effect increases as the overlap between the width of the terminal electrode of the multiple chip resistor and the width of the land of the mounting board on which it is mounted increases the surface tension.

【0006】本発明は、上記要求を満足させることを目
的とするものである。
The present invention aims to satisfy the above requirements.

【0007】[0007]

【課題を解決するための手段】この課題を解決するため
に本発明は、絶縁基板の長手方向に対して端面電極の上
面側の幅は等ピッチでかつ裏面側の幅は最外部が中央部
に対して1.3倍〜1.6倍となるように構成したもの
である。
In order to solve this problem, according to the present invention, the width of the end surface electrode on the upper surface side is equal pitch with respect to the longitudinal direction of the insulating substrate, and the width of the back surface side is the outermost central portion. It is configured to be 1.3 to 1.6 times.

【0008】また、多連チップ抵抗器の絶縁基板の長手
方向に対して端面電極の裏面側の最外部の端面電極の幅
と同じかまたは大きいランド幅を有するように多連チッ
プ抵抗器を実装する実装基板を構成したものである。
Further, the multiple chip resistors are mounted so as to have a land width equal to or larger than the width of the outermost end face electrode on the back surface side of the end face electrodes with respect to the longitudinal direction of the insulating substrate of the multiple face chip resistors. The mounting board is configured as follows.

【0009】[0009]

【発明の実施の形態】本発明の請求項1記載の発明は、
矩形状の絶縁基板と、前記絶縁基板の上面に設けられた
複数個の抵抗体と、前記複数個の抵抗体のそれぞれから
導出されかつ電気的に接続するように前記絶縁基板の上
面から裏面にかけて設けられた端面電極とを備えた多連
チップ抵抗器において、前記絶縁基板の長手方向に対し
て前記端面電極の上面側の幅は等ピッチでかつ裏面側の
幅は最外部が中央部に対して1.3〜1.6倍としたも
のである。
BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention is
A rectangular insulating substrate, a plurality of resistors provided on the upper surface of the insulating substrate, and from the upper surface to the back surface of the insulating substrate so as to be derived from and electrically connected to each of the plurality of resistors. In a multiple chip resistor having an end face electrode provided, the width of the upper face side of the end face electrode is equal pitch with respect to the longitudinal direction of the insulating substrate, and the width of the rear face side is the outermost part with respect to the central part. 1.3 to 1.6 times.

【0010】また、請求項2に記載の発明は、請求項1
記載の発明に、絶縁基板の上面に設けられた端面電極間
に、前記絶縁基板の端部から中央部に向かって矩形状の
凹部を有しかつ前記凹部の頂部は丸みを備えたものであ
る。
[0010] The invention described in claim 2 is the same as the claim 1.
In the invention described above, between the end face electrodes provided on the upper surface of the insulating substrate, a rectangular recess is provided from the end of the insulating substrate toward the center, and the top of the recess is rounded. .

【0011】また、請求項3に記載の発明は、請求項2
記載の発明に、絶縁基板の上面の対向する凹部の頂部と
等しいかまたは前記凹部の頂部より端面側に広げた保護
膜を備えたものである。
The invention described in claim 3 is the same as the claim 2
The invention described above is provided with a protective film that is equal to or apex to the tops of the recesses facing each other on the upper surface of the insulating substrate or that is widened toward the end face side from the tops of the recesses.

【0012】また、請求項4に記載の発明は、少なくと
も絶縁基板の長手方向に対して上面側電極の幅は等ピッ
チでかつ裏面側の幅は最外部が1.3〜1.6倍の端面
電極を有する多連チップ抵抗器と、前記多連チップ抵抗
器の前記端面電極の裏面側の最外部の端面電極の幅と同
じかまたは大きいランド幅を有する多連チップ抵抗器を
実装する実装基板とからなるものである。
Further, in the invention according to claim 4, the widths of the electrodes on the upper surface side are equal pitches and the widths on the back surface side are 1.3 to 1.6 times at the outermost portion at least with respect to the longitudinal direction of the insulating substrate. Mounting for mounting a multiple chip resistor having an end surface electrode and a multiple chip resistor having a land width equal to or larger than the width of the outermost end surface electrode on the back surface side of the end surface electrode of the multiple chip resistor It is composed of a substrate.

【0013】以下、本発明の一実施の形態について、図
面を参照しながら説明する。図1は本発明の一実施の形
態における多連チップ抵抗器の切り欠き上面図、図2は
同裏面図、図3は同断面図である。図において、11は
96%アルミナまたはガラスセラミック等のいずれかか
らなる矩形状の絶縁基板である。12は絶縁基板11の
長手方向に絶縁基板11の端部から中央部に向かって設
けられた矩形状の凹部で、この凹部12の頂部12aは
丸みを有している。13a〜13d、14a〜14d、
15a〜15dは4個の上面側端面電極、端面側端面電
極および裏面側端面電極で、絶縁基板11の長手方向の
凹部12を有しない領域の絶縁基板11の上面から裏面
にかけて設けられ、上面側および裏面側は金、銀、銅、
銀パラジウム等のいずれかを主成分とし、端面側はニッ
ケル系の導電性樹脂材料または銀、銀パラジウム等のい
ずれかを主成分とするものからなり、上面側端面電極1
3a〜13dはそれぞれ絶縁基板11の長手方向の幅は
等ピッチで、裏面側端面電極15a〜15dは最外部の
裏面側端面電極15a,15dは中央部の裏面側端面電
極15b,15cより1.3〜1.6倍の幅を有するも
のである。16は絶縁基板11の長手方向の対向する上
面側端面電極13a〜13dを跨ぎかつ電気的に接続す
るように設けられた酸化ルテニウム等からなる抵抗体で
ある。17は少なくとも抵抗体16を覆うように設けら
れたガラス等からなるプリコートガラス層である。18
は絶縁基板11の上面に対向する凹部12の頂部12a
と等しいかもしくは凹部12の頂部12aより絶縁基板
11の端面側に広げたエポキシ系の樹脂またはガラス等
を主成分とする保護膜である。
An embodiment of the present invention will be described below with reference to the drawings. 1 is a cutaway top view of a multiple chip resistor according to an embodiment of the present invention, FIG. 2 is a rear view of the same, and FIG. 3 is a sectional view thereof. In the figure, 11 is a rectangular insulating substrate made of 96% alumina or glass ceramic. Reference numeral 12 denotes a rectangular concave portion provided in the longitudinal direction of the insulating substrate 11 from the end portion of the insulating substrate 11 toward the central portion thereof. The top portion 12a of the concave portion 12 has a roundness. 13a to 13d, 14a to 14d,
15a to 15d are four upper surface side end surface electrodes, an end surface side end surface electrode and a rear surface side end surface electrode, which are provided from the upper surface to the rear surface of the insulating substrate 11 in a region having no recess 12 in the longitudinal direction of the insulating substrate 11. And the back side is gold, silver, copper,
The upper surface side end surface electrode 1 is made of silver palladium or the like as a main component, and the end face side is made of a nickel-based conductive resin material or silver, silver palladium or the like as a main component.
3a to 13d have equal widths in the longitudinal direction of the insulating substrate 11, and the rear surface side end surface electrodes 15a to 15d are the outermost rear surface side end surface electrodes 15a and 15d from the central rear surface side end surface electrodes 15b and 15c. It has a width of 3 to 1.6 times. Reference numeral 16 is a resistor made of ruthenium oxide or the like which is provided so as to straddle and electrically connect the upper surface side end surface electrodes 13a to 13d facing each other in the longitudinal direction of the insulating substrate 11. Reference numeral 17 is a pre-coated glass layer made of glass or the like provided so as to cover at least the resistor 16. 18
Is the top 12a of the recess 12 facing the upper surface of the insulating substrate 11.
Or a protective film containing epoxy resin, glass, or the like as a main component, which is spread from the top 12a of the recess 12 toward the end surface of the insulating substrate 11.

【0014】以上のように構成された本発明の一実施の
形態における多連チップ抵抗器の製造方法について、以
下に図面を参照しながら説明する。
A method of manufacturing the multiple chip resistor according to the embodiment of the present invention configured as described above will be described below with reference to the drawings.

【0015】図4、図5、図6は本発明の一実施の形態
における多連チップ抵抗器の工程図である。
FIG. 4, FIG. 5 and FIG. 6 are process diagrams of a multiple chip resistor in one embodiment of the present invention.

【0016】まず、図4(a)に示すように、長手方向
に凹部21を有しかつこの凹部21の頂部21aに丸み
を有する96%アルミナからなる絶縁基板22の裏面
に、銀を主成分とするペーストをスクリーン印刷した
後、約850℃で焼成して裏面側端面電極23a〜23
dを形成する。この際、最外部の裏面側端面電極23
a,23dは、中央部の裏面側端面電極23b,23c
より絶縁基板22の長手方向の幅が1.3〜1.6倍の
幅を有するように形成されている。
First, as shown in FIG. 4A, silver is the main component on the back surface of an insulating substrate 22 made of 96% alumina having a recess 21 in the longitudinal direction and a rounded top 21a of the recess 21. After screen-printing the paste to be burned at about 850 ° C., the back side end face electrodes 23a-23
forming d. At this time, the outermost back surface side end surface electrode 23
a and 23d are rear surface side end face electrodes 23b and 23c of the central portion.
The width of the insulating substrate 22 in the longitudinal direction is 1.3 to 1.6 times as wide.

【0017】次に、図4(b)に示すように、絶縁基板
22の上面に、銀を主成分とするペーストをスクリーン
印刷した後、約850℃で焼成して上面側端面電極24
a〜24dを形成する。この際、上面側端面電極24a
〜24dは、絶縁基板22の長手方向に対して等ピッチ
の幅を有するように形成されている。
Next, as shown in FIG. 4B, a paste containing silver as a main component is screen-printed on the upper surface of the insulating substrate 22 and then baked at about 850.degree.
a to 24d are formed. At this time, the upper surface side end surface electrode 24a
24d are formed to have an equal pitch width in the longitudinal direction of the insulating substrate 22.

【0018】次に、図4(c)に示すように、絶縁基板
22の上面の対向する上面側端面電極24a〜24dを
跨ぐように酸化ルテニウムからなるペーストをスクリー
ン印刷した後、約850℃で焼成して4個の抵抗体25
を形成する。
Next, as shown in FIG. 4C, a paste made of ruthenium oxide is screen-printed so as to straddle the opposing upper surface side end surface electrodes 24a to 24d on the upper surface of the insulating substrate 22, and then at about 850 ° C. 4 resistors 25 after firing
To form

【0019】次に、図5(a)に示すように、少なくと
も4個の抵抗体25を覆うようにガラスペーストをスク
リーン印刷した後、約600℃で焼成してプリコートガ
ラス層26を形成する。
Next, as shown in FIG. 5A, a glass paste is screen-printed so as to cover at least four resistors 25 and then baked at about 600 ° C. to form a pre-coated glass layer 26.

【0020】次に、図5(b)に示すように、所望の抵
抗値を得るためレーザーにより溝切り27して抵抗値修
正を行う。
Next, as shown in FIG. 5B, a groove is cut 27 by a laser to obtain a desired resistance value, and the resistance value is corrected.

【0021】次に、図5(c)に示すように、絶縁基板
22の上面に対向する凹部21の頂部21aと等しいか
もしくは凹部21の頂部21aより端面側に広げて、エ
ポキシ系の絶縁性樹脂を主成分とするペーストをスクリ
ーン印刷した後、約200℃で硬化して保護膜28を形
成する。
Next, as shown in FIG. 5 (c), the epoxy-based insulating property is equal to the top 21a of the recess 21 facing the upper surface of the insulating substrate 22 or is wider than the top 21a of the recess 21 toward the end face. After screen-printing a paste containing a resin as a main component, it is cured at about 200 ° C. to form a protective film 28.

【0022】次に、図6(a)に示すように、絶縁基板
22の長手方向で一次基板分割をする。
Next, as shown in FIG. 6A, the primary substrate is divided in the longitudinal direction of the insulating substrate 22.

【0023】次に、図6(b)に示すように、絶縁基板
22の端面側に上面側端面電極24a〜24dおよび裏
面側端面電極23a〜23dと電気的に接続するよう
に、ニッケル系の導電性樹脂を主成分とするペーストを
ローラーで塗布した後、約200℃で硬化して端面側端
面電極29a〜29dを形成する。
Next, as shown in FIG. 6B, a nickel-based material is used to electrically connect the upper surface side end surface electrodes 24a to 24d and the rear surface side end surface electrodes 23a to 23d to the end surface side of the insulating substrate 22. After applying a paste containing a conductive resin as a main component with a roller, the paste is cured at about 200 ° C. to form the end face side end face electrodes 29a to 29d.

【0024】次に、図6(c)に示すように、絶縁基板
22の凹部21を形成していない対向する面で二次基板
分割をする。
Next, as shown in FIG. 6 (c), the secondary substrate is divided at the opposing surfaces of the insulating substrate 22 on which the concave portions 21 are not formed.

【0025】最後に、図6(d)に示すように、上面側
端面電極24a〜24d、端面側端面電極29a〜29
dおよび裏面側端面電極23a〜23dを覆うようにニ
ッケルめっきを施し、その後ニッケルめっき(図示せ
ず)を覆うようにはんだめっき30を施して、多連チッ
プ抵抗器を製造するものである。
Finally, as shown in FIG. 6D, the upper surface side end surface electrodes 24a to 24d and the upper surface side end surface electrodes 29a to 29 are formed.
d is plated with nickel so as to cover the end electrodes 23a to 23d on the back side and the solder plating 30 is then coated so as to cover the nickel plating (not shown) to manufacture a multiple chip resistor.

【0026】なお、本発明は、本実施の形態における製
造方法にのみで説明した製造方法に限定されるものでは
ない。
The present invention is not limited to the manufacturing method described only in the manufacturing method of the present embodiment.

【0027】また、本一実施の形態で、最外部の裏面側
端面電極15a,15dは中央部の裏面側端面電極15
b,15cより1.3倍〜1.6倍の幅とした理由は以
下の通りである。従来の多連チップ抵抗器は、凹部の形
状が真円状であった上、4隅部分にも凹部を形成してい
たために、最外部の裏面側端面電極を中央部の裏面側端
面電極の1.3倍以上で形成すると、当然のことながら
凹部間が狭くなり、そこで分断が多発していた。しか
し、本実施の形態の多連チップ抵抗器は、凹部12を矩
形状とし、4隅部分には凹部を形成していないことか
ら、凹部12間を広くとれ、最外部の裏面側端面電極1
5a,15dを中央部の裏面側端面電極15b,15c
の1.3倍以上の幅で形成しても、凹部12間での分断
の発生率を増加させることなく、従来よりセルフアライ
メント効果を大きくすることが可能となる。なお、1.
6倍以上にすることは絶縁基板11作製上、物理的に不
可能である。
Further, in the present embodiment, the outermost back surface side end surface electrodes 15a and 15d are the back surface side end surface electrodes 15 in the central portion.
The reason why the width is 1.3 to 1.6 times wider than that of b and 15c is as follows. In the conventional multiple chip resistors, the shape of the recess is a perfect circle, and the recesses are formed at the four corners as well. Therefore, the outermost back surface side end electrode is the central back surface side end surface electrode. If it is formed by 1.3 times or more, the space between the concave portions is naturally narrowed, and the division frequently occurs there. However, in the multiple chip resistor according to the present embodiment, since the recesses 12 are rectangular and the recesses are not formed at the four corners, the recesses 12 can be widened and the outermost back surface side end surface electrode 1 can be formed.
5a and 15d are the end face electrodes 15b and 15c on the back side of the central portion.
Even if the width is 1.3 times or more, it is possible to increase the self-alignment effect as compared with the prior art without increasing the incidence of division between the recesses 12. In addition, 1.
It is physically impossible to make the number 6 times or more in terms of manufacturing the insulating substrate 11.

【0028】以下に本一実施の形態で説明した多連チッ
プ抵抗器を作製し、従来の形態の多連チップ抵抗器とセ
ルフアライメント効果を測定した結果を(表1)に示
す。測定方法として、最外部の裏面側端面電極15a,
15dが中央部の裏面側端面電極15b,15cの1.
1〜1.6倍の幅の多連チップ抵抗器を試作し、それを
それぞれ実装基板の正規の位置から0.05mm、0.
10mmおよび0.15mmずらして実装を行った。
The results of measuring the self-alignment effect with the conventional multiple chip resistors produced in the multiple chip resistors described in the present embodiment are shown in Table 1 below. As the measuring method, the outermost back surface side end surface electrode 15a,
15d is one of the back surface side end surface electrodes 15b and 15c in the central part.
A multi-chip resistor having a width of 1 to 1.6 times was prototyped, and each of them was mounted on a mounting board at a position of 0.05 mm, 0.
Mounting was performed by shifting by 10 mm and 0.15 mm.

【0029】[0029]

【表1】 [Table 1]

【0030】(表1)より、本発明は大きなセルフアラ
イメント効果を有し、高い実装性を誇ることがわかる。
From Table 1, it can be seen that the present invention has a large self-alignment effect and boasts high mountability.

【0031】以上のように構成、製造された本発明の一
実施の形態における多連チップ抵抗器について、以下に
その使用例を説明する。
An example of use of the multiple chip resistor having the above structure and manufactured according to the embodiment of the present invention will be described below.

【0032】図7は本発明の一実施の形態における多連
チップ抵抗器の使用例を示す図である。図において、4
1は上述した多連チップ抵抗器42を実装するための実
装基板である。この実装基板41は、多連チップ抵抗器
42の裏面側端面電極(図示せず)に対応したランド4
3に接続され、この際、少なくとも最外部の裏面側端面
電極は、この裏面側端面電極の幅より大きいランド44
に実装されるものである。
FIG. 7 is a diagram showing an example of use of the multiple chip resistors in one embodiment of the present invention. In the figure, 4
Reference numeral 1 is a mounting board for mounting the multiple chip resistor 42 described above. The mounting substrate 41 includes a land 4 corresponding to an end surface electrode (not shown) on the back surface side of the multiple chip resistor 42.
3 and at least the outermost back surface side end surface electrode is larger than the width of this back surface side end surface electrode.
Will be implemented in.

【0033】このように、少なくとも裏面側端面電極の
幅より大きいランド44を設けることにより、実装ズレ
が生じた場合のセルフアライメント効果の点で有利であ
る。
As described above, by providing the lands 44 at least larger than the width of the back surface side end surface electrode, it is advantageous in terms of the self-alignment effect when the mounting deviation occurs.

【0034】なお、ランド44は多連チップ抵抗器42
の裏面側端面電極の幅より大きくしたが、同じでもよ
い。
The land 44 is a multiple chip resistor 42.
Although the width is larger than the width of the back surface side end surface electrode of the above, it may be the same.

【0035】[0035]

【発明の効果】以上のように本発明によれば、次の有利
な効果が得られる。
As described above, according to the present invention, the following advantageous effects can be obtained.

【0036】(1)多連チップ抵抗器の絶縁基板の長手
方向に対して端面電極の裏面側の幅は最外部が中央部に
対して1.3倍〜1.6倍となるように構成しかつ多連
チップ抵抗器の絶縁基板の長手方向に対しての端面電極
の裏面側の最外部の端面電極の幅と同じかまたは大きい
ランド幅を有するように構成することにより、裏面側端
面電極の幅と、それを実装する実装基板のランドの幅の
重なりが大きいため、表面張力が強く働き、セルフアラ
イメント効果が大きくなる。
(1) The width of the rear surface side of the end face electrode in the longitudinal direction of the insulating substrate of the multiple chip resistor is 1.3 to 1.6 times the outermost part of the central part. And has a land width equal to or larger than the width of the outermost end face electrode on the back face side of the end face electrode with respect to the longitudinal direction of the insulating substrate of the multiple chip resistor. And the width of the land of the mounting substrate on which it is mounted are large, so that the surface tension is strong and the self-alignment effect is large.

【0037】(2)多連チップ抵抗器の端面電極間に、
絶縁基板の端部から中央部に向かって矩形状の凹部を備
えたことにより、多連チップ抵抗器の絶縁基板の長手方
向に対して端面電極の裏面側の幅は最外部が中央部に対
して1.3倍〜1.6倍とすることが可能となる。ま
た、凹部の頂部は丸みを備えることにより、凹部形成時
のストレスによりクラックを防止でき、製品強度が向上
する。
(2) Between the end face electrodes of the multiple chip resistor,
Since the rectangular concave portion is provided from the end of the insulating substrate toward the center, the width of the back surface side of the end face electrode with respect to the longitudinal direction of the insulating substrate of the multiple chip resistor is the outermost part with respect to the central part. It is possible to increase 1.3 times to 1.6 times. Moreover, since the top of the recess is rounded, cracks can be prevented due to stress during formation of the recess, and the product strength is improved.

【0038】(3)多連チップ抵抗器の絶縁基板の上面
に対向する凹部の頂部と等しいかまたは凹部の頂部より
端面側に広げた保護膜を備えることにより、端子間のマ
イグレーションを防止できる。
(3) Migration between terminals can be prevented by providing a protective film which is equal to the top of the recess facing the upper surface of the insulating substrate of the multiple chip resistor or which is widened toward the end face side from the top of the recess.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施の形態における多連チップ抵抗
器の切り欠き上面図
FIG. 1 is a cutaway top view of a multiple chip resistor according to an embodiment of the present invention.

【図2】同裏面図[Fig. 2] Rear view of the same

【図3】同断面図FIG. 3 is a sectional view of the same.

【図4】同工程図[Fig. 4]

【図5】同工程図[Fig. 5]

【図6】同工程図FIG. 6

【図7】同使用例を示す図FIG. 7 is a diagram showing the same usage example.

【図8】従来の多連チップ抵抗器の上面図FIG. 8 is a top view of a conventional multiple chip resistor.

【符号の説明】[Explanation of symbols]

11 絶縁基板 12 凹部 12a 頂部 13a〜13d 上面側端面電極 14a〜14d 端面側端面電極 15a〜15d 裏面側端面電極 16 抵抗体 17 プリコートガラス層 18 保護膜 11 Insulating Substrate 12 Recess 12a Top 13a to 13d Top Surface End Electrode 14a to 14d End Surface End Electrode 15a to 15d Back Side End Electrode 16 Resistor 17 Precoat Glass Layer 18 Protective Film

───────────────────────────────────────────────────── フロントページの続き (72)発明者 川端 統夫 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 福岡 章夫 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Norio Kawabata 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Akio Fukuoka, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 矩形状の絶縁基板と、前記絶縁基板の上
面に設けられた複数個の抵抗体と、前記複数個の抵抗体
のそれぞれから導出されかつ電気的に接続するように前
記絶縁基板の上面から裏面にかけて設けられた端面電極
とを備えた多連チップ抵抗器において、前記絶縁基板の
長手方向に対して前記端面電極の上面側の幅は等ピッチ
でかつ裏面側の幅は最外部が中央部に対して1.3〜
1.6倍とした多連チップ抵抗器。
1. A rectangular insulating substrate, a plurality of resistors provided on an upper surface of the insulating substrate, and the insulating substrate which is derived from and electrically connected to each of the plurality of resistors. In a multiple chip resistor having an end surface electrode provided from the upper surface to the back surface of the end surface electrode, the width of the end surface electrode on the upper surface side is equal pitch and the width on the back surface side is outermost with respect to the longitudinal direction of the insulating substrate. Is 1.3 to the center
Multiple chip resistor with 1.6 times.
【請求項2】 端面電極間に、前記絶縁基板の端部から
中央部に向かって矩形状の凹部を有しかつ前記凹部の頂
部は丸みを備えた請求項1記載の多連チップ抵抗器。
2. The multiple chip resistor according to claim 1, wherein between the end face electrodes, a rectangular recess is provided from the end of the insulating substrate toward the center, and the top of the recess is rounded.
【請求項3】 絶縁基板の上面の対向する凹部の頂部と
等しいかまたは前記凹部の頂部より端面側に広げた保護
膜を備えた請求項2記載の多連チップ抵抗器。
3. The multiple chip resistor according to claim 2, further comprising a protective film which is equal to or apex to the tops of the recesses facing each other on the upper surface of the insulating substrate, and which is widened toward the end face side from the tops of the recesses.
【請求項4】 少なくとも絶縁基板の長手方向に対して
上面側電極の幅は等ピッチでかつ裏面側の幅は最外部が
1.3〜1.6倍の端面電極を有する多連チップ抵抗器
と、前記多連チップ抵抗器の前記端面電極の裏面側の最
外部の端面電極の幅と同じかまたは大きいランド幅を有
する多連チップ抵抗器を実装する実装基板。
4. A multiple chip resistor having an end face electrode in which the widths of the upper surface side electrodes are at equal pitches at least with respect to the longitudinal direction of the insulating substrate, and the outermost width of the rear surface side is 1.3 to 1.6 times. And a mounting substrate for mounting a multiple chip resistor having a land width equal to or larger than the width of the outermost end face electrode on the back surface side of the end face electrode of the multiple chip resistor.
JP00634496A 1996-01-18 1996-01-18 Multiple chip resistor and mounting board for mounting it Expired - Fee Related JP3557762B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP00634496A JP3557762B2 (en) 1996-01-18 1996-01-18 Multiple chip resistor and mounting board for mounting it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP00634496A JP3557762B2 (en) 1996-01-18 1996-01-18 Multiple chip resistor and mounting board for mounting it

Publications (2)

Publication Number Publication Date
JPH09199301A true JPH09199301A (en) 1997-07-31
JP3557762B2 JP3557762B2 (en) 2004-08-25

Family

ID=11635763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP00634496A Expired - Fee Related JP3557762B2 (en) 1996-01-18 1996-01-18 Multiple chip resistor and mounting board for mounting it

Country Status (1)

Country Link
JP (1) JP3557762B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043717A (en) * 2000-07-28 2002-02-08 Matsushita Electric Ind Co Ltd Electronic parts and its manufacturing method
JP2008034671A (en) * 2006-07-31 2008-02-14 Yamaha Motor Co Ltd Wiring board and saddle riding vehicle provided with the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043717A (en) * 2000-07-28 2002-02-08 Matsushita Electric Ind Co Ltd Electronic parts and its manufacturing method
JP4547781B2 (en) * 2000-07-28 2010-09-22 パナソニック株式会社 Method for manufacturing multiple chip resistors
JP2008034671A (en) * 2006-07-31 2008-02-14 Yamaha Motor Co Ltd Wiring board and saddle riding vehicle provided with the same

Also Published As

Publication number Publication date
JP3557762B2 (en) 2004-08-25

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