JPH0864403A - Square chip resistor with circuit inspection terminal - Google Patents
Square chip resistor with circuit inspection terminalInfo
- Publication number
- JPH0864403A JPH0864403A JP6201992A JP20199294A JPH0864403A JP H0864403 A JPH0864403 A JP H0864403A JP 6201992 A JP6201992 A JP 6201992A JP 20199294 A JP20199294 A JP 20199294A JP H0864403 A JPH0864403 A JP H0864403A
- Authority
- JP
- Japan
- Prior art keywords
- surface electrode
- electrode layer
- layer
- chip resistor
- circuit inspection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Measuring Leads Or Probes (AREA)
- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高密度配線回路に用い
られる回路検査端子付き角形チップ抵抗器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rectangular chip resistor with a circuit inspection terminal used in a high-density wiring circuit.
【０００２】[0002]
【従来の技術】近年、電子機器の軽薄短小化に対する要
求がますます増大していく中、回路基板の配線密度を高
めるため、抵抗素子には非常に小型な抵抗器が多く用い
られるようになってきた。2. Description of the Related Art In recent years, with the ever-increasing demand for smaller, lighter, smaller electronic devices, very small resistors are often used as resistive elements in order to increase the wiring density of circuit boards. Came.
【０００３】一方、角形チップ抵抗器等の電子部品をプ
リント基板に実装した後には、プリント基板上に設けた
回路チェック用のランドパターンに回路チェック用の検
針を接触させ、回路の動作チェックを行うことが一般的
である。On the other hand, after the electronic components such as the rectangular chip resistors are mounted on the printed board, the circuit check meter is brought into contact with the circuit check land pattern provided on the printed board to check the operation of the circuit. Is common.
【０００４】以下に従来の角形チップ抵抗器について説
明する。図４は従来の角形チップ抵抗器の構成を示す平
面図（ａ）と断面図（ｂ）である。図４において、１は
セラミック基板、２は一対の上面電極層、３はセラミッ
ク基板１上に上面電極層２の一部に重なるように焼成、
形成された抵抗層である。４はセラミック基板１の端面
に上面電極層２の一部に重なるように焼成、形成された
側面電極層、５は抵抗層３を完全に覆うように焼成、形
成された保護層である。このように構成された角形チッ
プ抵抗器はプリント基板に実装され、別に、前記プリン
ト基板上に回路チェック用のランドパターン（図示せ
ず）が設けられている。A conventional rectangular chip resistor will be described below. FIG. 4 is a plan view (a) and a sectional view (b) showing a configuration of a conventional rectangular chip resistor. In FIG. 4, 1 is a ceramic substrate, 2 is a pair of upper surface electrode layers, and 3 is fired on the ceramic substrate 1 so as to overlap a part of the upper surface electrode layer 2,
The formed resistance layer. Reference numeral 4 is a side surface electrode layer formed by firing so as to overlap with a part of the upper surface electrode layer 2 on the end surface of the ceramic substrate 1, and reference numeral 5 is a protective layer formed by baking so as to completely cover the resistance layer 3. The rectangular chip resistor configured as described above is mounted on a printed circuit board, and a land pattern (not shown) for circuit check is separately provided on the printed circuit board.
【０００５】以上のように構成された角形チップ抵抗器
を実装したプリント基板の回路チェックは、ランドパタ
ーンに回路チェック用の検針を接触させ回路の動作チェ
ックをする。In the circuit check of the printed circuit board on which the rectangular chip resistor having the above-mentioned structure is mounted, a circuit check meter is brought into contact with the land pattern to check the operation of the circuit.
【０００６】さらに、ここ数年で部品の実装密度は１０
０５サイズの部品等の登場で飛躍的に高まりつつある
が、前記回路チェック用のランドパターンさえも無くし
たいという要望が高まりつつある。Furthermore, the mounting density of parts has been 10 in the last few years.
With the advent of 05-size parts and the like, the number is rapidly increasing, but there is also a growing demand for eliminating even the circuit check land pattern.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら従来の構
成では、角形チップ抵抗器の上面部分（あるいは裏面電
極）の電極面積が小さく（特に高実装密度が要求される
回路に多数用いられる１００５サイズ角形チップ抵抗器
では）、プリント基板上のランドパターンの代わりに上
面部分の電極をチェック端子とするには不可能であっ
た。However, in the conventional configuration, the electrode area of the upper surface portion (or the rear surface electrode) of the rectangular chip resistor is small (especially the 1005 size rectangular chip used in many circuits requiring high packaging density). It was impossible to use the electrodes on the upper surface as a check terminal instead of the land pattern on the printed circuit board.
【０００８】本発明は上記従来の問題点を解決するもの
で、微細角形チップ抵抗器でもチェック端子として使用
可能な回路検査端子付き角形チップ抵抗器を提供するこ
とを目的とする。The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a rectangular chip resistor with a circuit inspection terminal that can be used as a check terminal even in a fine rectangular chip resistor.
【０００９】[0009]
【課題を解決するための手段】この目的を達成するため
に本発明の回路検査端子付き角形チップ抵抗器は、絶縁
性の角板形のセラミック基板と、前記セラミック基板上
の長手方向に形成された一対の第１上面電極層と、前記
一対の第１上面電極層の一部に重なる抵抗層と、前記抵
抗層を完全に覆う保護層と、前記保護層の面積の半分以
上を覆いかつ前記第１上面電極層の何れか片方と導通す
る第２上面電極層と、前記第１上面電極層の一部に重な
る一対の側面電極層とを備えた構成とするか、絶縁性の
角板形のセラミック基板と、前記セラミック基板上の長
手方向に形成された一対の上面電極層と、前記一対の上
面電極層の一部に重なる抵抗層と、前記抵抗層を完全に
覆う保護層と、前記上面電極層の一部に重なる一対の側
面電極層と、前記上面電極層の形成された面の裏面上で
前記裏面の面積の半分以上を覆いかつ前記一対の側面電
極層の何れか一方と導通する裏面電極層とを備えた構成
としたものである。To achieve this object, a rectangular chip resistor with a circuit inspection terminal of the present invention is formed of an insulating rectangular plate-shaped ceramic substrate and a longitudinal direction on the ceramic substrate. A pair of first upper surface electrode layers, a resistance layer that partially overlaps the pair of first upper surface electrode layers, a protection layer that completely covers the resistance layer, and a half or more of the area of the protection layer and A second upper surface electrode layer that is electrically connected to any one of the first upper surface electrode layers, and a pair of side surface electrode layers that overlap a part of the first upper surface electrode layer, or an insulating rectangular plate shape. A ceramic substrate, a pair of upper surface electrode layers formed in the longitudinal direction on the ceramic substrate, a resistance layer that partially overlaps the pair of upper surface electrode layers, a protective layer that completely covers the resistance layer, A pair of side surface electrode layers overlapping a part of the upper surface electrode layer, and Is on the back surface of the formed surface of the surface electrode layer which has a configuration that includes a back electrode layer electrically connected to one of the rear surface of the cover more than half of the area and the pair of side electrode layers.
【００１０】[0010]
【作用】この構成によって、微細角形チップ抵抗器の上
面部分あるいは裏面部分に大きな面積のチェック端子が
設けられることになり、プリント基板上のチェック用ラ
ンドパターンの代わりに使用することができる。With this structure, a check terminal having a large area is provided on the upper surface portion or the back surface portion of the fine rectangular chip resistor, which can be used in place of the check land pattern on the printed board.
【００１１】[0011]
（実施例１）以下、本発明の第１の実施例について図面
を参照しながら説明する。なお、従来例と同一構成部品
には同じ符号で示し説明は省略する。(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The same components as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.
【００１２】図１に示すように、本発明の回路検査端子
付き角形チップ抵抗器の回路検査用の第２上面電極層６
は、セラミック基板１上の銀系厚膜からなる一対の第１
上面電極層２の片方に接続し、保護層５の面積の半分以
上を覆うように構成した。As shown in FIG. 1, the second upper electrode layer 6 for circuit inspection of the rectangular chip resistor with circuit inspection terminals of the present invention.
Is a pair of first thick silver-based films on the ceramic substrate 1.
It was connected to one side of the upper surface electrode layer 2 so as to cover more than half of the area of the protective layer 5.
【００１３】次に、本実施例における回路検査端子付き
角形チップ抵抗器の製造方法について説明する。まず、
耐熱性および絶縁性に優れたシート状のセラミック基板
１を用意する。このシート状のセラミック基板１には短
冊状および個片状に分割するための溝（グリーンシート
時に金型成形）が形成されている。次に、シート状のセ
ラミック基板１の表面に厚膜銀ペーストをスクリーン印
刷・乾燥し、ベルト式連続焼成炉によって８５０℃の温
度で、ピーク時間６分、ＩＮ−ＯＵＴ ４５分のプロフ
ァイルによって焼成し第１上面電極層２を形成した。次
に、第１上面電極層２の一部に重なるように、ＲｕＯ2
を主成分とする厚膜抵抗ペーストをスクリーン印刷し、
ベルト式連続焼成炉により８５０℃の温度でピーク時間
６分、ＩＮ−ＯＵＴ時間４５分のプロファイルによって
焼成し、抵抗層３を形成した。次に、第１上面電極層２
間の抵抗層３の抵抗値を揃えるために、レーザー光によ
って、抵抗層３の一部を破壊し抵抗値修正（Ｌカット）
を行った。続いて、抵抗層３を完全に覆うように、ホウ
ケイ酸鉛系ガラスペーストをスクリーン印刷し、ベルト
式連続焼成炉によって５９０℃の温度で、ピーク時間６
分、ＩＮ−ＯＵＴ５０分の焼成プロファイルによって焼
成し、保護層５を形成した。次に、側面電極を形成する
ための準備工程として、側面電極を露出させるために、
シート状のセラミック基板１を短冊状に分割し、短冊状
のセラミック基板１を得た。短冊状セラミック基板１の
側面に、上面電極層２の一部に重なるように厚膜銀ペー
ストをローラーによって塗布し、ベルト式連続焼成炉に
よって６００℃の温度で、ピーク時間６分、ＩＮ−ＯＵ
Ｔ ４５分の焼成プロファイルによって焼成し側面電極
層４を形成した。Next, a method of manufacturing the rectangular chip resistor with the circuit inspection terminal in this embodiment will be described. First,
A sheet-shaped ceramic substrate 1 having excellent heat resistance and insulation is prepared. The sheet-shaped ceramic substrate 1 is provided with grooves (molding at the time of green sheet) for dividing into strips and individual pieces. Next, a thick film silver paste is screen-printed and dried on the surface of the sheet-shaped ceramic substrate 1, and fired in a belt type continuous firing furnace at a temperature of 850 ° C. for a peak time of 6 minutes and IN-OUT 45 minutes profile. The first upper surface electrode layer 2 was formed. Next, RuO 2 is formed so as to partially overlap the first upper surface electrode layer 2.
Screen printing thick film resistor paste with
The resistance layer 3 was formed by firing in a belt type continuous firing furnace at a temperature of 850 ° C. with a profile having a peak time of 6 minutes and an IN-OUT time of 45 minutes. Next, the first upper electrode layer 2
In order to equalize the resistance value of the resistance layer 3 between them, a part of the resistance layer 3 is destroyed by laser light and the resistance value is corrected (L cut).
I went. Subsequently, a lead borosilicate glass paste was screen-printed so as to completely cover the resistance layer 3, and the belt type continuous firing furnace was used at a temperature of 590 ° C. for a peak time of 6 hours.
Minute, and the protective layer 5 was formed by firing with a firing profile of 50 minutes for IN-OUT. Next, as a preparatory step for forming the side surface electrode, in order to expose the side surface electrode,
The sheet-shaped ceramic substrate 1 was divided into strips to obtain strip-shaped ceramic substrates 1. A thick film silver paste was applied to the side surface of the strip-shaped ceramic substrate 1 by a roller so as to overlap a part of the upper electrode layer 2, and the belt-type continuous firing furnace was used at a temperature of 600 ° C. for a peak time of 6 minutes and IN-OU.
The side surface electrode layer 4 was formed by firing with a firing profile of T 45 minutes.
【００１４】次に、電極メッキの準備工程として、側面
電極層４を形成済みの短冊状のセラミック基板１を個片
状に分割する二次基板分割を行い、個片状のセラミック
基板１を得た。次に、露出している第１上面電極層２と
側面電極層４上に、電解メッキによってＮｉメッキ層と
はんだメッキ層を形成した。最後に、片方の第１上面電
極層２上のＮｉおよびはんだメッキ層に重なるように、
硬化性の樹脂を含む樹脂銀ペーストをパッド印刷を用い
ることにより印刷し、２００℃３０分の硬化条件にて硬
化し第２上面電極層６を形成した。Next, as a preparatory step for electrode plating, the strip-shaped ceramic substrate 1 on which the side surface electrode layer 4 has been formed is divided into individual secondary substrates to obtain individual ceramic substrates 1. It was Next, a Ni plating layer and a solder plating layer were formed on the exposed first upper surface electrode layer 2 and side surface electrode layer 4 by electrolytic plating. Finally, so as to overlap the Ni and the solder plating layer on one of the first upper surface electrode layers 2,
A resin silver paste containing a curable resin was printed by using pad printing and cured under a curing condition of 200 ° C. for 30 minutes to form the second upper surface electrode layer 6.
【００１５】以上のように構成された回路検査端子付き
角形チップ抵抗器について、図３を用いてその動作を説
明する。回路検査端子付き角形チップ抵抗器の上面部分
に構成された第２上面電極層６を大きな面積を有するチ
ェック端子として、プリント基板上のチェック用ランド
パターンの代わりに使用することができる。The operation of the rectangular chip resistor with circuit inspection terminals constructed as above will be described with reference to FIG. The second upper surface electrode layer 6 formed on the upper surface portion of the rectangular chip resistor with the circuit inspection terminal can be used as a check terminal having a large area instead of the check land pattern on the printed board.
【００１６】以上のように本実施例によれば、角形チッ
プ抵抗器の上面部分に構成した第２上面電極層６をプリ
ント基板上のチェック用ランドパターンの代わりに使用
できるので、チェックランドパターンが不要となり、実
装するプリント基板の実装密度を高めることができる。As described above, according to this embodiment, since the second upper surface electrode layer 6 formed on the upper surface portion of the rectangular chip resistor can be used instead of the check land pattern on the printed board, the check land pattern can be formed. It becomes unnecessary and the mounting density of the printed circuit board to be mounted can be increased.
【００１７】（実施例２）次に、本発明の第２の実施例
について図面を参照しながら説明する。なお、従来例と
同一構成部品には同じ符号で示し説明は省略する。(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to the drawings. The same components as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.
【００１８】図２に示すように、本実施例における回路
検査端子付き角形チップ抵抗器は、セラミック基板１上
の銀系厚膜の一対の上面電極層２の一部に重なるルテニ
ウム系厚膜の抵抗層３を完全に覆う保護層５と、上面電
極層２の一部に重なる銀系厚膜からなる側面電極層４の
片方に接続する回路検査用の裏面電極層７の露出電極面
にＮｉメッキ層とはんだメッキ層を形成した構成となっ
ている。As shown in FIG. 2, the rectangular chip resistor with a circuit inspection terminal according to the present embodiment is a ruthenium-based thick film that overlaps a part of a pair of silver-based thick film upper electrode layers 2 on a ceramic substrate 1. Ni is formed on the exposed electrode surface of the back surface electrode layer 7 for circuit inspection, which is connected to one of the protective layer 5 that completely covers the resistance layer 3 and the side surface electrode layer 4 formed of a silver-based thick film that partially overlaps the top surface electrode layer 2. It has a structure in which a plating layer and a solder plating layer are formed.
【００１９】次に、本実施例における回路検査端子付き
角形チップ抵抗器の製造方法について説明する。まず、
耐熱性および絶縁性に優れたシート状のセラミック基板
１を用意する。このシート状のセラミック基板１には短
冊状および個片状に分割するための溝（グリーンシート
時に金型成形）が形成されている。次に、シート状のセ
ラミック基板１の表面に厚膜銀ペーストをスクリーン印
刷・乾燥し、さらにシート状のセラミック基板１の裏面
上に厚膜銀ペーストをスクリーン印刷・乾燥し、ベルト
式連続焼成炉によって８５０℃の温度で、ピーク時間６
分、ＩＮ−ＯＵＴ ４５分のプロファイルによって焼成
し、上面電極層２および裏面電極層７を形成した。次
に、上面電極層２の一部に重なるように、ＲｕＯ2を主
成分とする厚膜抵抗ペーストをスクリーン印刷し、ベル
ト式連続焼成炉により８５０℃の温度でピーク時間６
分、ＩＮ−ＯＵＴ時間４５分のプロファイルによって焼
成し、抵抗層３を形成した。次に、上面電極層２間の抵
抗層３の抵抗値を揃えるために、レーザー光によって、
抵抗層３の一部を破壊し抵抗値修正（Ｌカット）を行っ
た。続いて、抵抗層３を完全に覆うように、ホウケイ酸
鉛系ガラスペーストをスクリーン印刷し、ベルト式連続
焼成炉によって５９０℃の温度で、ピーク時間６分、Ｉ
Ｎ−ＯＵＴ ５０分の焼成プロファイルによって焼成
し、保護層５を形成した。次に、側面電極層４を形成す
るための準備工程として、側面部分を露出させるため
に、シート状のセラミック基板１を短冊状に分割し、短
冊状のセラミック基板１を得た。短冊状のセラミック基
板１の側面に、上面電極層２の一部に重なるように厚膜
銀ペーストをローラーによって塗布し、ベルト式連続焼
成炉によって６００℃の温度で、ピーク時間６分、ＩＮ
−ＯＵＴ ４５分の焼成プロファイルによって焼成し側
面電極層４を形成した。次に、電極メッキの準備工程と
して、側面電極層４を形成済みの短冊状のセラミック基
板１を個片状に分割する二次基板分割を行い、個片状の
セラミック基板１を得た。最後に、露出している上面電
極層２と側面電極層４上および裏面電極層７上に、電解
メッキによってＮｉメッキ層とはんだメッキ層を形成し
た。Next, a method of manufacturing the rectangular chip resistor with the circuit inspection terminal in this embodiment will be described. First,
A sheet-shaped ceramic substrate 1 having excellent heat resistance and insulation is prepared. The sheet-shaped ceramic substrate 1 is provided with grooves (molding at the time of green sheet) for dividing into strips and individual pieces. Next, the thick film silver paste is screen-printed and dried on the front surface of the sheet-shaped ceramic substrate 1, and the thick-film silver paste is screen-printed and dried on the back surface of the sheet-shaped ceramic substrate 1 in a belt-type continuous firing furnace. At a temperature of 850 ° C with a peak time of 6
And an IN-OUT 45-minute profile, the upper surface electrode layer 2 and the back surface electrode layer 7 were formed. Next, a thick film resistance paste containing RuO 2 as a main component was screen-printed so as to overlap a part of the upper surface electrode layer 2, and a peak time of 6 at a temperature of 850 ° C. in a belt type continuous firing furnace.
And a resistance layer 3 was formed by firing with a profile of 45 minutes and an IN-OUT time of 45 minutes. Next, in order to make the resistance value of the resistance layer 3 between the upper electrode layers 2 uniform,
A part of the resistance layer 3 was destroyed and the resistance value was corrected (L cut). Subsequently, a lead borosilicate glass paste was screen-printed so as to completely cover the resistance layer 3, and the belt type continuous firing furnace was used at a temperature of 590 ° C. for a peak time of 6 minutes and I
The protective layer 5 was formed by firing with a N-OUT 50 minute firing profile. Next, as a preparatory step for forming the side surface electrode layer 4, the sheet-shaped ceramic substrate 1 was divided into strips to obtain the strip-shaped ceramic substrate 1 in order to expose the side surface portion. A thick film silver paste is applied to the side surface of the strip-shaped ceramic substrate 1 by a roller so as to overlap a part of the upper surface electrode layer 2, and the belt type continuous firing furnace is used at a temperature of 600 ° C. for a peak time of 6 minutes and IN.
The side surface electrode layer 4 was formed by firing according to a -OUT 45 minute firing profile. Next, as a preparatory step for electrode plating, a secondary substrate division in which the strip-shaped ceramic substrate 1 on which the side surface electrode layer 4 has been formed is divided into individual pieces is performed to obtain individual piece-shaped ceramic substrates 1. Finally, a Ni plating layer and a solder plating layer were formed by electrolytic plating on the exposed upper surface electrode layer 2, side surface electrode layer 4, and back surface electrode layer 7.
【００２０】以上のように構成された回路検査端子付き
角形チップ抵抗器は、図３に示すように回路検査端子付
き角形チップ抵抗器の裏面部分に構成された裏面電極層
７を大きな面積を有するチェック端子として、プリント
基板上のチェック用ランドパターンの代わりに使用する
ことができる。The rectangular chip resistor with circuit inspection terminal constructed as described above has a large area of the back electrode layer 7 formed on the back surface of the rectangular chip resistor with circuit inspection terminal as shown in FIG. It can be used as a check terminal instead of the check land pattern on the printed circuit board.
【００２１】以上のように本実施例によれば、角形チッ
プ抵抗器の裏面部分に構成した裏面電極層７をプリント
基板上のチェックパターンの代わりに使用できるので、
チェックランドパターンが不要となり、実装するプリン
ト基板の実装密度を高めることができる。As described above, according to this embodiment, the back electrode layer 7 formed on the back surface of the rectangular chip resistor can be used instead of the check pattern on the printed circuit board.
The checkland pattern is not needed, and the mounting density of the printed circuit board to be mounted can be increased.
【００２２】特に第１の実施例の回路検査端子付き角形
チップ抵抗器は回路検査端子として硬度の低い樹脂材料
を用いているため、回路検査時の接触信頼性が向上する
という効果も有する。In particular, the rectangular chip resistor with the circuit inspection terminal of the first embodiment uses the resin material having low hardness as the circuit inspection terminal, so that it also has the effect of improving the contact reliability during the circuit inspection.
【００２３】なお、各実施例では抵抗膜に厚膜の抵抗材
料を用いた厚膜チップ抵抗器に適用したが、薄膜材料を
用いた薄膜チップ抵抗器にも適用できることは言うまで
もない。Although each embodiment is applied to the thick film chip resistor using the thick film resistance material for the resistance film, it is needless to say that it is also applicable to the thin film chip resistor using the thin film material.
【００２４】また、各実施例において、回路検査用の第
２上面電極層または裏面電極層は、セラミック基板の片
面のみに形成したが、セラミック基板の両面に形成する
ことにより、表裏の方向性によらず実装可能となる。Further, in each of the embodiments, the second upper surface electrode layer or the rear surface electrode layer for circuit inspection is formed on only one surface of the ceramic substrate, but by forming it on both surfaces of the ceramic substrate, the directionality of the front and back sides is improved. It can be implemented regardless.
【００２５】[0025]
【発明の効果】以上のように、本発明によれば、回路検
査端子付き角形チップ抵抗器の第１上面電極層および抵
抗層を覆う保護層上に形成した第２上面電極層を、ある
いは回路検査端子付き角形チップ抵抗器の上面電極層の
反対側の裏面電極層を、プリント基板に実装後のチェッ
ク端子として使用することにより、前記プリント基板上
のチェック用ランドパターンが不要となり、実装密度の
高いプリント基板を実現できるものである。As described above, according to the present invention, the second upper surface electrode layer formed on the protective layer covering the first upper surface electrode layer and the resistance layer of the rectangular chip resistor with the circuit inspection terminal, or the circuit. By using the back electrode layer on the opposite side of the top electrode layer of the square chip resistor with the inspection terminal as the check terminal after mounting on the printed circuit board, the check land pattern on the printed circuit board becomes unnecessary and the mounting density can be reduced. A high printed circuit board can be realized.
【図１】（ａ）は本発明の第１の実施例における回路検
査端子付き角形チップ抵抗器の平面図 （ｂ）は同図（ａ）の断面図FIG. 1A is a plan view of a rectangular chip resistor with a circuit inspection terminal according to a first embodiment of the present invention, and FIG. 1B is a sectional view of FIG.
【図２】（ａ）は本発明の第２の実施例における回路検
査端子付き角形チップ抵抗器の平面図 （ｂ）は同図（ａ）の断面図FIG. 2A is a plan view of a rectangular chip resistor with a circuit inspection terminal according to a second embodiment of the present invention, and FIG. 2B is a sectional view of FIG.
【図３】本発明の第１の実施例および第２の実施例にお
ける回路検査端子付き角形チップ抵抗器のプリント基板
上での実装状態を示す斜視図FIG. 3 is a perspective view showing a mounting state of a rectangular chip resistor with a circuit inspection terminal on a printed board according to the first and second embodiments of the present invention.
【図４】（ａ）は従来の角形チップ抵抗器の平面図 （ｂ）は同図（ａ）の断面図FIG. 4A is a plan view of a conventional rectangular chip resistor, and FIG. 4B is a sectional view of FIG.
１ セラミック基板 ２ 第１上面電極層 ３ 抵抗層 ４ 側面電極層 ５ 保護層 ６ 第２上面電極層 ７ 裏面電極層 1 Ceramic Substrate 2 First Top Electrode Layer 3 Resistance Layer 4 Side Electrode Layer 5 Protective Layer 6 Second Top Electrode Layer 7 Back Electrode Layer
Claims (3)
記セラミック基板上の長手方向に形成された一対の第１
上面電極層と、前記一対の第１上面電極層の一部に重な
る抵抗層と、前記抵抗層を完全に覆う保護層と、前記保
護層の面積の半分以上を覆いかつ前記第１上面電極層の
何れか片方と導通する回路検査用の第２上面電極層と、
前記第１上面電極層の一部に重なる一対の側面電極層と
を備えた回路検査端子付き角形チップ抵抗器。1. An insulative rectangular plate-shaped ceramic substrate, and a pair of first first members formed in the longitudinal direction on the ceramic substrate.
A top surface electrode layer, a resistance layer that partially overlaps the pair of first top surface electrode layers, a protection layer that completely covers the resistance layer, and a first top surface electrode layer that covers at least half the area of the protection layer A second upper surface electrode layer for circuit inspection, which is electrically connected to any one of
A rectangular chip resistor with a circuit inspection terminal, comprising a pair of side surface electrode layers overlapping a part of the first upper surface electrode layer.
電極ペーストを印刷・硬化させることにより形成したこ
とを特徴とする請求項１記載の回路検査端子付き角形チ
ップ抵抗器。2. The rectangular chip resistor with a circuit inspection terminal according to claim 1, wherein the second upper surface electrode layer is formed by printing and curing an electrode paste containing a curable resin.
記セラミック基板上の長手方向に形成された一対の上面
電極層と、前記一対の上面電極層の一部に重なる抵抗層
と、前記抵抗層を完全に覆う保護層と、前記上面電極層
の一部に重なる一対の側面電極層と、前記上面電極層の
形成された面の裏面上で前記裏面の面積の半分以上を覆
いかつ前記一対の側面電極層の何れか一方と導通する回
路検査用の裏面電極層とを備えた回路検査端子付き角形
チップ抵抗器。3. An insulating rectangular plate-shaped ceramic substrate, a pair of upper surface electrode layers formed in the longitudinal direction on the ceramic substrate, a resistance layer overlapping a part of the pair of upper surface electrode layers, A protective layer that completely covers the resistance layer, a pair of side surface electrode layers that overlap a part of the upper surface electrode layer, and a surface of the surface on which the upper surface electrode layer is formed. A rectangular chip resistor with a circuit inspection terminal, comprising a back electrode layer for circuit inspection, which is electrically connected to any one of a pair of side surface electrode layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06201992A JP3111823B2 (en) | 1994-08-26 | 1994-08-26 | Square chip resistor with circuit inspection terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06201992A JP3111823B2 (en) | 1994-08-26 | 1994-08-26 | Square chip resistor with circuit inspection terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0864403A true JPH0864403A (en) | 1996-03-08 |
| JP3111823B2 JP3111823B2 (en) | 2000-11-27 |
Family
ID=16450154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06201992A Expired - Fee Related JP3111823B2 (en) | 1994-08-26 | 1994-08-26 | Square chip resistor with circuit inspection terminal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3111823B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008053255A (en) * | 2006-08-22 | 2008-03-06 | Taiyosha Electric Co Ltd | Chip resistor |
| JP2010050469A (en) * | 2009-10-16 | 2010-03-04 | Koa Corp | Method of manufacturing resistor for current detection |
| JP2017195323A (en) * | 2016-04-22 | 2017-10-26 | Koa株式会社 | Chip Resistor and Component Integrated Circuit Board |
| WO2022065246A1 (en) * | 2020-09-24 | 2022-03-31 | 株式会社村田製作所 | Electronic component module, and method for manufacturing electronic component module |
-
1994
- 1994-08-26 JP JP06201992A patent/JP3111823B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008053255A (en) * | 2006-08-22 | 2008-03-06 | Taiyosha Electric Co Ltd | Chip resistor |
| JP4699311B2 (en) * | 2006-08-22 | 2011-06-08 | 太陽社電気株式会社 | Chip resistor |
| JP2010050469A (en) * | 2009-10-16 | 2010-03-04 | Koa Corp | Method of manufacturing resistor for current detection |
| JP4542608B2 (en) * | 2009-10-16 | 2010-09-15 | コーア株式会社 | Manufacturing method of current detection resistor |
| JP2017195323A (en) * | 2016-04-22 | 2017-10-26 | Koa株式会社 | Chip Resistor and Component Integrated Circuit Board |
| WO2022065246A1 (en) * | 2020-09-24 | 2022-03-31 | 株式会社村田製作所 | Electronic component module, and method for manufacturing electronic component module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3111823B2 (en) | 2000-11-27 |
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